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author | Raghu Nambiath | 2017-03-03 14:08:02 -0600 |
---|---|---|
committer | Raghu Nambiath | 2017-03-03 14:08:02 -0600 |
commit | 72fe9dc35b9e128a95b4e3e4403cb197616e2e88 (patch) | |
tree | 5c40a8f252d9a4c3f34c4cbbb560841527ac1819 | |
parent | 135ce92e3bb8724e81fc8d035986eb4feec2a0ff (diff) | |
parent | 90bc94d9279207c64dc3a17619d95c5f4d8d8f93 (diff) | |
download | qmss-lld-72fe9dc35b9e128a95b4e3e4403cb197616e2e88.tar.gz qmss-lld-72fe9dc35b9e128a95b4e3e4403cb197616e2e88.tar.xz qmss-lld-72fe9dc35b9e128a95b4e3e4403cb197616e2e88.zip |
Merge pull request #3 in PROCESSOR-SDK/qmss-lld from review-prsdk-1892 to masterDEV.QMSS_LLD.02.01.00.15A
* commit '90bc94d9279207c64dc3a17619d95c5f4d8d8f93':
resolved compilation and functionality issues for accumulator tests
-rw-r--r-- | .gitignore | 2 | ||||
-rw-r--r-- | test/k2h/c66/bios/qmAccK2HC66BiosTestProject.txt | 3 | ||||
-rw-r--r-- | test/k2h/c66/bios/qmss_testAccK2.cfg | 3 | ||||
-rw-r--r-- | test/src/test_acc.c | 1366 |
4 files changed, 711 insertions, 663 deletions
@@ -30,6 +30,6 @@ firmware/src/*_[bl]e_v?.txt | |||
30 | firmware/src/*_[bl]e_v?.bib | 30 | firmware/src/*_[bl]e_v?.bib |
31 | firmware/src/*_[bl]e_v?_bin.h | 31 | firmware/src/*_[bl]e_v?_bin.h |
32 | analysis/ | 32 | analysis/ |
33 | test/*/c66/bios/src | 33 | test/*/*/bios/src |
34 | Debug/ | 34 | Debug/ |
35 | Release/ | 35 | Release/ |
diff --git a/test/k2h/c66/bios/qmAccK2HC66BiosTestProject.txt b/test/k2h/c66/bios/qmAccK2HC66BiosTestProject.txt index 9e23578..4b04242 100644 --- a/test/k2h/c66/bios/qmAccK2HC66BiosTestProject.txt +++ b/test/k2h/c66/bios/qmAccK2HC66BiosTestProject.txt | |||
@@ -4,7 +4,8 @@ | |||
4 | -ccs.linkFile "PDK_INSTALL_PATH/ti/drv/qmss/src/qmss_acc.c" | 4 | -ccs.linkFile "PDK_INSTALL_PATH/ti/drv/qmss/src/qmss_acc.c" |
5 | -ccs.linkFile "PDK_INSTALL_PATH/ti/drv/qmss/src/qmss_qos.c" | 5 | -ccs.linkFile "PDK_INSTALL_PATH/ti/drv/qmss/src/qmss_qos.c" |
6 | -ccs.linkFile "PDK_INSTALL_PATH/ti/drv/qmss/device/k2h/src/qmss_device.c" | 6 | -ccs.linkFile "PDK_INSTALL_PATH/ti/drv/qmss/device/k2h/src/qmss_device.c" |
7 | -ccs.linkFile "PDK_INSTALL_PATH/ti/drv/qmss/test/k2h/c66/bios/test_osal.c" | 7 | -ccs.linkFile "PDK_INSTALL_PATH/ti/drv/cppi/device/k2h/src/cppi_device.c" |
8 | -ccs.linkFile "PDK_INSTALL_PATH/ti/drv/qmss/test/k2h/c66/bios/test_osal_with_cppi.c" | ||
8 | -ccs.linkFile "PDK_INSTALL_PATH/ti/drv/qmss/test/k2h/c66/bios/qmss_testAccK2.cfg" | 9 | -ccs.linkFile "PDK_INSTALL_PATH/ti/drv/qmss/test/k2h/c66/bios/qmss_testAccK2.cfg" |
9 | -ccs.setCompilerOptions "-mv64+ -g -DSOC_K2H --diag_warning=225 -I${PDK_INSTALL_PATH}/ti/drv/qmss/test/src" | 10 | -ccs.setCompilerOptions "-mv64+ -g -DSOC_K2H --diag_warning=225 -I${PDK_INSTALL_PATH}/ti/drv/qmss/test/src" |
10 | -rtsc.enableRtsc | 11 | -rtsc.enableRtsc |
diff --git a/test/k2h/c66/bios/qmss_testAccK2.cfg b/test/k2h/c66/bios/qmss_testAccK2.cfg index 1181e18..90eed1a 100644 --- a/test/k2h/c66/bios/qmss_testAccK2.cfg +++ b/test/k2h/c66/bios/qmss_testAccK2.cfg | |||
@@ -31,6 +31,9 @@ var osType = "tirtos" | |||
31 | var Osal = xdc.loadPackage('ti.osal'); | 31 | var Osal = xdc.loadPackage('ti.osal'); |
32 | Osal.Settings.osType = osType; | 32 | Osal.Settings.osType = osType; |
33 | 33 | ||
34 | /* Load and use the CPPI package */ | ||
35 | var Cppi = xdc.loadPackage('ti.drv.cppi'); | ||
36 | |||
34 | var System = xdc.useModule('xdc.runtime.System'); | 37 | var System = xdc.useModule('xdc.runtime.System'); |
35 | var SysStd = xdc.useModule('xdc.runtime.SysStd'); | 38 | var SysStd = xdc.useModule('xdc.runtime.SysStd'); |
36 | System.SupportProxy = SysStd; | 39 | System.SupportProxy = SysStd; |
diff --git a/test/src/test_acc.c b/test/src/test_acc.c index e29be1c..571efb6 100644 --- a/test/src/test_acc.c +++ b/test/src/test_acc.c | |||
@@ -6,7 +6,7 @@ | |||
6 | * | 6 | * |
7 | * \par | 7 | * \par |
8 | * ============================================================================ | 8 | * ============================================================================ |
9 | * @n (C) Copyright 2014-2016, Texas Instruments, Inc. | 9 | * @n (C) Copyright 2014-2017, Texas Instruments, Inc. |
10 | * | 10 | * |
11 | * Redistribution and use in source and binary forms, with or without | 11 | * Redistribution and use in source and binary forms, with or without |
12 | * modification, are permitted provided that the following conditions | 12 | * modification, are permitted provided that the following conditions |
@@ -59,58 +59,76 @@ | |||
59 | 59 | ||
60 | /* CSL RL includes */ | 60 | /* CSL RL includes */ |
61 | #include <ti/csl/csl_chip.h> | 61 | #include <ti/csl/csl_chip.h> |
62 | #ifdef _TMS320C6X | ||
62 | #include <ti/csl/csl_cacheAux.h> | 63 | #include <ti/csl/csl_cacheAux.h> |
64 | #endif | ||
65 | /* Queue Reclamation test and firmware is verfied | ||
66 | * is done only on K2H SoC as the firmware is | ||
67 | * same for all the devices and no need to test | ||
68 | * on all possible SoCs | ||
69 | */ | ||
70 | #if defined(DEVICE_K2H) || defined(SOC_K2H) | ||
63 | 71 | ||
64 | #if defined(DEVICE_K2H) || defined(SOC_K2H) || \ | 72 | #ifdef _TMS320C6X |
65 | defined(DEVICE_K2K) || defined(SOC_K2K) || \ | ||
66 | defined(DEVICE_K2L) || defined(SOC_K2L) || \ | ||
67 | defined(DEVICE_K2E) || defined(SOC_K2E) | ||
68 | |||
69 | /* CPPI LLD include */ | 73 | /* CPPI LLD include */ |
70 | #include <ti/drv/cppi/cppi_drv.h> | 74 | #include <ti/drv/cppi/cppi_drv.h> |
71 | #include <ti/drv/cppi/cppi_desc.h> | 75 | #include <ti/drv/cppi/cppi_desc.h> |
72 | #include <cppi_osal.h> | 76 | #include <ti/drv/cppi/test/src/cppi_osal.h> |
73 | 77 | ||
74 | #include <ti/osal/CacheP.h> | 78 | #include <ti/osal/CacheP.h> |
75 | IHeap_Handle cppiHeap; | 79 | IHeap_Handle cppiHeap; |
76 | 80 | ||
77 | //The following definitions are for the barrier usage test | 81 | //The following definitions are for the barrier usage test |
78 | #define ACC_Q 704 | 82 | #define ACC_Q 704 |
79 | #define ACC_FDQ 750 | 83 | #define ACC_FDQ 750 |
80 | #define TX_Q 800 | 84 | #define TX_Q 800 |
81 | #define TX_FREE_Q 1000 | 85 | #define TX_FREE_Q 1000 |
82 | #define RX_FREE_Q 2000 | 86 | #define RX_FREE_Q 2000 |
83 | #define BARRIER_Q 2100 | 87 | #define BARRIER_Q 2100 |
84 | #define DEST_Q 2200 | 88 | #define DEST_Q 2200 |
85 | #define BAD_Q 2300 | 89 | #define BAD_Q 2300 |
86 | #define BARRIER_PKTS 100000 | 90 | #define BARRIER_PKTS 100000 |
87 | #define DESC_ADDR (uint32_t *)0x60000000 /* DDR3B */ | 91 | #define DESC_ADDR (uint32_t *)0x60000000 /* DDR3B */ |
88 | #define DESC_BUF_ADDR (uint8_t *)0x70000000 /* DDR3B */ | 92 | #define DESC_BUF_ADDR (uint8_t *)0x70000000 /* DDR3B */ |
89 | #define DESC_BUF_SIZE 2048 /* bytes */ | 93 | #define DESC_BUF_SIZE 2048 /* bytes */ |
90 | #define BENCH_BUF_SIZE 16 | 94 | #define BENCH_BUF_SIZE 16 |
91 | 95 | ||
92 | #define CLOCKS_PER_PERIOD 98304 /* assuming 983Mhz CPU, this is a 0.1ms period */ | 96 | #define CLOCKS_PER_PERIOD 98304 /* assuming 983Mhz CPU, this is a 0.1ms period */ |
93 | #define PERIODS_PER_SEC 10000 | 97 | #define PERIODS_PER_SEC 10000 |
94 | 98 | ||
95 | /* CPDMA configuration */ | 99 | /* CPDMA configuration */ |
96 | Cppi_CpDmaInitCfg cpdmaCfg; | 100 | Cppi_CpDmaInitCfg cpdmaCfg; |
97 | /* Tx channel configuration */ | 101 | /* Tx channel configuration */ |
98 | Cppi_TxChInitCfg txChCfg; | 102 | Cppi_TxChInitCfg txChCfg; |
99 | Cppi_ChHnd txChHnd; | 103 | Cppi_ChHnd txChHnd; |
100 | /* Rx channel configuration */ | 104 | /* Rx channel configuration */ |
101 | Cppi_RxChInitCfg rxChCfg; | 105 | Cppi_RxChInitCfg rxChCfg; |
102 | Cppi_ChHnd rxChHnd; | 106 | Cppi_ChHnd rxChHnd; |
103 | /* Rx flow configuration */ | 107 | /* Rx flow configuration */ |
104 | Cppi_RxFlowCfg rxFlowCfg; | 108 | Cppi_RxFlowCfg rxFlowCfg; |
105 | /* CPPI device specific configuration */ | 109 | /* CPPI device specific configuration */ |
106 | extern Cppi_GlobalConfigParams cppiGblCfgParams; | 110 | extern Cppi_GlobalConfigParams cppiGblCfgParams; |
107 | 111 | ||
108 | #endif //If a K2 device | 112 | #endif /* C66x */ |
113 | #else | ||
114 | /************************ USER DEFINES ********************/ | ||
109 | 115 | ||
116 | #define NUM_DATA_BUFFER 32 | ||
117 | #define SIZE_DATA_BUFFER 64 | ||
110 | 118 | ||
111 | /************************ USER DEFINES ********************/ | 119 | #define MAPPED_VIRTUAL_ADDRESS 0x81000000 |
120 | |||
121 | /* MPAX segment 2 registers */ | ||
122 | #define XMPAXL2 0x08000010 | ||
123 | #define XMPAXH2 0x08000014 | ||
124 | |||
125 | #endif //If a K2 device | ||
126 | |||
127 | /*********** USER DEFINES for all SoCs *********************/ | ||
112 | #define NUM_HOST_DESC (256) | 128 | #define NUM_HOST_DESC (256) |
113 | #define SIZE_HOST_DESC (64) | 129 | #define SIZE_HOST_DESC (64) |
130 | #define NUM_MONOLITHIC_DESC 256 | ||
131 | #define SIZE_MONOLITHIC_DESC 160 | ||
114 | 132 | ||
115 | 133 | ||
116 | 134 | ||
@@ -173,41 +191,33 @@ static uint32_t l2_global_address (uint32_t addr) | |||
173 | #endif | 191 | #endif |
174 | } | 192 | } |
175 | 193 | ||
176 | /* These only apply to K2 devices */ | 194 | /* These only apply to K2H devices */ |
177 | #if defined(DEVICE_K2H) || defined(SOC_K2H) || \ | 195 | #if defined(DEVICE_K2H) || defined(SOC_K2H) |
178 | defined(DEVICE_K2K) || defined(SOC_K2K) || \ | ||
179 | defined(DEVICE_K2L) || defined(SOC_K2L) || \ | ||
180 | defined(DEVICE_K2E) || defined(SOC_K2E) | ||
181 | 196 | ||
182 | #ifdef _TMS320C6X | 197 | #ifdef _TMS320C6X |
183 | #pragma DATA_ALIGN (hostDescBuf, 128) | 198 | #pragma DATA_ALIGN (hostDescBuf, 128); |
184 | #pragma DATA_SECTION (hostDescBuf, ".far:hostDescBuf") | 199 | #pragma DATA_SECTION (hostDescBuf, ".far:hostDescBuf"); |
185 | #endif | 200 | uint8_t hostDescBuf[SIZE_HOST_DESC * NUM_HOST_DESC]; |
186 | uint8_t hostDescBuf[SIZE_HOST_DESC * NUM_HOST_DESC] | 201 | |
187 | #ifndef _TMS320C6X | 202 | |
188 | __attribute__ ((aligned (64)), section(".far:hostDescBuf")) | 203 | /* This function reads a QMSS INTD Int Count Register. |
189 | #endif | 204 | * Reading has no effect on the register. |
190 | ; /* hostDescBuf */ | 205 | * "intnum" is: 0..31 for High Pri interrupts |
191 | 206 | * 32..47 for Low Pri interrupts | |
192 | 207 | * 48..49 for PKTDMA Starvation interrupts | |
193 | /* This function reads a QMSS INTD Int Count Register. | 208 | */ |
194 | * Reading has no effect on the register. | 209 | uint32_t intd_read_intcount(uint32_t intd, uint32_t intnum) |
195 | * "intnum" is: 0..31 for High Pri interrupts | 210 | { |
196 | * 32..47 for Low Pri interrupts | 211 | uint32_t *reg; |
197 | * 48..49 for PKTDMA Starvation interrupts | 212 | uint32_t value; |
198 | */ | 213 | uint32_t offset = (intd - 1) * 0x100 + 0x300 + (intnum * 4); |
199 | uint32_t intd_read_intcount(uint32_t intd, uint32_t intnum) | 214 | |
200 | { | 215 | reg = (uint32_t *)(CSL_QMSS_CFG_INTD_1_REGS + offset); |
201 | uint32_t *reg; | 216 | |
202 | uint32_t value; | 217 | value = *reg; |
203 | uint32_t offset = (intd - 1) * 0x100 + 0x300 + (intnum * 4); | 218 | |
204 | 219 | return(value); | |
205 | reg = (uint32_t *)(CSL_QMSS_CFG_INTD_1_REGS + offset); | 220 | } |
206 | |||
207 | value = *reg; | ||
208 | |||
209 | return(value); | ||
210 | } | ||
211 | 221 | ||
212 | 222 | ||
213 | void benchmark_barrier (Qmss_QueueHnd freeQ, Qmss_QueueHnd barrierQ, const char *name) | 223 | void benchmark_barrier (Qmss_QueueHnd freeQ, Qmss_QueueHnd barrierQ, const char *name) |
@@ -232,19 +242,19 @@ void benchmark_barrier (Qmss_QueueHnd freeQ, Qmss_QueueHnd barrierQ, const char | |||
232 | System_printf ("Took %d cycles to move 10000 descs through %s barrier\n", (int)(stop - start), name); | 242 | System_printf ("Took %d cycles to move 10000 descs through %s barrier\n", (int)(stop - start), name); |
233 | System_printf ("Assuming 983Mhz clock, this is %d desc/sec\n", 983000000 / ((stop - start) / 10000)); | 243 | System_printf ("Assuming 983Mhz clock, this is %d desc/sec\n", 983000000 / ((stop - start) / 10000)); |
234 | } | 244 | } |
235 | 245 | ||
236 | 246 | ||
237 | extern uint32_t errorCount; | 247 | extern uint32_t errorCount; |
238 | 248 | ||
239 | /* This function is written to produce a single benchmark, depending on these | 249 | /* This function is written to produce a single benchmark, depending on these |
240 | * macros: | 250 | * macros: |
241 | * NO_ACCUMULATOR - If defined, the Accumulator is bypassed, allowing timing of | 251 | * NO_ACCUMULATOR - If defined, the Accumulator is bypassed, allowing timing of |
242 | * the barrier processing in isolation. | 252 | * the barrier processing in isolation. |
243 | * NO_BARRIER - If defined, the barrier queue is not programmed. Allows timing of | 253 | * NO_BARRIER - If defined, the barrier queue is not programmed. Allows timing of |
244 | * Accumulator and pktDMA. | 254 | * Accumulator and pktDMA. |
245 | * ARM_CORE - Includes a check for descriptors arriving in the wrong destination | 255 | * ARM_CORE - Includes a check for descriptors arriving in the wrong destination |
246 | * queue. This does not happen on C66x, so it should not be defined. | 256 | * queue. This does not happen on C66x, so it should not be defined. |
247 | */ | 257 | */ |
248 | void benchmark_acc_with_barrier(void) | 258 | void benchmark_acc_with_barrier(void) |
249 | { | 259 | { |
250 | Qmss_Result reg0, reg1, retVal; | 260 | Qmss_Result reg0, reg1, retVal; |
@@ -270,71 +280,71 @@ void benchmark_acc_with_barrier(void) | |||
270 | uint8_t *buffAddr; | 280 | uint8_t *buffAddr; |
271 | uint32_t *desc; | 281 | uint32_t *desc; |
272 | uint32_t *list; | 282 | uint32_t *list; |
273 | Cppi_Handle cppiHnd; | 283 | Cppi_Handle cppiHnd; |
274 | Cppi_FlowHnd rxFlowHnd; | 284 | Cppi_FlowHnd rxFlowHnd; |
275 | Cppi_DescTag tag; | 285 | Cppi_DescTag tag; |
276 | Qmss_Queue que; | 286 | Qmss_Queue que; |
277 | Cppi_Result result; | 287 | Cppi_Result result; |
278 | 288 | ||
279 | /* Initialize CPPI LLD */ | 289 | /* Initialize CPPI LLD */ |
280 | result = Cppi_init (&cppiGblCfgParams); | 290 | result = Cppi_init (&cppiGblCfgParams); |
281 | if (result != CPPI_SOK) | 291 | if (result != CPPI_SOK) |
282 | { | 292 | { |
283 | System_printf ("Error : Initializing CPPI LLD error code : %d\n", result); | 293 | System_printf ("Error : Initializing CPPI LLD error code : %d\n", result); |
284 | errorCount++; | 294 | errorCount++; |
285 | } | 295 | } |
286 | 296 | ||
287 | /* Set up QMSS CPDMA configuration */ | 297 | /* Set up QMSS CPDMA configuration */ |
288 | memset ((void *) &cpdmaCfg, 0, sizeof (Cppi_CpDmaInitCfg)); | 298 | memset ((void *) &cpdmaCfg, 0, sizeof (Cppi_CpDmaInitCfg)); |
289 | cpdmaCfg.dmaNum = Cppi_CpDma_QMSS_CPDMA; | 299 | cpdmaCfg.dmaNum = Cppi_CpDma_QMSS_CPDMA; |
290 | 300 | ||
291 | /* Open QMSS CPDMA */ | 301 | /* Open QMSS CPDMA */ |
292 | cppiHnd = (Cppi_Handle) Cppi_open (&cpdmaCfg); | 302 | cppiHnd = (Cppi_Handle) Cppi_open (&cpdmaCfg); |
293 | if (cppiHnd == NULL) | 303 | if (cppiHnd == NULL) |
294 | { | 304 | { |
295 | errorCount++; | 305 | errorCount++; |
296 | System_printf ("Error : Initializing QMSS CPPI CPDMA %d\n", cpdmaCfg.dmaNum); | 306 | System_printf ("Error : Initializing QMSS CPPI CPDMA %d\n", cpdmaCfg.dmaNum); |
297 | return; | 307 | return; |
298 | } | 308 | } |
299 | 309 | ||
300 | rxChCfg.channelNum = 0; | 310 | rxChCfg.channelNum = 0; |
301 | rxChCfg.rxEnable = Cppi_ChState_CHANNEL_ENABLE; | 311 | rxChCfg.rxEnable = Cppi_ChState_CHANNEL_ENABLE; |
302 | rxChHnd = (Cppi_ChHnd) Cppi_rxChannelOpen (cppiHnd, &rxChCfg, &isAllocated); | 312 | rxChHnd = (Cppi_ChHnd) Cppi_rxChannelOpen (cppiHnd, &rxChCfg, &isAllocated); |
303 | if (rxChHnd == NULL) | 313 | if (rxChHnd == NULL) |
304 | { | 314 | { |
305 | System_printf ("Error : Opening Rx channel : %d\n", rxChCfg.channelNum); | 315 | System_printf ("Error : Opening Rx channel : %d\n", rxChCfg.channelNum); |
306 | errorCount++; | 316 | errorCount++; |
307 | } | 317 | } |
308 | 318 | ||
309 | txChCfg.channelNum = 0; | 319 | txChCfg.channelNum = 0; |
310 | txChCfg.txEnable = Cppi_ChState_CHANNEL_ENABLE; | 320 | txChCfg.txEnable = Cppi_ChState_CHANNEL_ENABLE; |
311 | txChHnd = (Cppi_ChHnd) Cppi_txChannelOpen (cppiHnd, &txChCfg, &isAllocated); | 321 | txChHnd = (Cppi_ChHnd) Cppi_txChannelOpen (cppiHnd, &txChCfg, &isAllocated); |
312 | if (txChHnd == NULL) | 322 | if (txChHnd == NULL) |
313 | { | 323 | { |
314 | System_printf ("Error : Opening Tx channel : %d\n", txChCfg.channelNum); | 324 | System_printf ("Error : Opening Tx channel : %d\n", txChCfg.channelNum); |
315 | errorCount++; | 325 | errorCount++; |
316 | } | 326 | } |
317 | 327 | ||
318 | /* Configure Rx flow 0 */ | 328 | /* Configure Rx flow 0 */ |
319 | memset ((void *) &rxFlowCfg, 0, sizeof (Cppi_RxFlowCfg)); | 329 | memset ((void *) &rxFlowCfg, 0, sizeof (Cppi_RxFlowCfg)); |
320 | rxFlowCfg.rx_dest_qmgr = 0; | 330 | rxFlowCfg.rx_dest_qmgr = 0; |
321 | rxFlowCfg.rx_dest_qnum = BARRIER_Q; | 331 | rxFlowCfg.rx_dest_qnum = BARRIER_Q; |
322 | rxFlowCfg.rx_dest_tag_hi = DEST_Q >> 8; //This will be read by the Acc firmware | 332 | rxFlowCfg.rx_dest_tag_hi = DEST_Q >> 8; //This will be read by the Acc firmware |
323 | rxFlowCfg.rx_dest_tag_lo = DEST_Q & 0xff; | 333 | rxFlowCfg.rx_dest_tag_lo = DEST_Q & 0xff; |
324 | rxFlowCfg.rx_dest_tag_lo_sel = 1; | 334 | rxFlowCfg.rx_dest_tag_lo_sel = 1; |
325 | rxFlowCfg.rx_dest_tag_hi_sel = 1; | 335 | rxFlowCfg.rx_dest_tag_hi_sel = 1; |
326 | rxFlowCfg.rx_fdq0_sz0_qmgr = 0; | 336 | rxFlowCfg.rx_fdq0_sz0_qmgr = 0; |
327 | rxFlowCfg.rx_fdq0_sz0_qnum = RX_FREE_Q; | 337 | rxFlowCfg.rx_fdq0_sz0_qnum = RX_FREE_Q; |
328 | rxFlowCfg.rx_fdq1_qmgr = 0; | 338 | rxFlowCfg.rx_fdq1_qmgr = 0; |
329 | rxFlowCfg.rx_fdq1_qnum = RX_FREE_Q; | 339 | rxFlowCfg.rx_fdq1_qnum = RX_FREE_Q; |
330 | rxFlowCfg.rx_psinfo_present = 1; | 340 | rxFlowCfg.rx_psinfo_present = 1; |
331 | rxFlowHnd = (Cppi_FlowHnd) Cppi_configureRxFlow (cppiHnd, &rxFlowCfg, &isAllocated); | 341 | rxFlowHnd = (Cppi_FlowHnd) Cppi_configureRxFlow (cppiHnd, &rxFlowCfg, &isAllocated); |
332 | if (rxFlowHnd == NULL) | 342 | if (rxFlowHnd == NULL) |
333 | { | 343 | { |
334 | System_printf ("Error : Opening Rx flow : %d\n", rxFlowCfg.flowIdNum); | 344 | System_printf ("Error : Opening Rx flow : %d\n", rxFlowCfg.flowIdNum); |
335 | errorCount++; | 345 | errorCount++; |
336 | } | 346 | } |
337 | 347 | ||
338 | /* Setup memory region for barrier host descriptors */ | 348 | /* Setup memory region for barrier host descriptors */ |
339 | memInfo.descBase = DESC_ADDR; | 349 | memInfo.descBase = DESC_ADDR; |
340 | memset ((void *) memInfo.descBase, 0, (SIZE_HOST_DESC * NUM_HOST_DESC)); | 350 | memset ((void *) memInfo.descBase, 0, (SIZE_HOST_DESC * NUM_HOST_DESC)); |
@@ -351,7 +361,7 @@ void benchmark_acc_with_barrier(void) | |||
351 | System_printf ("Error : Inserting memory region %d error code : %d\n", memInfo.memRegion, reg0); | 361 | System_printf ("Error : Inserting memory region %d error code : %d\n", memInfo.memRegion, reg0); |
352 | errorCount++; | 362 | errorCount++; |
353 | } | 363 | } |
354 | 364 | ||
355 | /* Setup memory region for accumulator host descriptors */ | 365 | /* Setup memory region for accumulator host descriptors */ |
356 | memInfo.descBase = (uint32_t *) l2_global_address ((uint32_t) hostDescBuf); | 366 | memInfo.descBase = (uint32_t *) l2_global_address ((uint32_t) hostDescBuf); |
357 | memset ((void *) memInfo.descBase, 0, (SIZE_HOST_DESC * NUM_HOST_DESC)); | 367 | memset ((void *) memInfo.descBase, 0, (SIZE_HOST_DESC * NUM_HOST_DESC)); |
@@ -388,7 +398,7 @@ void benchmark_acc_with_barrier(void) | |||
388 | errorCount++; | 398 | errorCount++; |
389 | return; | 399 | return; |
390 | } | 400 | } |
391 | 401 | ||
392 | //Move half the descriptors to RX_FREE_Q | 402 | //Move half the descriptors to RX_FREE_Q |
393 | if ((rxfdq = Qmss_queueOpen(Qmss_QueueType_GENERAL_PURPOSE_QUEUE, | 403 | if ((rxfdq = Qmss_queueOpen(Qmss_QueueType_GENERAL_PURPOSE_QUEUE, |
394 | RX_FREE_Q, &isAllocated)) < QMSS_SOK) | 404 | RX_FREE_Q, &isAllocated)) < QMSS_SOK) |
@@ -396,46 +406,46 @@ void benchmark_acc_with_barrier(void) | |||
396 | System_printf ("Error: Failed to open Rx Free queue: %d\n", rxfdq); | 406 | System_printf ("Error: Failed to open Rx Free queue: %d\n", rxfdq); |
397 | errorCount++; | 407 | errorCount++; |
398 | return; | 408 | return; |
399 | } | 409 | } |
400 | 410 | ||
401 | tag.srcTagHi = 0; | 411 | tag.srcTagHi = 0; |
402 | tag.srcTagLo = 0; | 412 | tag.srcTagLo = 0; |
403 | tag.destTagHi = BAD_Q >> 8; | 413 | tag.destTagHi = BAD_Q >> 8; |
404 | tag.destTagLo = BAD_Q & 0xff; | 414 | tag.destTagLo = BAD_Q & 0xff; |
405 | que.qMgr = 0; | 415 | que.qMgr = 0; |
406 | que.qNum = DEST_Q; | 416 | que.qNum = DEST_Q; |
407 | buffAddr = DESC_BUF_ADDR + (NUM_HOST_DESC/2 * BENCH_BUF_SIZE); | 417 | buffAddr = DESC_BUF_ADDR + (NUM_HOST_DESC/2 * BENCH_BUF_SIZE); |
408 | 418 | ||
409 | for (cnt = 0; cnt < NUM_HOST_DESC/2; cnt++) | 419 | for (cnt = 0; cnt < NUM_HOST_DESC/2; cnt++) |
410 | { | 420 | { |
411 | desc = (uint32_t *)QMSS_DESC_PTR (Qmss_queuePop (TX_FREE_Q)); | 421 | desc = (uint32_t *)QMSS_DESC_PTR (Qmss_queuePop (TX_FREE_Q)); |
412 | if (desc) | 422 | if (desc) |
413 | { | 423 | { |
414 | Cppi_setOriginalBufInfo(Cppi_DescType_HOST, (Cppi_Desc *)desc, | 424 | Cppi_setOriginalBufInfo(Cppi_DescType_HOST, (Cppi_Desc *)desc, |
415 | buffAddr, BENCH_BUF_SIZE); | 425 | buffAddr, BENCH_BUF_SIZE); |
416 | Cppi_setTag (Cppi_DescType_HOST, (Cppi_Desc *)desc, &tag); | 426 | Cppi_setTag (Cppi_DescType_HOST, (Cppi_Desc *)desc, &tag); |
417 | Cppi_setReturnQueue (Cppi_DescType_HOST, (Cppi_Desc *)desc, que); | 427 | Cppi_setReturnQueue (Cppi_DescType_HOST, (Cppi_Desc *)desc, que); |
418 | Qmss_queuePushDesc (RX_FREE_Q, desc); | 428 | Qmss_queuePushDesc (RX_FREE_Q, desc); |
419 | } | 429 | } |
420 | buffAddr += BENCH_BUF_SIZE; | 430 | buffAddr += BENCH_BUF_SIZE; |
421 | } | 431 | } |
422 | 432 | ||
423 | //Update the descriptors in TX_FREE_Q | 433 | //Update the descriptors in TX_FREE_Q |
424 | que.qMgr = 0; | 434 | que.qMgr = 0; |
425 | que.qNum = TX_FREE_Q; | 435 | que.qNum = TX_FREE_Q; |
426 | buffAddr = DESC_BUF_ADDR; | 436 | buffAddr = DESC_BUF_ADDR; |
427 | 437 | ||
428 | for (cnt = 0; cnt < NUM_HOST_DESC; cnt++) | 438 | for (cnt = 0; cnt < NUM_HOST_DESC; cnt++) |
429 | { | 439 | { |
430 | /* Put freeQ in dest tag */ | 440 | /* Put freeQ in dest tag */ |
431 | desc = (uint32_t *)QMSS_DESC_PTR (Qmss_queuePop (TX_FREE_Q)); | 441 | desc = (uint32_t *)QMSS_DESC_PTR (Qmss_queuePop (TX_FREE_Q)); |
432 | if (desc) | 442 | if (desc) |
433 | { | 443 | { |
434 | Cppi_setData (Cppi_DescType_HOST, (Cppi_Desc *)desc, | 444 | Cppi_setData (Cppi_DescType_HOST, (Cppi_Desc *)desc, |
435 | buffAddr, BENCH_BUF_SIZE); | 445 | buffAddr, BENCH_BUF_SIZE); |
436 | Cppi_setPacketLen (Cppi_DescType_HOST, (Cppi_Desc *)desc, BENCH_BUF_SIZE); | 446 | Cppi_setPacketLen (Cppi_DescType_HOST, (Cppi_Desc *)desc, BENCH_BUF_SIZE); |
437 | Cppi_setReturnQueue (Cppi_DescType_HOST, (Cppi_Desc *)desc, que); | 447 | Cppi_setReturnQueue (Cppi_DescType_HOST, (Cppi_Desc *)desc, que); |
438 | Cppi_setPSLen (Cppi_DescType_HOST, (Cppi_Desc *)desc, 4); | 448 | Cppi_setPSLen (Cppi_DescType_HOST, (Cppi_Desc *)desc, 4); |
439 | Qmss_queuePushDesc (TX_FREE_Q, desc); | 449 | Qmss_queuePushDesc (TX_FREE_Q, desc); |
440 | } | 450 | } |
441 | else | 451 | else |
@@ -466,7 +476,7 @@ void benchmark_acc_with_barrier(void) | |||
466 | errorCount++; | 476 | errorCount++; |
467 | return; | 477 | return; |
468 | } | 478 | } |
469 | 479 | ||
470 | //Open the Accumulator's queue to monitor | 480 | //Open the Accumulator's queue to monitor |
471 | if ((accQ = Qmss_queueOpen(Qmss_QueueType_GENERAL_PURPOSE_QUEUE, | 481 | if ((accQ = Qmss_queueOpen(Qmss_QueueType_GENERAL_PURPOSE_QUEUE, |
472 | ACC_Q, &isAllocated)) < QMSS_SOK) | 482 | ACC_Q, &isAllocated)) < QMSS_SOK) |
@@ -474,13 +484,13 @@ void benchmark_acc_with_barrier(void) | |||
474 | System_printf ("Error: Failed to open Acc queue: %d\n", accQ); | 484 | System_printf ("Error: Failed to open Acc queue: %d\n", accQ); |
475 | errorCount++; | 485 | errorCount++; |
476 | return; | 486 | return; |
477 | } | 487 | } |
478 | 488 | ||
479 | memset ((void *) &hiPrioList, 0, sizeof (hiPrioList)); | 489 | memset ((void *) &hiPrioList, 0, sizeof (hiPrioList)); |
480 | cfg.channel = 0; | 490 | cfg.channel = 0; |
481 | cfg.command = Qmss_AccCmd_ENABLE_CHANNEL; | 491 | cfg.command = Qmss_AccCmd_ENABLE_CHANNEL; |
482 | cfg.queueEnMask = 0; | 492 | cfg.queueEnMask = 0; |
483 | cfg.listAddress = l2_global_address ((uint32_t) hiPrioList); | 493 | cfg.listAddress = l2_global_address ((uint32_t) hiPrioList); |
484 | /* Get queue manager and queue number from handle */ | 494 | /* Get queue manager and queue number from handle */ |
485 | cfg.queMgrIndex = Qmss_getQIDFromHandle (accQ); | 495 | cfg.queMgrIndex = Qmss_getQIDFromHandle (accQ); |
486 | cfg.maxPageEntries = 16 + 1; | 496 | cfg.maxPageEntries = 16 + 1; |
@@ -496,7 +506,7 @@ void benchmark_acc_with_barrier(void) | |||
496 | cfg.channel, cfg.queMgrIndex, result); | 506 | cfg.channel, cfg.queMgrIndex, result); |
497 | errorCount++; | 507 | errorCount++; |
498 | } | 508 | } |
499 | 509 | ||
500 | /* Write back the DDR */ | 510 | /* Write back the DDR */ |
501 | // CacheP_wb (hostDescBuf, sizeof(hostDescBuf)); | 511 | // CacheP_wb (hostDescBuf, sizeof(hostDescBuf)); |
502 | 512 | ||
@@ -523,187 +533,188 @@ void benchmark_acc_with_barrier(void) | |||
523 | errorCount++; | 533 | errorCount++; |
524 | return; | 534 | return; |
525 | } | 535 | } |
526 | 536 | ||
527 | #ifndef NO_BARRIER | 537 | #ifndef NO_BARRIER |
528 | if ((retVal = Qmss_programDDRBarrierQueue (Qmss_PdspId_PDSP1, ddrQ)) != QMSS_ACC_SOK) | 538 | retVal = Qmss_programDDRBarrierQueue (Qmss_PdspId_PDSP1, ddrQ, 0); |
539 | if (retVal != QMSS_ACC_SOK) | ||
529 | { | 540 | { |
530 | System_printf ("Error: failed to program DDR barrier queue: %d\n", retVal); | 541 | System_printf ("Error: failed to program DDR barrier queue: %d\n", retVal); |
531 | errorCount++; | 542 | errorCount++; |
532 | return; | 543 | return; |
533 | } | 544 | } |
534 | #endif | 545 | #endif |
535 | 546 | ||
536 | iter = 0; | 547 | iter = 0; |
537 | err1_cnt = 0; | 548 | err1_cnt = 0; |
538 | err2_cnt = 0; | 549 | err2_cnt = 0; |
539 | pingpong = 0; | 550 | pingpong = 0; |
540 | acc_pkts = bar_pkts= 0; | 551 | acc_pkts = bar_pkts= 0; |
541 | lat_sum = bar_sum = 0; | 552 | lat_sum = bar_sum = 0; |
542 | lat_min = bar_min = 0x7fffffff; | 553 | lat_min = bar_min = 0x7fffffff; |
543 | lat_max = bar_max = 0; | 554 | lat_max = bar_max = 0; |
544 | TSCL = 0; //if this isn't the first set, it won't actually zero it. | 555 | TSCL = 0; //if this isn't the first set, it won't actually zero it. |
545 | TSCH = 0; | 556 | TSCH = 0; |
546 | 557 | ||
547 | start = TSCL; | 558 | start = TSCL; |
548 | next = start + CLOCKS_PER_PERIOD; | 559 | next = start + CLOCKS_PER_PERIOD; |
549 | 560 | ||
550 | while (iter < PERIODS_PER_SEC) //we will ignore the first two | 561 | while (iter < PERIODS_PER_SEC) //we will ignore the first two |
551 | { | 562 | { |
552 | //Since the main loop will iterate once each 0.1ms, pushing x descriptors | 563 | //Since the main loop will iterate once each 0.1ms, pushing x descriptors |
553 | //here will create a push rate of x0,000 descriptors per second. Set | 564 | //here will create a push rate of x0,000 descriptors per second. Set |
554 | //this loop limit to the maximum of desired Acc or Barrier packet rate. | 565 | //this loop limit to the maximum of desired Acc or Barrier packet rate. |
555 | for (idx = 0; idx < 20; idx++) | 566 | for (idx = 0; idx < 20; idx++) |
556 | { | 567 | { |
557 | #ifndef NO_BARRIER | 568 | #ifndef NO_BARRIER |
558 | //Push descriptors to the Tx pktDMA barrier, channel 0 | 569 | //Push descriptors to the Tx pktDMA barrier, channel 0 |
559 | if (idx < 20) | 570 | if (idx < 20) |
560 | { | 571 | { |
561 | desc = (uint32_t *)QMSS_DESC_PTR(Qmss_queuePop(TX_FREE_Q)); | 572 | desc = (uint32_t *)QMSS_DESC_PTR(Qmss_queuePop(TX_FREE_Q)); |
562 | if (desc) | 573 | if (desc) |
563 | { | 574 | { |
564 | desc[8] = TSCL; | 575 | desc[8] = TSCL; |
565 | Qmss_queuePushDescSizeRaw(TX_Q, desc, 48); | 576 | Qmss_queuePushDescSizeRaw(TX_Q, desc, 48); |
566 | } | 577 | } |
567 | else //count starvations | 578 | else //count starvations |
568 | err2_cnt ++; | 579 | err2_cnt ++; |
569 | } | 580 | } |
570 | #endif | 581 | #endif |
571 | 582 | ||
572 | #ifndef NO_ACCUMULATOR | 583 | #ifndef NO_ACCUMULATOR |
573 | //Push descriptors to the Accumulator. | 584 | //Push descriptors to the Accumulator. |
574 | if (idx < 5) | 585 | if (idx < 5) |
575 | { | 586 | { |
576 | desc = (uint32_t *)QMSS_DESC_PTR(Qmss_queuePop(ACC_FDQ)); | 587 | desc = (uint32_t *)QMSS_DESC_PTR(Qmss_queuePop(ACC_FDQ)); |
577 | //And tag descriptor PS word with the CPU time of the push. | 588 | //And tag descriptor PS word with the CPU time of the push. |
578 | if (desc) | 589 | if (desc) |
579 | { | 590 | { |
580 | desc[8] = TSCL; | 591 | desc[8] = TSCL; |
581 | Qmss_queuePushDesc (ACC_Q, desc); | 592 | Qmss_queuePushDesc (ACC_Q, desc); |
582 | } | 593 | } |
583 | else //count starvations | 594 | else //count starvations |
584 | err1_cnt ++; | 595 | err1_cnt ++; |
585 | } | 596 | } |
586 | #endif | 597 | #endif |
587 | } | 598 | } |
588 | 599 | ||
589 | //While waiting for this time period to elapse, check all the | 600 | //While waiting for this time period to elapse, check all the |
590 | //output queues and recycle appropriately. | 601 | //output queues and recycle appropriately. |
591 | 602 | ||
592 | cur_time = TSCL; | 603 | cur_time = TSCL; |
593 | while (cur_time < next) | 604 | while (cur_time < next) |
594 | { | 605 | { |
595 | #ifndef NO_ACCUMULATOR | 606 | #ifndef NO_ACCUMULATOR |
596 | uint32_t value; | 607 | uint32_t value; |
597 | 608 | ||
598 | //Check for an accumulator interrupt. | 609 | //Check for an accumulator interrupt. |
599 | value = intd_read_intcount(1, 0); | 610 | value = intd_read_intcount(1, 0); |
600 | if (value == 1) //an interrupt occurred | 611 | if (value == 1) //an interrupt occurred |
601 | { | 612 | { |
602 | if (pingpong == 0) //ping | 613 | if (pingpong == 0) //ping |
603 | { | 614 | { |
604 | list = &hiPrioList[0]; | 615 | list = &hiPrioList[0]; |
605 | pingpong = 1; | 616 | pingpong = 1; |
606 | } | 617 | } |
607 | else | 618 | else |
608 | { | 619 | { |
609 | list = &hiPrioList[17]; | 620 | list = &hiPrioList[17]; |
610 | pingpong = 0; | 621 | pingpong = 0; |
611 | } | 622 | } |
612 | 623 | ||
613 | cnt = list[0]; | 624 | cnt = list[0]; |
614 | for (idx = 0; idx < cnt; idx++) | 625 | for (idx = 0; idx < cnt; idx++) |
615 | { | 626 | { |
616 | desc = (uint32_t *)list[idx+1]; | 627 | desc = (uint32_t *)list[idx+1]; |
617 | if (desc) | 628 | if (desc) |
618 | { | 629 | { |
619 | cur_time = TSCL; | 630 | cur_time = TSCL; |
620 | desc_time = desc[8]; | 631 | desc_time = desc[8]; |
621 | 632 | ||
622 | lat_time = (uint32_t)(cur_time - desc_time); | 633 | lat_time = (uint32_t)(cur_time - desc_time); |
623 | lat_sum += lat_time; | 634 | lat_sum += lat_time; |
624 | if (lat_time < lat_min) | 635 | if (lat_time < lat_min) |
625 | lat_min = lat_time; | 636 | lat_min = lat_time; |
626 | if (lat_time > lat_max) | 637 | if (lat_time > lat_max) |
627 | lat_max = lat_time; | 638 | lat_max = lat_time; |
628 | 639 | ||
629 | acc_pkts ++; | 640 | acc_pkts ++; |
630 | Qmss_queuePushDesc (ACC_FDQ, desc); | 641 | Qmss_queuePushDesc (ACC_FDQ, desc); |
631 | } | 642 | } |
632 | } | 643 | } |
633 | 644 | ||
634 | //reset the interrupt. | 645 | //reset the interrupt. |
635 | result = Qmss_ackInterrupt (0, 1); | 646 | result = Qmss_ackInterrupt (0, 1); |
636 | result = Qmss_setEoiVectorByIntd (0, Qmss_IntdInterruptType_HIGH, 0); | 647 | result = Qmss_setEoiVectorByIntd (0, Qmss_IntdInterruptType_HIGH, 0); |
637 | } | 648 | } |
638 | #endif | 649 | #endif |
639 | 650 | ||
640 | #ifndef NO_BARRIER | 651 | #ifndef NO_BARRIER |
641 | //Process descriptors correctly arriving at the destination queue. | 652 | //Process descriptors correctly arriving at the destination queue. |
642 | cnt = Qmss_getQueueEntryCount(destQ); | 653 | cnt = Qmss_getQueueEntryCount(destQ); |
643 | for (idx = 0; idx < cnt; idx++) | 654 | for (idx = 0; idx < cnt; idx++) |
644 | { | 655 | { |
645 | desc = (uint32_t *)QMSS_DESC_PTR(Qmss_queuePop(DEST_Q)); | 656 | desc = (uint32_t *)QMSS_DESC_PTR(Qmss_queuePop(DEST_Q)); |
646 | if (desc) | 657 | if (desc) |
647 | { | 658 | { |
648 | //Write the illegal tag (bad queue number) back to the descriptor | 659 | //Write the illegal tag (bad queue number) back to the descriptor |
649 | tag.destTagHi = BAD_Q >> 8; | 660 | tag.destTagHi = BAD_Q >> 8; |
650 | tag.destTagLo = BAD_Q & 0xff; | 661 | tag.destTagLo = BAD_Q & 0xff; |
651 | Cppi_setTag (Cppi_DescType_HOST, (Cppi_Desc *)desc, &tag); | 662 | Cppi_setTag (Cppi_DescType_HOST, (Cppi_Desc *)desc, &tag); |
652 | 663 | ||
653 | cur_time = TSCL; | 664 | cur_time = TSCL; |
654 | desc_time = desc[8]; | 665 | desc_time = desc[8]; |
655 | 666 | ||
656 | lat_time = (uint32_t)(cur_time - desc_time); | 667 | lat_time = (uint32_t)(cur_time - desc_time); |
657 | bar_sum += lat_time; | 668 | bar_sum += lat_time; |
658 | if (lat_time < bar_min) | 669 | if (lat_time < bar_min) |
659 | bar_min = lat_time; | 670 | bar_min = lat_time; |
660 | if (lat_time > bar_max) | 671 | if (lat_time > bar_max) |
661 | bar_max = lat_time; | 672 | bar_max = lat_time; |
662 | 673 | ||
663 | bar_pkts ++; | 674 | bar_pkts ++; |
664 | Qmss_queuePushDesc (RX_FREE_Q, desc); | 675 | Qmss_queuePushDesc (RX_FREE_Q, desc); |
665 | } | 676 | } |
666 | } | 677 | } |
667 | 678 | ||
668 | #ifdef ARM_CORE | 679 | #ifdef ARM_CORE |
669 | //A descriptor arriving in this queue (badQ) indicates that the firmware | 680 | //A descriptor arriving in this queue (badQ) indicates that the firmware |
670 | //read the tag before the write from the Rx pktDMA had landed. This is | 681 | //read the tag before the write from the Rx pktDMA had landed. This is |
671 | //an error. This failure should not occur on a DSP core, only an ARM. | 682 | //an error. This failure should not occur on a DSP core, only an ARM. |
672 | cnt = Qmss_getQueueEntryCount(badQ); | 683 | cnt = Qmss_getQueueEntryCount(badQ); |
673 | for (idx = 0; idx < cnt; idx++) | 684 | for (idx = 0; idx < cnt; idx++) |
674 | { | 685 | { |
675 | desc = (uint32_t *)QMSS_DESC_PTR(Qmss_queuePop(BAD_Q)); | 686 | desc = (uint32_t *)QMSS_DESC_PTR(Qmss_queuePop(BAD_Q)); |
676 | if (desc) | 687 | if (desc) |
677 | { | 688 | { |
678 | err2_cnt ++; | 689 | err2_cnt ++; |
679 | 690 | ||
680 | //Make sure the bad queue number is back in the descriptor | 691 | //Make sure the bad queue number is back in the descriptor |
681 | tag.destTagHi = BAD_Q >> 8; | 692 | tag.destTagHi = BAD_Q >> 8; |
682 | tag.destTagLo = BAD_Q & 0xff; | 693 | tag.destTagLo = BAD_Q & 0xff; |
683 | Cppi_setTag (Cppi_DescType_HOST, (Cppi_Desc *)desc, &tag); | 694 | Cppi_setTag (Cppi_DescType_HOST, (Cppi_Desc *)desc, &tag); |
684 | Qmss_queuePushDesc (RX_FREE_Q, desc); | 695 | Qmss_queuePushDesc (RX_FREE_Q, desc); |
685 | } | 696 | } |
686 | } | 697 | } |
687 | #endif | 698 | #endif |
688 | #endif | 699 | #endif |
689 | cur_time = TSCL; | 700 | cur_time = TSCL; |
690 | } | 701 | } |
691 | 702 | ||
692 | next += CLOCKS_PER_PERIOD; | 703 | next += CLOCKS_PER_PERIOD; |
693 | iter ++; | 704 | iter ++; |
694 | } | 705 | } |
695 | 706 | ||
696 | stop = TSCL; | 707 | stop = TSCL; |
697 | lat_avg = lat_sum / acc_pkts; | 708 | lat_avg = lat_sum / acc_pkts; |
698 | bar_avg = bar_sum / bar_pkts; | 709 | bar_avg = bar_sum / bar_pkts; |
699 | 710 | ||
700 | if (err1_cnt > 0) | 711 | if (err1_cnt > 0) |
701 | System_printf ("Acc FDQ starved %d times\n", err1_cnt); | 712 | System_printf ("Acc FDQ starved %d times\n", err1_cnt); |
702 | 713 | ||
703 | if (err2_cnt > 0) | 714 | if (err2_cnt > 0) |
704 | System_printf ("Barrier FDQ starved %d times\n", err2_cnt); | 715 | System_printf ("Barrier FDQ starved %d times\n", err2_cnt); |
705 | 716 | ||
706 | System_printf ("Ran %d cycles, moved %d descs through Accumulator and %d through barrier\n", | 717 | System_printf ("Ran %d cycles, moved %d descs through Accumulator and %d through barrier\n", |
707 | (int)(stop - start), acc_pkts, bar_pkts); | 718 | (int)(stop - start), acc_pkts, bar_pkts); |
708 | System_printf ("Minimum Acc latency: %d \n", lat_min); | 719 | System_printf ("Minimum Acc latency: %d \n", lat_min); |
709 | System_printf ("Average Acc latency: %d \n", lat_avg); | 720 | System_printf ("Average Acc latency: %d \n", lat_avg); |
@@ -711,15 +722,15 @@ void benchmark_acc_with_barrier(void) | |||
711 | System_printf ("Minimum Bar latency: %d \n", bar_min); | 722 | System_printf ("Minimum Bar latency: %d \n", bar_min); |
712 | System_printf ("Average Bar latency: %d \n", bar_avg); | 723 | System_printf ("Average Bar latency: %d \n", bar_avg); |
713 | System_printf ("Maximum Bar latency: %d \n", bar_max); | 724 | System_printf ("Maximum Bar latency: %d \n", bar_max); |
714 | 725 | ||
715 | cnt = Qmss_getQueueEntryCount(rxfdq); | 726 | cnt = Qmss_getQueueEntryCount(rxfdq); |
716 | if (cnt != NUM_HOST_DESC/2) | 727 | if (cnt != NUM_HOST_DESC/2) |
717 | System_printf ("Error : Rx FDQ ended with %d descs, should be %d\n", cnt, NUM_HOST_DESC/2); | 728 | System_printf ("Error : Rx FDQ ended with %d descs, should be %d\n", cnt, NUM_HOST_DESC/2); |
718 | 729 | ||
719 | Qmss_queueEmpty(rxfdq); | 730 | Qmss_queueEmpty(rxfdq); |
720 | Qmss_queueEmpty(txfdq); | 731 | Qmss_queueEmpty(txfdq); |
721 | Qmss_queueEmpty(accfdq); | 732 | Qmss_queueEmpty(accfdq); |
722 | 733 | ||
723 | 734 | ||
724 | /* unprogram accumulator */ | 735 | /* unprogram accumulator */ |
725 | if ( (result = Qmss_disableAccumulator (Qmss_PdspId_PDSP1, cfg.channel)) != QMSS_ACC_SOK) | 736 | if ( (result = Qmss_disableAccumulator (Qmss_PdspId_PDSP1, cfg.channel)) != QMSS_ACC_SOK) |
@@ -729,7 +740,10 @@ void benchmark_acc_with_barrier(void) | |||
729 | } | 740 | } |
730 | 741 | ||
731 | /* Disable DDR Q */ | 742 | /* Disable DDR Q */ |
732 | if ((retVal = Qmss_programDDRBarrierQueue (Qmss_PdspId_PDSP1, 0)) != QMSS_ACC_SOK) | 743 | retVal = Qmss_programDDRBarrierQueue (Qmss_PdspId_PDSP1, 0, 0); |
744 | |||
745 | if (retVal != QMSS_ACC_SOK) | ||
746 | |||
733 | { | 747 | { |
734 | System_printf ("Error : failed to unprogram DDR barrier queue: %d\n", retVal); | 748 | System_printf ("Error : failed to unprogram DDR barrier queue: %d\n", retVal); |
735 | errorCount++; | 749 | errorCount++; |
@@ -751,6 +765,11 @@ void benchmark_acc_with_barrier(void) | |||
751 | System_printf ("Error : closing ddrQ %d: %d\n", ddrQ, retVal); | 765 | System_printf ("Error : closing ddrQ %d: %d\n", ddrQ, retVal); |
752 | errorCount++; | 766 | errorCount++; |
753 | } | 767 | } |
768 | if ( (retVal = Qmss_queueClose (destQ)) != QMSS_SOK) | ||
769 | { | ||
770 | System_printf ("Error : closing destQ %d: %d\n", destQ, retVal); | ||
771 | errorCount++; | ||
772 | } | ||
754 | if ( (retVal = Qmss_queueClose (badQ)) != QMSS_SOK) | 773 | if ( (retVal = Qmss_queueClose (badQ)) != QMSS_SOK) |
755 | { | 774 | { |
756 | System_printf ("Error : closing badQ %d: %d\n", badQ, retVal); | 775 | System_printf ("Error : closing badQ %d: %d\n", badQ, retVal); |
@@ -772,24 +791,30 @@ void benchmark_acc_with_barrier(void) | |||
772 | System_printf ("Error : removing memory region 0: %d\n", retVal); | 791 | System_printf ("Error : removing memory region 0: %d\n", retVal); |
773 | errorCount++; | 792 | errorCount++; |
774 | } | 793 | } |
775 | 794 | ||
776 | /* Close Tx channel */ | 795 | if ( (retVal = Qmss_removeMemoryRegion (reg1, 0)) != QMSS_SOK) |
777 | Cppi_channelDisable (txChHnd); | 796 | { |
778 | if ((result = Cppi_channelClose (txChHnd)) != CPPI_SOK) | 797 | System_printf ("Error : removing memory region 1: %d\n", retVal); |
779 | { | 798 | errorCount++; |
780 | System_printf ("Error : Closing Tx channel error code : %d\n", result); | 799 | } |
781 | errorCount++; | 800 | |
782 | } | 801 | /* Close Tx channel */ |
783 | 802 | Cppi_channelDisable (txChHnd); | |
784 | /* Close Rx channel */ | 803 | if ((result = Cppi_channelClose (txChHnd)) != CPPI_SOK) |
785 | Cppi_channelDisable (rxChHnd); | 804 | { |
786 | if ((result = Cppi_channelClose (rxChHnd)) != CPPI_SOK) | 805 | System_printf ("Error : Closing Tx channel error code : %d\n", result); |
787 | { | 806 | errorCount++; |
788 | System_printf ("Error : Closing Rx channel error code : %d\n", result); | 807 | } |
789 | errorCount++; | 808 | |
790 | } | 809 | /* Close Rx channel */ |
810 | Cppi_channelDisable (rxChHnd); | ||
811 | if ((result = Cppi_channelClose (rxChHnd)) != CPPI_SOK) | ||
812 | { | ||
813 | System_printf ("Error : Closing Rx channel error code : %d\n", result); | ||
814 | errorCount++; | ||
815 | } | ||
791 | } | 816 | } |
792 | 817 | ||
793 | 818 | ||
794 | void test_barrier (void) | 819 | void test_barrier (void) |
795 | { | 820 | { |
@@ -877,34 +902,34 @@ void test_barrier (void) | |||
877 | errorCount++; | 902 | errorCount++; |
878 | return; | 903 | return; |
879 | } | 904 | } |
880 | 905 | ||
881 | if ((ddrNetCPQ = Qmss_queueOpen | 906 | if ((ddrNetCPQ = Qmss_queueOpen |
882 | (Qmss_QueueType_GENERAL_PURPOSE_QUEUE, | 907 | (Qmss_QueueType_GENERAL_PURPOSE_QUEUE, |
883 | QMSS_PARAM_NOT_SPECIFIED, | 908 | QMSS_PARAM_NOT_SPECIFIED, |
884 | &isAllocated)) < QMSS_SOK) | 909 | &isAllocated)) < QMSS_SOK) |
885 | { | 910 | { |
886 | System_printf ("Error: Failed to open fw queue ddr netcp barrier: %d\n", ddrNetCPQ); | 911 | System_printf ("Error: Failed to open fw queue ddr netcp barrier: %d\n", ddrNetCPQ); |
887 | errorCount++; | 912 | errorCount++; |
888 | return; | 913 | return; |
889 | } | 914 | } |
890 | if ((msmcNetCPQ = Qmss_queueOpen | 915 | if ((msmcNetCPQ = Qmss_queueOpen |
891 | (Qmss_QueueType_GENERAL_PURPOSE_QUEUE, | 916 | (Qmss_QueueType_GENERAL_PURPOSE_QUEUE, |
892 | QMSS_PARAM_NOT_SPECIFIED, | 917 | QMSS_PARAM_NOT_SPECIFIED, |
893 | &isAllocated)) < QMSS_SOK) | 918 | &isAllocated)) < QMSS_SOK) |
894 | { | 919 | { |
895 | System_printf ("Error: Failed to open fw queue msmc netcp barrier: %d\n", msmcNetCPQ); | 920 | System_printf ("Error: Failed to open fw queue msmc netcp barrier: %d\n", msmcNetCPQ); |
896 | errorCount++; | 921 | errorCount++; |
897 | return; | 922 | return; |
898 | } | 923 | } |
899 | 924 | ||
900 | if ((retVal = Qmss_programDDRBarrierQueue (Qmss_PdspId_PDSP1, ddrInfQ, ddrNetCPQ)) != QMSS_ACC_SOK) | 925 | if ((retVal = Qmss_programDDRBarrierQueue (Qmss_PdspId_PDSP1, ddrInfQ, ddrNetCPQ)) != QMSS_ACC_SOK) |
901 | { | 926 | { |
902 | System_printf ("Error: failed to program DDR barrier queue: %d\n", retVal); | 927 | System_printf ("Error: failed to program DDR barrier queue: %d\n", retVal); |
903 | errorCount++; | 928 | errorCount++; |
904 | return; | 929 | return; |
905 | } | 930 | } |
906 | 931 | ||
907 | if ((retVal = Qmss_programMSMCBarrierQueue (Qmss_PdspId_PDSP1, msmcInfQ, msmcNetCPQ)) != QMSS_ACC_SOK) | 932 | if ((retVal = Qmss_programMSMCBarrierQueue (Qmss_PdspId_PDSP1, msmcInfQ, msmcNetCPQ)) != QMSS_ACC_SOK) |
908 | { | 933 | { |
909 | System_printf ("Error: failed to program MSMC barrier queue: %d\n", retVal); | 934 | System_printf ("Error: failed to program MSMC barrier queue: %d\n", retVal); |
910 | errorCount++; | 935 | errorCount++; |
@@ -912,38 +937,38 @@ void test_barrier (void) | |||
912 | } | 937 | } |
913 | 938 | ||
914 | /* Measure time to send 10000 packets through ddrQ */ | 939 | /* Measure time to send 10000 packets through ddrQ */ |
915 | benchmark_barrier (freeQ, ddrInfQ, "ddr infra"); | 940 | benchmark_barrier (freeQ, ddrInfQ, "ddr infra"); |
916 | 941 | ||
917 | /* Measure time to send 10000 packets through msmcQ */ | 942 | /* Measure time to send 10000 packets through msmcQ */ |
918 | benchmark_barrier (freeQ, msmcInfQ, "msmc infra"); | 943 | benchmark_barrier (freeQ, msmcInfQ, "msmc infra"); |
919 | 944 | ||
920 | /* Move return queue from dest tag to swinfo[1] */ | 945 | /* Move return queue from dest tag to swinfo[1] */ |
921 | for (cnt = 0; cnt < NUM_HOST_DESC; cnt++) | 946 | for (cnt = 0; cnt < NUM_HOST_DESC; cnt++) |
922 | { | 947 | { |
923 | /* Remove freeQ from dest tag; put it in swinfo[1] */ | 948 | /* Remove freeQ from dest tag; put it in swinfo[1] */ |
924 | uint32_t *desc = (uint32_t *)QMSS_DESC_PTR (Qmss_queuePop (freeQ)); | 949 | uint32_t *desc = (uint32_t *)QMSS_DESC_PTR (Qmss_queuePop (freeQ)); |
925 | if (desc) | 950 | if (desc) |
926 | { | 951 | { |
927 | desc[1] = 0; /* dest tag */ | 952 | desc[1] = 0; /* dest tag */ |
928 | desc[10] = freeQ; /* swinfo[1] */ | 953 | desc[10] = freeQ; /* swinfo[1] */ |
929 | Qmss_queuePushDesc (freeQ, desc); | 954 | Qmss_queuePushDesc (freeQ, desc); |
930 | } | 955 | } |
931 | else | 956 | else |
932 | { | 957 | { |
933 | System_printf ("Error: got NULL desc %d \n", cnt); | 958 | System_printf ("Error: got NULL desc %d \n", cnt); |
934 | errorCount++; | 959 | errorCount++; |
935 | return; | 960 | return; |
936 | } | 961 | } |
937 | } | 962 | } |
938 | 963 | ||
939 | /* Write back the DDR */ | 964 | /* Write back the DDR */ |
940 | CacheP_wb (hostDescBuf, sizeof(hostDescBuf)); | 965 | CacheP_wb (hostDescBuf, sizeof(hostDescBuf)); |
941 | 966 | ||
942 | /* Measure time to send 10000 packets through ddrNetCPQ */ | 967 | /* Measure time to send 10000 packets through ddrNetCPQ */ |
943 | benchmark_barrier (freeQ, ddrNetCPQ, "ddr netcp"); | 968 | benchmark_barrier (freeQ, ddrNetCPQ, "ddr netcp"); |
944 | 969 | ||
945 | /* Measure time to send 10000 packets through msmcNetCPQ */ | 970 | /* Measure time to send 10000 packets through msmcNetCPQ */ |
946 | benchmark_barrier (freeQ, msmcNetCPQ, "msmc netcp"); | 971 | benchmark_barrier (freeQ, msmcNetCPQ, "msmc netcp"); |
947 | 972 | ||
948 | /* Disable DDR Q */ | 973 | /* Disable DDR Q */ |
949 | if ((retVal = Qmss_programDDRBarrierQueue (Qmss_PdspId_PDSP1, 0, 0)) != QMSS_ACC_SOK) | 974 | if ((retVal = Qmss_programDDRBarrierQueue (Qmss_PdspId_PDSP1, 0, 0)) != QMSS_ACC_SOK) |
@@ -978,16 +1003,16 @@ void test_barrier (void) | |||
978 | System_printf ("Error closing msmcInfQ %d: %d\n", msmcInfQ, retVal); | 1003 | System_printf ("Error closing msmcInfQ %d: %d\n", msmcInfQ, retVal); |
979 | errorCount++; | 1004 | errorCount++; |
980 | } | 1005 | } |
981 | if ( (retVal = Qmss_queueClose (ddrNetCPQ)) != QMSS_SOK) | 1006 | if ( (retVal = Qmss_queueClose (ddrNetCPQ)) != QMSS_SOK) |
982 | { | 1007 | { |
983 | System_printf ("Error closing ddrNetCPQ %d: %d\n", ddrNetCPQ, retVal); | 1008 | System_printf ("Error closing ddrNetCPQ %d: %d\n", ddrNetCPQ, retVal); |
984 | errorCount++; | 1009 | errorCount++; |
985 | } | 1010 | } |
986 | if ( (retVal = Qmss_queueClose (msmcNetCPQ)) != QMSS_SOK) | 1011 | if ( (retVal = Qmss_queueClose (msmcNetCPQ)) != QMSS_SOK) |
987 | { | 1012 | { |
988 | System_printf ("Error closing msmcNetCPQ %d: %d\n", msmcNetCPQ, retVal); | 1013 | System_printf ("Error closing msmcNetCPQ %d: %d\n", msmcNetCPQ, retVal); |
989 | errorCount++; | 1014 | errorCount++; |
990 | } | 1015 | } |
991 | 1016 | ||
992 | if ( (retVal = Qmss_removeMemoryRegion (reg0, 0)) != QMSS_SOK) | 1017 | if ( (retVal = Qmss_removeMemoryRegion (reg0, 0)) != QMSS_SOK) |
993 | { | 1018 | { |
@@ -996,26 +1021,26 @@ void test_barrier (void) | |||
996 | } | 1021 | } |
997 | 1022 | ||
998 | } | 1023 | } |
999 | 1024 | ||
1000 | 1025 | ||
1001 | /* The barrier usage test works like this: | 1026 | /* The barrier usage test works like this: |
1002 | 1027 | ||
1003 | 1) barrierQ is programmed into Acc as the DDR barrier queue. | 1028 | 1) barrierQ is programmed into Acc as the DDR barrier queue. |
1004 | 2) pktDMA rxFreeQ is initialized, with dest_tag initialized to an incorrect queue. | 1029 | 2) pktDMA rxFreeQ is initialized, with dest_tag initialized to an incorrect queue. |
1005 | 3) pktDMA txFreeQ is initialized. | 1030 | 3) pktDMA txFreeQ is initialized. |
1006 | 4) an rx flow is programmed with: | 1031 | 4) an rx flow is programmed with: |
1007 | a) rxFreeQ as the descriptor source, | 1032 | a) rxFreeQ as the descriptor source, |
1008 | b) barrierQ as the destination Q, | 1033 | b) barrierQ as the destination Q, |
1009 | c) dest_tag is to be hardcoded from Rx flow with final destination Rx Q. | 1034 | c) dest_tag is to be hardcoded from Rx flow with final destination Rx Q. |
1010 | 5) Loop for X output descriptors: | 1035 | 5) Loop for X output descriptors: |
1011 | a) Pop N descriptors from txFreeQ, and push to pktDMA Tx Q. | 1036 | a) Pop N descriptors from txFreeQ, and push to pktDMA Tx Q. |
1012 | b) Check for output on final Rx Q: | 1037 | b) Check for output on final Rx Q: |
1013 | 1) check dest_tag for final Rx Q, increment an error count if not equal. | 1038 | 1) check dest_tag for final Rx Q, increment an error count if not equal. |
1014 | 2) write incorrect queue back to dest_tag. | 1039 | 2) write incorrect queue back to dest_tag. |
1015 | 3) push to rxFreeQ. | 1040 | 3) push to rxFreeQ. |
1016 | c) Check for output on the incorrect queue (catches missed barrier events). | 1041 | c) Check for output on the incorrect queue (catches missed barrier events). |
1017 | 1) increment an error count. | 1042 | 1) increment an error count. |
1018 | 2) push to rxFreeQ. | 1043 | 2) push to rxFreeQ. |
1019 | */ | 1044 | */ |
1020 | void test_barrier_usage(void) | 1045 | void test_barrier_usage(void) |
1021 | { | 1046 | { |
@@ -1031,71 +1056,71 @@ void test_barrier_usage(void) | |||
1031 | int32_t cnt, txcnt, rxcnt; | 1056 | int32_t cnt, txcnt, rxcnt; |
1032 | uint8_t isAllocated; | 1057 | uint8_t isAllocated; |
1033 | uint8_t *buffAddr; | 1058 | uint8_t *buffAddr; |
1034 | Cppi_Handle cppiHnd; | 1059 | Cppi_Handle cppiHnd; |
1035 | Cppi_FlowHnd rxFlowHnd; | 1060 | Cppi_FlowHnd rxFlowHnd; |
1036 | Cppi_DescTag tag; | 1061 | Cppi_DescTag tag; |
1037 | Qmss_Queue que; | 1062 | Qmss_Queue que; |
1038 | Cppi_Result result; | 1063 | Cppi_Result result; |
1039 | Cppi_HostDesc *host; | 1064 | Cppi_HostDesc *host; |
1040 | 1065 | ||
1041 | /* Initialize CPPI LLD */ | 1066 | /* Initialize CPPI LLD */ |
1042 | result = Cppi_init (&cppiGblCfgParams); | 1067 | result = Cppi_init (&cppiGblCfgParams); |
1043 | if (result != CPPI_SOK) | 1068 | if (result != CPPI_SOK) |
1044 | { | 1069 | { |
1045 | System_printf ("Error : Initializing CPPI LLD error code : %d\n", result); | 1070 | System_printf ("Error : Initializing CPPI LLD error code : %d\n", result); |
1046 | errorCount++; | 1071 | errorCount++; |
1047 | } | 1072 | } |
1048 | 1073 | ||
1049 | /* Set up QMSS CPDMA configuration */ | 1074 | /* Set up QMSS CPDMA configuration */ |
1050 | memset ((void *) &cpdmaCfg, 0, sizeof (Cppi_CpDmaInitCfg)); | 1075 | memset ((void *) &cpdmaCfg, 0, sizeof (Cppi_CpDmaInitCfg)); |
1051 | cpdmaCfg.dmaNum = Cppi_CpDma_QMSS_CPDMA; | 1076 | cpdmaCfg.dmaNum = Cppi_CpDma_QMSS_CPDMA; |
1052 | 1077 | ||
1053 | /* Open QMSS CPDMA */ | 1078 | /* Open QMSS CPDMA */ |
1054 | cppiHnd = (Cppi_Handle) Cppi_open (&cpdmaCfg); | 1079 | cppiHnd = (Cppi_Handle) Cppi_open (&cpdmaCfg); |
1055 | if (cppiHnd == NULL) | 1080 | if (cppiHnd == NULL) |
1056 | { | 1081 | { |
1057 | errorCount++; | 1082 | errorCount++; |
1058 | System_printf ("Error : Initializing QMSS CPPI CPDMA %d\n", cpdmaCfg.dmaNum); | 1083 | System_printf ("Error : Initializing QMSS CPPI CPDMA %d\n", cpdmaCfg.dmaNum); |
1059 | return; | 1084 | return; |
1060 | } | 1085 | } |
1061 | 1086 | ||
1062 | rxChCfg.channelNum = 0; | 1087 | rxChCfg.channelNum = 0; |
1063 | rxChCfg.rxEnable = Cppi_ChState_CHANNEL_ENABLE; | 1088 | rxChCfg.rxEnable = Cppi_ChState_CHANNEL_ENABLE; |
1064 | rxChHnd = (Cppi_ChHnd) Cppi_rxChannelOpen (cppiHnd, &rxChCfg, &isAllocated); | 1089 | rxChHnd = (Cppi_ChHnd) Cppi_rxChannelOpen (cppiHnd, &rxChCfg, &isAllocated); |
1065 | if (rxChHnd == NULL) | 1090 | if (rxChHnd == NULL) |
1066 | { | 1091 | { |
1067 | System_printf ("Error : Opening Rx channel : %d\n", rxChCfg.channelNum); | 1092 | System_printf ("Error : Opening Rx channel : %d\n", rxChCfg.channelNum); |
1068 | errorCount++; | 1093 | errorCount++; |
1069 | } | 1094 | } |
1070 | 1095 | ||
1071 | txChCfg.channelNum = 0; | 1096 | txChCfg.channelNum = 0; |
1072 | txChCfg.txEnable = Cppi_ChState_CHANNEL_ENABLE; | 1097 | txChCfg.txEnable = Cppi_ChState_CHANNEL_ENABLE; |
1073 | txChHnd = (Cppi_ChHnd) Cppi_txChannelOpen (cppiHnd, &txChCfg, &isAllocated); | 1098 | txChHnd = (Cppi_ChHnd) Cppi_txChannelOpen (cppiHnd, &txChCfg, &isAllocated); |
1074 | if (txChHnd == NULL) | 1099 | if (txChHnd == NULL) |
1075 | { | 1100 | { |
1076 | System_printf ("Error : Opening Tx channel : %d\n", txChCfg.channelNum); | 1101 | System_printf ("Error : Opening Tx channel : %d\n", txChCfg.channelNum); |
1077 | errorCount++; | 1102 | errorCount++; |
1078 | } | 1103 | } |
1079 | 1104 | ||
1080 | /* Configure Rx flow 0 */ | 1105 | /* Configure Rx flow 0 */ |
1081 | memset ((void *) &rxFlowCfg, 0, sizeof (Cppi_RxFlowCfg)); | 1106 | memset ((void *) &rxFlowCfg, 0, sizeof (Cppi_RxFlowCfg)); |
1082 | rxFlowCfg.rx_dest_qmgr = 0; | 1107 | rxFlowCfg.rx_dest_qmgr = 0; |
1083 | rxFlowCfg.rx_dest_qnum = BARRIER_Q; | 1108 | rxFlowCfg.rx_dest_qnum = BARRIER_Q; |
1084 | rxFlowCfg.rx_dest_tag_hi = DEST_Q >> 8; //This will be read by the Acc firmware | 1109 | rxFlowCfg.rx_dest_tag_hi = DEST_Q >> 8; //This will be read by the Acc firmware |
1085 | rxFlowCfg.rx_dest_tag_lo = DEST_Q & 0xff; | 1110 | rxFlowCfg.rx_dest_tag_lo = DEST_Q & 0xff; |
1086 | rxFlowCfg.rx_dest_tag_lo_sel = 1; | 1111 | rxFlowCfg.rx_dest_tag_lo_sel = 1; |
1087 | rxFlowCfg.rx_dest_tag_hi_sel = 1; | 1112 | rxFlowCfg.rx_dest_tag_hi_sel = 1; |
1088 | rxFlowCfg.rx_fdq0_sz0_qmgr = 0; | 1113 | rxFlowCfg.rx_fdq0_sz0_qmgr = 0; |
1089 | rxFlowCfg.rx_fdq0_sz0_qnum = RX_FREE_Q; | 1114 | rxFlowCfg.rx_fdq0_sz0_qnum = RX_FREE_Q; |
1090 | rxFlowCfg.rx_fdq1_qmgr = 0; | 1115 | rxFlowCfg.rx_fdq1_qmgr = 0; |
1091 | rxFlowCfg.rx_fdq1_qnum = RX_FREE_Q; | 1116 | rxFlowCfg.rx_fdq1_qnum = RX_FREE_Q; |
1092 | rxFlowHnd = (Cppi_FlowHnd) Cppi_configureRxFlow (cppiHnd, &rxFlowCfg, &isAllocated); | 1117 | rxFlowHnd = (Cppi_FlowHnd) Cppi_configureRxFlow (cppiHnd, &rxFlowCfg, &isAllocated); |
1093 | if (rxFlowHnd == NULL) | 1118 | if (rxFlowHnd == NULL) |
1094 | { | 1119 | { |
1095 | System_printf ("Error : Opening Rx flow : %d\n", rxFlowCfg.flowIdNum); | 1120 | System_printf ("Error : Opening Rx flow : %d\n", rxFlowCfg.flowIdNum); |
1096 | errorCount++; | 1121 | errorCount++; |
1097 | } | 1122 | } |
1098 | 1123 | ||
1099 | /* Setup memory region for host descriptors */ | 1124 | /* Setup memory region for host descriptors */ |
1100 | memset ((void *) hostDescBuf, 0, (SIZE_HOST_DESC * NUM_HOST_DESC)); | 1125 | memset ((void *) hostDescBuf, 0, (SIZE_HOST_DESC * NUM_HOST_DESC)); |
1101 | memInfo.descBase = DESC_ADDR; | 1126 | memInfo.descBase = DESC_ADDR; |
@@ -1132,7 +1157,7 @@ void test_barrier_usage(void) | |||
1132 | errorCount++; | 1157 | errorCount++; |
1133 | return; | 1158 | return; |
1134 | } | 1159 | } |
1135 | 1160 | ||
1136 | //Move half the descriptors to RX_FREE_Q | 1161 | //Move half the descriptors to RX_FREE_Q |
1137 | if ((rxfdq = Qmss_queueOpen(Qmss_QueueType_GENERAL_PURPOSE_QUEUE, | 1162 | if ((rxfdq = Qmss_queueOpen(Qmss_QueueType_GENERAL_PURPOSE_QUEUE, |
1138 | RX_FREE_Q, &isAllocated)) < QMSS_SOK) | 1163 | RX_FREE_Q, &isAllocated)) < QMSS_SOK) |
@@ -1140,47 +1165,47 @@ void test_barrier_usage(void) | |||
1140 | System_printf ("Error: Failed to open Rx Free queue: %d\n", rxfdq); | 1165 | System_printf ("Error: Failed to open Rx Free queue: %d\n", rxfdq); |
1141 | errorCount++; | 1166 | errorCount++; |
1142 | return; | 1167 | return; |
1143 | } | 1168 | } |
1144 | 1169 | ||
1145 | tag.srcTagHi = 0; | 1170 | tag.srcTagHi = 0; |
1146 | tag.srcTagLo = 0; | 1171 | tag.srcTagLo = 0; |
1147 | tag.destTagHi = BAD_Q >> 8; | 1172 | tag.destTagHi = BAD_Q >> 8; |
1148 | tag.destTagLo = BAD_Q & 0xff; | 1173 | tag.destTagLo = BAD_Q & 0xff; |
1149 | que.qMgr = 0; | 1174 | que.qMgr = 0; |
1150 | que.qNum = DEST_Q; | 1175 | que.qNum = DEST_Q; |
1151 | buffAddr = DESC_BUF_ADDR + (NUM_HOST_DESC/2 * DESC_BUF_SIZE); | 1176 | buffAddr = DESC_BUF_ADDR + (NUM_HOST_DESC/2 * DESC_BUF_SIZE); |
1152 | 1177 | ||
1153 | for (cnt = 0; cnt < NUM_HOST_DESC/2; cnt++) | 1178 | for (cnt = 0; cnt < NUM_HOST_DESC/2; cnt++) |
1154 | { | 1179 | { |
1155 | uint32_t *desc = (uint32_t *)QMSS_DESC_PTR (Qmss_queuePop (TX_FREE_Q)); | 1180 | uint32_t *desc = (uint32_t *)QMSS_DESC_PTR (Qmss_queuePop (TX_FREE_Q)); |
1156 | if (desc) | 1181 | if (desc) |
1157 | { | 1182 | { |
1158 | host = (Cppi_HostDesc *)desc; | 1183 | host = (Cppi_HostDesc *)desc; |
1159 | Cppi_setOriginalBufInfo(Cppi_DescType_HOST, (Cppi_Desc *)desc, | 1184 | Cppi_setOriginalBufInfo(Cppi_DescType_HOST, (Cppi_Desc *)desc, |
1160 | buffAddr, DESC_BUF_SIZE); | 1185 | buffAddr, DESC_BUF_SIZE); |
1161 | Cppi_setTag (Cppi_DescType_HOST, (Cppi_Desc *)desc, &tag); | 1186 | Cppi_setTag (Cppi_DescType_HOST, (Cppi_Desc *)desc, &tag); |
1162 | Cppi_setReturnQueue (Cppi_DescType_HOST, (Cppi_Desc *)desc, que); | 1187 | Cppi_setReturnQueue (Cppi_DescType_HOST, (Cppi_Desc *)desc, que); |
1163 | Qmss_queuePushDesc (RX_FREE_Q, desc); | 1188 | Qmss_queuePushDesc (RX_FREE_Q, desc); |
1164 | } | 1189 | } |
1165 | buffAddr += DESC_BUF_SIZE; | 1190 | buffAddr += DESC_BUF_SIZE; |
1166 | } | 1191 | } |
1167 | 1192 | ||
1168 | //Update the descriptors in TX_FREE_Q | 1193 | //Update the descriptors in TX_FREE_Q |
1169 | que.qMgr = 0; | 1194 | que.qMgr = 0; |
1170 | que.qNum = TX_FREE_Q; | 1195 | que.qNum = TX_FREE_Q; |
1171 | buffAddr = DESC_BUF_ADDR; | 1196 | buffAddr = DESC_BUF_ADDR; |
1172 | 1197 | ||
1173 | for (cnt = 0; cnt < NUM_HOST_DESC; cnt++) | 1198 | for (cnt = 0; cnt < NUM_HOST_DESC; cnt++) |
1174 | { | 1199 | { |
1175 | /* Put freeQ in dest tag */ | 1200 | /* Put freeQ in dest tag */ |
1176 | uint32_t *desc = (uint32_t *)QMSS_DESC_PTR (Qmss_queuePop (TX_FREE_Q)); | 1201 | uint32_t *desc = (uint32_t *)QMSS_DESC_PTR (Qmss_queuePop (TX_FREE_Q)); |
1177 | if (desc) | 1202 | if (desc) |
1178 | { | 1203 | { |
1179 | host = (Cppi_HostDesc *)desc; | 1204 | host = (Cppi_HostDesc *)desc; |
1180 | Cppi_setData (Cppi_DescType_HOST, (Cppi_Desc *)desc, | 1205 | Cppi_setData (Cppi_DescType_HOST, (Cppi_Desc *)desc, |
1181 | buffAddr, DESC_BUF_SIZE); | 1206 | buffAddr, DESC_BUF_SIZE); |
1182 | Cppi_setPacketLen (Cppi_DescType_HOST, (Cppi_Desc *)desc, DESC_BUF_SIZE); | 1207 | Cppi_setPacketLen (Cppi_DescType_HOST, (Cppi_Desc *)desc, DESC_BUF_SIZE); |
1183 | Cppi_setReturnQueue (Cppi_DescType_HOST, (Cppi_Desc *)desc, que); | 1208 | Cppi_setReturnQueue (Cppi_DescType_HOST, (Cppi_Desc *)desc, que); |
1184 | Qmss_queuePushDesc (TX_FREE_Q, desc); | 1209 | Qmss_queuePushDesc (TX_FREE_Q, desc); |
1185 | } | 1210 | } |
1186 | else | 1211 | else |
@@ -1191,7 +1216,7 @@ void test_barrier_usage(void) | |||
1191 | } | 1216 | } |
1192 | buffAddr += DESC_BUF_SIZE; | 1217 | buffAddr += DESC_BUF_SIZE; |
1193 | } | 1218 | } |
1194 | 1219 | ||
1195 | /* Write back the DDR */ | 1220 | /* Write back the DDR */ |
1196 | // CacheP_wb (hostDescBuf, sizeof(hostDescBuf)); | 1221 | // CacheP_wb (hostDescBuf, sizeof(hostDescBuf)); |
1197 | 1222 | ||
@@ -1219,109 +1244,116 @@ void test_barrier_usage(void) | |||
1219 | return; | 1244 | return; |
1220 | } | 1245 | } |
1221 | 1246 | ||
1222 | if ((retVal = Qmss_programDDRBarrierQueue (Qmss_PdspId_PDSP1, ddrQ)) != QMSS_ACC_SOK) | 1247 | retVal = Qmss_programDDRBarrierQueue (Qmss_PdspId_PDSP1, ddrQ, 0); |
1248 | if (retVal != QMSS_ACC_SOK) | ||
1223 | { | 1249 | { |
1224 | System_printf ("Error: failed to program DDR barrier queue: %d\n", retVal); | 1250 | System_printf ("Error: failed to program DDR barrier queue: %d\n", retVal); |
1225 | errorCount++; | 1251 | errorCount++; |
1226 | return; | 1252 | return; |
1227 | } | 1253 | } |
1228 | 1254 | ||
1229 | txcnt = 0; | 1255 | txcnt = 0; |
1230 | rxcnt = 0; | 1256 | rxcnt = 0; |
1231 | err1_cnt = 0; | 1257 | err1_cnt = 0; |
1232 | err2_cnt = 0; | 1258 | err2_cnt = 0; |
1233 | TSCL = 0; //since this isn't the first set, it doesn't actually zero it. | 1259 | TSCL = 0; //since this isn't the first set, it doesn't actually zero it. |
1234 | start = TSCL; | 1260 | start = TSCL; |
1235 | 1261 | ||
1236 | while (rxcnt < BARRIER_PKTS) | 1262 | while (rxcnt < BARRIER_PKTS) |
1237 | { | 1263 | { |
1238 | //Push descriptors to the Tx pktDMA, channel 0 | 1264 | //Push descriptors to the Tx pktDMA, channel 0 |
1239 | for (idx = 0; idx < 16; idx++) | 1265 | for (idx = 0; idx < 16; idx++) |
1240 | { | 1266 | { |
1241 | if (txcnt < BARRIER_PKTS) | 1267 | if (txcnt < BARRIER_PKTS) |
1242 | { | 1268 | { |
1243 | uint32_t *desc = (uint32_t *)QMSS_DESC_PTR(Qmss_queuePop(TX_FREE_Q)); | 1269 | uint32_t *desc = (uint32_t *)QMSS_DESC_PTR(Qmss_queuePop(TX_FREE_Q)); |
1244 | if (desc) | 1270 | if (desc) |
1245 | { | 1271 | { |
1246 | //No MFENCE needed, since descriptors are not modified | 1272 | //No MFENCE needed, since descriptors are not modified |
1247 | Qmss_queuePushDescSizeRaw(TX_Q, desc, 32); | 1273 | Qmss_queuePushDescSizeRaw(TX_Q, desc, 32); |
1248 | txcnt++; | 1274 | txcnt++; |
1249 | } | 1275 | } |
1250 | } | 1276 | } |
1251 | } | 1277 | } |
1252 | 1278 | ||
1253 | //Process descriptors correctly arriving at the destination queue. | 1279 | //Process descriptors correctly arriving at the destination queue. |
1254 | cnt = Qmss_getQueueEntryCount(destQ); | 1280 | cnt = Qmss_getQueueEntryCount(destQ); |
1255 | for (idx = 0; idx < cnt; idx++) | 1281 | for (idx = 0; idx < cnt; idx++) |
1256 | { | 1282 | { |
1257 | uint32_t *desc = (uint32_t *)QMSS_DESC_PTR(Qmss_queuePop(DEST_Q)); | 1283 | uint32_t *desc = (uint32_t *)QMSS_DESC_PTR(Qmss_queuePop(DEST_Q)); |
1258 | if (desc) | 1284 | if (desc) |
1259 | { | 1285 | { |
1260 | host = (Cppi_HostDesc *)desc; | 1286 | host = (Cppi_HostDesc *)desc; |
1261 | 1287 | ||
1262 | //Examine the dest tag. This test shouldn't fail because the descriptor | 1288 | //Examine the dest tag. This test shouldn't fail because the descriptor |
1263 | //is in the correct queue, but we'll check for completeness. | 1289 | //is in the correct queue, but we'll check for completeness. |
1264 | tag = Cppi_getTag(Cppi_DescType_HOST, (Cppi_Desc *)host); | 1290 | tag = Cppi_getTag(Cppi_DescType_HOST, (Cppi_Desc *)host); |
1265 | if ((tag.destTagHi != (DEST_Q >> 8)) || | 1291 | if ((tag.destTagHi != (DEST_Q >> 8)) || |
1266 | (tag.destTagLo != (DEST_Q & 0xff))) | 1292 | (tag.destTagLo != (DEST_Q & 0xff))) |
1267 | err1_cnt ++; | 1293 | err1_cnt ++; |
1268 | 1294 | ||
1269 | //Write the illegal tag (bad queue number) back to the descriptor | 1295 | //Write the illegal tag (bad queue number) back to the descriptor |
1270 | tag.destTagHi = BAD_Q >> 8; | 1296 | tag.destTagHi = BAD_Q >> 8; |
1271 | tag.destTagLo = BAD_Q & 0xff; | 1297 | tag.destTagLo = BAD_Q & 0xff; |
1272 | Cppi_setTag (Cppi_DescType_HOST, (Cppi_Desc *)desc, &tag); | 1298 | Cppi_setTag (Cppi_DescType_HOST, (Cppi_Desc *)desc, &tag); |
1273 | Qmss_queuePushDesc (RX_FREE_Q, desc); | 1299 | Qmss_queuePushDesc (RX_FREE_Q, desc); |
1274 | 1300 | ||
1275 | rxcnt++; | 1301 | rxcnt++; |
1276 | } | 1302 | } |
1277 | } | 1303 | } |
1278 | 1304 | ||
1279 | //A descriptor arriving in this queue (badQ) indicates that the firmware | 1305 | //A descriptor arriving in this queue (badQ) indicates that the firmware |
1280 | //read the tag before the write from the Rx pktDMA had landed. This is | 1306 | //read the tag before the write from the Rx pktDMA had landed. This is |
1281 | //an error. This failure should not occur on a DSP core, only an ARM. | 1307 | //an error. This failure should not occur on a DSP core, only an ARM. |
1282 | cnt = Qmss_getQueueEntryCount(badQ); | 1308 | cnt = Qmss_getQueueEntryCount(badQ); |
1283 | for (idx = 0; idx < cnt; idx++) | 1309 | for (idx = 0; idx < cnt; idx++) |
1284 | { | 1310 | { |
1285 | uint32_t *desc = (uint32_t *)QMSS_DESC_PTR(Qmss_queuePop(BAD_Q)); | 1311 | uint32_t *desc = (uint32_t *)QMSS_DESC_PTR(Qmss_queuePop(BAD_Q)); |
1286 | if (desc) | 1312 | if (desc) |
1287 | { | 1313 | { |
1288 | host = (Cppi_HostDesc *)desc; | 1314 | host = (Cppi_HostDesc *)desc; |
1289 | err2_cnt ++; | 1315 | err2_cnt ++; |
1290 | 1316 | ||
1291 | //Make sure the bad queue number is back in the descriptor | 1317 | //Make sure the bad queue number is back in the descriptor |
1292 | tag.destTagHi = BAD_Q >> 8; | 1318 | tag.destTagHi = BAD_Q >> 8; |
1293 | tag.destTagLo = BAD_Q & 0xff; | 1319 | tag.destTagLo = BAD_Q & 0xff; |
1294 | Cppi_setTag (Cppi_DescType_HOST, (Cppi_Desc *)desc, &tag); | 1320 | Cppi_setTag (Cppi_DescType_HOST, (Cppi_Desc *)desc, &tag); |
1295 | Qmss_queuePushDesc (RX_FREE_Q, desc); | 1321 | Qmss_queuePushDesc (RX_FREE_Q, desc); |
1296 | } | 1322 | } |
1297 | } | 1323 | } |
1298 | } | 1324 | } |
1299 | 1325 | ||
1300 | stop = TSCL; | 1326 | stop = TSCL; |
1301 | System_printf ("Took %d cycles to move %d descs through pktDMA and barrier\n", (int)(stop - start), rxcnt); | 1327 | System_printf ("Took %d cycles to move %d descs through pktDMA and barrier\n", (int)(stop - start), rxcnt); |
1302 | System_printf ("Assuming 983Mhz clock, this is %d desc/sec\n", 983000000 / ((stop - start) / 10000)); | 1328 | System_printf ("Assuming 983Mhz clock, this is %d desc/sec\n", 983000000 / ((stop - start) / 10000)); |
1303 | 1329 | ||
1304 | if (err1_cnt > 0) | 1330 | if (err1_cnt > 0) |
1305 | System_printf ("Error : %d descs received with invalid dest tags\n", err1_cnt); | 1331 | System_printf ("Error : %d descs received with invalid dest tags\n", err1_cnt); |
1306 | 1332 | ||
1307 | if (err2_cnt > 0) | 1333 | if (err2_cnt > 0) |
1308 | System_printf ("Error : %d descs routed to erroneous dest queue\n", err2_cnt); | 1334 | System_printf ("Error : %d descs routed to erroneous dest queue\n", err2_cnt); |
1309 | 1335 | ||
1310 | cnt = Qmss_getQueueEntryCount(rxfdq); | 1336 | cnt = Qmss_getQueueEntryCount(rxfdq); |
1311 | if (cnt != NUM_HOST_DESC/2) | 1337 | if (cnt != NUM_HOST_DESC/2) |
1312 | System_printf ("Error : Rx FDQ ended with %d descs, should be %d\n", cnt, NUM_HOST_DESC/2); | 1338 | System_printf ("Error : Rx FDQ ended with %d descs, should be %d\n", cnt, NUM_HOST_DESC/2); |
1313 | 1339 | ||
1314 | Qmss_queueEmpty(rxfdq); | 1340 | Qmss_queueEmpty(rxfdq); |
1315 | Qmss_queueEmpty(txfdq); | 1341 | Qmss_queueEmpty(txfdq); |
1316 | 1342 | ||
1317 | /* Disable DDR Q */ | 1343 | /* Disable DDR Q */ |
1318 | if ((retVal = Qmss_programDDRBarrierQueue (Qmss_PdspId_PDSP1, 0)) != QMSS_ACC_SOK) | 1344 | retVal = Qmss_programDDRBarrierQueue (Qmss_PdspId_PDSP1, 0, 0); |
1345 | |||
1346 | if (retVal != QMSS_ACC_SOK) | ||
1319 | { | 1347 | { |
1320 | System_printf ("Error : failed to unprogram DDR barrier queue: %d\n", retVal); | 1348 | System_printf ("Error : failed to unprogram DDR barrier queue: %d\n", retVal); |
1321 | errorCount++; | 1349 | errorCount++; |
1322 | return; | 1350 | return; |
1323 | } | 1351 | } |
1324 | 1352 | ||
1353 | Qmss_queueEmpty(destQ); | ||
1354 | Qmss_queueEmpty(ddrQ); | ||
1355 | Qmss_queueEmpty(badQ); | ||
1356 | |||
1325 | if ( (retVal = Qmss_queueClose (txfdq)) != QMSS_SOK) | 1357 | if ( (retVal = Qmss_queueClose (txfdq)) != QMSS_SOK) |
1326 | { | 1358 | { |
1327 | System_printf ("Error : closing txfdq %d: %d\n", txfdq, retVal); | 1359 | System_printf ("Error : closing txfdq %d: %d\n", txfdq, retVal); |
@@ -1338,31 +1370,42 @@ void test_barrier_usage(void) | |||
1338 | errorCount++; | 1370 | errorCount++; |
1339 | } | 1371 | } |
1340 | 1372 | ||
1373 | if ( (retVal = Qmss_queueClose (destQ)) != QMSS_SOK) | ||
1374 | { | ||
1375 | System_printf ("Error : closing destQ %d: %d\n", destQ, retVal); | ||
1376 | errorCount++; | ||
1377 | } | ||
1378 | |||
1379 | if ( (retVal = Qmss_queueClose (badQ)) != QMSS_SOK) | ||
1380 | { | ||
1381 | System_printf ("Error : closing badQ %d: %d\n", badQ, retVal); | ||
1382 | errorCount++; | ||
1383 | } | ||
1384 | |||
1341 | if ( (retVal = Qmss_removeMemoryRegion (reg0, 0)) != QMSS_SOK) | 1385 | if ( (retVal = Qmss_removeMemoryRegion (reg0, 0)) != QMSS_SOK) |
1342 | { | 1386 | { |
1343 | System_printf ("Error : removing memory region 0: %d\n", retVal); | 1387 | System_printf ("Error : removing memory region 0: %d\n", retVal); |
1344 | errorCount++; | 1388 | errorCount++; |
1345 | } | 1389 | } |
1346 | 1390 | ||
1347 | /* Close Tx channel */ | 1391 | /* Close Tx channel */ |
1348 | Cppi_channelDisable (txChHnd); | 1392 | Cppi_channelDisable (txChHnd); |
1349 | if ((result = Cppi_channelClose (txChHnd)) != CPPI_SOK) | 1393 | if ((result = Cppi_channelClose (txChHnd)) != CPPI_SOK) |
1350 | { | 1394 | { |
1351 | System_printf ("Error : Closing Tx channel error code : %d\n", result); | 1395 | System_printf ("Error : Closing Tx channel error code : %d\n", result); |
1352 | errorCount++; | 1396 | errorCount++; |
1353 | } | 1397 | } |
1354 | 1398 | ||
1355 | /* Close Rx channel */ | 1399 | /* Close Rx channel */ |
1356 | Cppi_channelDisable (rxChHnd); | 1400 | Cppi_channelDisable (rxChHnd); |
1357 | if ((result = Cppi_channelClose (rxChHnd)) != CPPI_SOK) | 1401 | if ((result = Cppi_channelClose (rxChHnd)) != CPPI_SOK) |
1358 | { | 1402 | { |
1359 | System_printf ("Error : Closing Rx channel error code : %d\n", result); | 1403 | System_printf ("Error : Closing Rx channel error code : %d\n", result); |
1360 | errorCount++; | 1404 | errorCount++; |
1361 | } | 1405 | } |
1362 | } | 1406 | } |
1363 | #endif | 1407 | |
1364 | 1408 | ||
1365 | |||
1366 | //This function tests a push to head reclamation scenario. | 1409 | //This function tests a push to head reclamation scenario. |
1367 | void test_reclamation_to_head(void) | 1410 | void test_reclamation_to_head(void) |
1368 | { | 1411 | { |
@@ -1414,7 +1457,7 @@ void test_reclamation_to_head(void) | |||
1414 | errorCount++; | 1457 | errorCount++; |
1415 | return; | 1458 | return; |
1416 | } | 1459 | } |
1417 | 1460 | ||
1418 | if ((destQ = Qmss_queueOpen | 1461 | if ((destQ = Qmss_queueOpen |
1419 | (Qmss_QueueType_GENERAL_PURPOSE_QUEUE, | 1462 | (Qmss_QueueType_GENERAL_PURPOSE_QUEUE, |
1420 | QMSS_PARAM_NOT_SPECIFIED, | 1463 | QMSS_PARAM_NOT_SPECIFIED, |
@@ -1434,73 +1477,73 @@ void test_reclamation_to_head(void) | |||
1434 | return; | 1477 | return; |
1435 | } | 1478 | } |
1436 | 1479 | ||
1437 | //Pop two descriptors and initialize for the reclamation queue | 1480 | //Pop two descriptors and initialize for the reclamation queue |
1438 | /* Put freeQ in dest tag */ | 1481 | /* Put freeQ in dest tag */ |
1439 | desc1 = (uint32_t *)QMSS_DESC_PTR (Qmss_queuePop (freeQ)); | 1482 | desc1 = (uint32_t *)QMSS_DESC_PTR (Qmss_queuePop (freeQ)); |
1440 | desc2 = (uint32_t *)QMSS_DESC_PTR (Qmss_queuePop (freeQ)); | 1483 | desc2 = (uint32_t *)QMSS_DESC_PTR (Qmss_queuePop (freeQ)); |
1441 | if ((desc1 == NULL) || (desc2 == NULL) || (desc1 == desc2)) | 1484 | if ((desc1 == NULL) || (desc2 == NULL) || (desc1 == desc2)) |
1442 | { | 1485 | { |
1443 | System_printf ("Error: reclaim input descriptors bad 0x%x 0x%x\n", | 1486 | System_printf ("Error: reclaim input descriptors bad 0x%x 0x%x\n", |
1444 | desc1, desc2); | 1487 | desc1, desc2); |
1445 | errorCount++; | 1488 | errorCount++; |
1446 | return; | 1489 | return; |
1447 | } | 1490 | } |
1448 | 1491 | ||
1449 | //initialize the words that the firmware will use | 1492 | //initialize the words that the firmware will use |
1450 | desc1[2] = 0x0000c000 + destQ; | 1493 | desc1[2] = 0x0000c000 + destQ; |
1451 | desc1[5] = (uint32_t) desc2; | 1494 | desc1[5] = (uint32_t) desc2; |
1452 | desc2[2] = 0x0000c000 + destQ; | 1495 | desc2[2] = 0x0000c000 + destQ; |
1453 | desc2[5] = 0; | 1496 | desc2[5] = 0; |
1454 | 1497 | ||
1455 | if ((retVal = Qmss_programReclaimQueue (Qmss_PdspId_PDSP1, recQ)) != QMSS_ACC_SOK) | 1498 | if ((retVal = Qmss_programReclaimQueue (Qmss_PdspId_PDSP1, recQ)) != QMSS_ACC_SOK) |
1456 | { | 1499 | { |
1457 | System_printf ("Error: failed to program reclamation queue: %d\n", retVal); | 1500 | System_printf ("Error: failed to program reclamation queue: %d\n", retVal); |
1458 | errorCount++; | 1501 | errorCount++; |
1459 | return; | 1502 | return; |
1460 | } | 1503 | } |
1461 | 1504 | ||
1462 | //The two descriptors are linked. Push the head descriptor to the reclamation queue. | 1505 | //The two descriptors are linked. Push the head descriptor to the reclamation queue. |
1463 | Qmss_queuePushDesc(recQ, desc1); | 1506 | Qmss_queuePushDesc(recQ, desc1); |
1464 | 1507 | ||
1465 | for (cnt = 0; cnt < 1000; cnt++) | 1508 | for (cnt = 0; cnt < 1000; cnt++) |
1466 | asm(" nop 5 "); | 1509 | asm(" nop 5 "); |
1467 | 1510 | ||
1468 | //Now, examine the results: | 1511 | //Now, examine the results: |
1469 | cnt = Qmss_getQueueEntryCount(destQ); | 1512 | cnt = Qmss_getQueueEntryCount(destQ); |
1470 | if (cnt != 2) | 1513 | if (cnt != 2) |
1471 | { | 1514 | { |
1472 | System_printf ("Error : Dest Q ended with %d descs, should be %d\n", cnt, 2); | 1515 | System_printf ("Error : Dest Q ended with %d descs, should be %d\n", cnt, 2); |
1473 | errorCount++; | 1516 | errorCount++; |
1474 | } | 1517 | } |
1475 | 1518 | ||
1476 | desc3 = (uint32_t *)QMSS_DESC_PTR (Qmss_queuePop (destQ)); | 1519 | desc3 = (uint32_t *)QMSS_DESC_PTR (Qmss_queuePop (destQ)); |
1477 | desc4 = (uint32_t *)QMSS_DESC_PTR (Qmss_queuePop (destQ)); | 1520 | desc4 = (uint32_t *)QMSS_DESC_PTR (Qmss_queuePop (destQ)); |
1478 | 1521 | ||
1479 | /* Push head causes descriptors to get reversed */ | 1522 | /* Push head causes descriptors to get reversed */ |
1480 | if (desc3 != desc2) | 1523 | if (desc3 != desc2) |
1481 | { | 1524 | { |
1482 | System_printf ("Error : Desc2 did not recycle correctly, 0x%x != 0x%x\n", | 1525 | System_printf ("Error : Desc2 did not recycle correctly, 0x%x != 0x%x\n", |
1483 | desc2, desc3); | 1526 | desc2, desc3); |
1484 | errorCount++; | 1527 | errorCount++; |
1485 | } | 1528 | } |
1486 | 1529 | ||
1487 | if (desc4 != desc1) | 1530 | if (desc4 != desc1) |
1488 | { | 1531 | { |
1489 | System_printf ("Error : Desc1 did not recycle correctly, 0x%x != 0x%x\n", | 1532 | System_printf ("Error : Desc1 did not recycle correctly, 0x%x != 0x%x\n", |
1490 | desc1, desc4); | 1533 | desc1, desc4); |
1491 | errorCount++; | 1534 | errorCount++; |
1492 | } | 1535 | } |
1493 | 1536 | ||
1494 | Qmss_queueEmpty(destQ); | 1537 | Qmss_queueEmpty(destQ); |
1495 | Qmss_queueEmpty(freeQ); | 1538 | Qmss_queueEmpty(freeQ); |
1496 | 1539 | ||
1497 | if ((retVal = Qmss_programReclaimQueue (Qmss_PdspId_PDSP1, 0)) != QMSS_ACC_SOK) | 1540 | if ((retVal = Qmss_programReclaimQueue (Qmss_PdspId_PDSP1, 0)) != QMSS_ACC_SOK) |
1498 | { | 1541 | { |
1499 | System_printf ("Error: failed to unprogram reclamation queue: %d\n", retVal); | 1542 | System_printf ("Error: failed to unprogram reclamation queue: %d\n", retVal); |
1500 | errorCount++; | 1543 | errorCount++; |
1501 | return; | 1544 | return; |
1502 | } | 1545 | } |
1503 | 1546 | ||
1504 | if ( (retVal = Qmss_queueClose (freeQ)) != QMSS_SOK) | 1547 | if ( (retVal = Qmss_queueClose (freeQ)) != QMSS_SOK) |
1505 | { | 1548 | { |
1506 | System_printf ("Error closing freeQ %d: %d\n", freeQ, retVal); | 1549 | System_printf ("Error closing freeQ %d: %d\n", freeQ, retVal); |
@@ -1524,7 +1567,8 @@ void test_reclamation_to_head(void) | |||
1524 | } | 1567 | } |
1525 | 1568 | ||
1526 | } | 1569 | } |
1527 | 1570 | #endif | |
1571 | #endif | ||
1528 | 1572 | ||
1529 | /** | 1573 | /** |
1530 | * @b Description | 1574 | * @b Description |
@@ -1570,7 +1614,7 @@ void accTest (void) | |||
1570 | qmssInitConfig.linkingRAM0Base = 0; | 1614 | qmssInitConfig.linkingRAM0Base = 0; |
1571 | qmssInitConfig.linkingRAM0Size = 0; | 1615 | qmssInitConfig.linkingRAM0Size = 0; |
1572 | qmssInitConfig.linkingRAM1Base = 0; | 1616 | qmssInitConfig.linkingRAM1Base = 0; |
1573 | qmssInitConfig.maxDescNum = NUM_HOST_DESC * 2; | 1617 | qmssInitConfig.maxDescNum = NUM_HOST_DESC + NUM_MONOLITHIC_DESC; |
1574 | 1618 | ||
1575 | /* Select endian dependent firmware version */ | 1619 | /* Select endian dependent firmware version */ |
1576 | #ifdef xdc_target__bigEndian | 1620 | #ifdef xdc_target__bigEndian |
@@ -1669,22 +1713,21 @@ void accTest (void) | |||
1669 | errorCount++; | 1713 | errorCount++; |
1670 | System_printf ("Error closing queue %d QM: %d \n", rxQueHnd, result); | 1714 | System_printf ("Error closing queue %d QM: %d \n", rxQueHnd, result); |
1671 | } | 1715 | } |
1672 | 1716 | ||
1673 | test_reclamation_to_head(); | ||
1674 | |||
1675 | /* These only apply to K2 devices */ | 1717 | /* These only apply to K2 devices */ |
1676 | #if defined(DEVICE_K2H) || defined(SOC_K2H) || \ | 1718 | #if defined(DEVICE_K2H) || defined(SOC_K2H) |
1677 | defined(DEVICE_K2K) || defined(SOC_K2K) || \ | 1719 | |
1678 | defined(DEVICE_K2L) || defined(SOC_K2L) || \ | 1720 | #ifdef _TMS320C6X |
1679 | defined(DEVICE_K2E) || defined(SOC_K2E) | 1721 | test_reclamation_to_head(); |
1680 | 1722 | ||
1681 | test_barrier (); | 1723 | test_barrier (); |
1682 | test_barrier_usage(); | 1724 | test_barrier_usage(); |
1683 | 1725 | ||
1684 | //See preamble for usage notes. | 1726 | //See preamble for usage notes. |
1685 | benchmark_acc_with_barrier(); | 1727 | benchmark_acc_with_barrier(); |
1686 | #endif | 1728 | #endif |
1687 | 1729 | #endif | |
1730 | |||
1688 | System_printf ("exit QM\n"); | 1731 | System_printf ("exit QM\n"); |
1689 | if ( (result = Qmss_exit()) != QMSS_SOK) | 1732 | if ( (result = Qmss_exit()) != QMSS_SOK) |
1690 | { | 1733 | { |
@@ -1708,3 +1751,4 @@ void run_test (void) | |||
1708 | { | 1751 | { |
1709 | accTest (); | 1752 | accTest (); |
1710 | } | 1753 | } |
1754 | |||