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author | Aravind Batni | 2019-08-13 12:13:35 -0500 |
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committer | Mahesh Radhakrishnan | 2019-10-23 14:20:12 -0500 |
commit | 8b5155c2ac072a87807e84dcab87600f3bbf7f72 (patch) | |
tree | fa0f7579ec13651f06b483b84bad7660c9e0e461 | |
parent | b91ff5dd873c46e2ee7a87c85d0e872491134197 (diff) | |
download | sd-mmc-8b5155c2ac072a87807e84dcab87600f3bbf7f72.tar.gz sd-mmc-8b5155c2ac072a87807e84dcab87600f3bbf7f72.tar.xz sd-mmc-8b5155c2ac072a87807e84dcab87600f3bbf7f72.zip |
PRSDK-6273: Align MMCSD soc c source to align to CSL define updates for PG1 bug fixes
Signed-off-by: Aravind Batni <aravindbr@ti.com>
-rw-r--r-- | soc/am65xx/MMCSD_soc.c | 28 |
1 files changed, 14 insertions, 14 deletions
diff --git a/soc/am65xx/MMCSD_soc.c b/soc/am65xx/MMCSD_soc.c index 4669ae1..262196a 100644 --- a/soc/am65xx/MMCSD_soc.c +++ b/soc/am65xx/MMCSD_soc.c | |||
@@ -55,15 +55,15 @@ MMCSD_v2_HwAttrs MMCSDInitCfg[MMCSD_CNT] = | |||
55 | { | 55 | { |
56 | 1, | 56 | 1, |
57 | #if defined (__aarch64__) | 57 | #if defined (__aarch64__) |
58 | CSL_MMCSD1_CTL_CFG_BASE, /* Controller Registers */ | 58 | CSL_MMC0_CTL_CFG_BASE, /* Controller Registers */ |
59 | CSL_MMCSD1_SS_CFG_BASE , /* SS Registers */ | 59 | CSL_MMC0_SS_CFG_BASE , /* SS Registers */ |
60 | CSL_MMCSD1_SS_CFG_BASE + 0x100 ,/* PHY Registers */ | 60 | CSL_MMC0_SS_CFG_BASE + 0x100 ,/* PHY Registers */ |
61 | CSL_GIC0_INTR_MMCSD1_BUS_EMMCSDSS_INTR, /* Corresponds to GIC500_SPI_INT_IN_168 */ | 61 | CSL_GIC0_INTR_MMC0_BUS_EMMCSDSS_INTR, /* Corresponds to GIC500_SPI_INT_IN_168 */ |
62 | 0, /* Event ID is not used */ | 62 | 0, /* Event ID is not used */ |
63 | #else | 63 | #else |
64 | CSL_MMCSD1_CTL_CFG_BASE, | 64 | CSL_MMC0_CTL_CFG_BASE, |
65 | CSL_MMCSD1_SS_CFG_BASE , /* SS Registers */ | 65 | CSL_MMC0_SS_CFG_BASE , /* SS Registers */ |
66 | CSL_MMCSD1_SS_CFG_BASE + 0x100,/* PHY Registers */ | 66 | CSL_MMC0_SS_CFG_BASE + 0x100,/* PHY Registers */ |
67 | CSL_MCU0_INTR_MAIN2MCU_LVL_INTR0_OUTL_0 +21, /* intNum: Choosing random values 21 & 22 */ | 67 | CSL_MCU0_INTR_MAIN2MCU_LVL_INTR0_OUTL_0 +21, /* intNum: Choosing random values 21 & 22 */ |
68 | 0, /* eventNum: Corresponds to MAIN2MCU_INTRTR_LVL_IN_28, or bus_emmcsdss_intr (0) for DMSC firmware */ | 68 | 0, /* eventNum: Corresponds to MAIN2MCU_INTRTR_LVL_IN_28, or bus_emmcsdss_intr (0) for DMSC firmware */ |
69 | #endif | 69 | #endif |
@@ -101,15 +101,15 @@ MMCSD_v2_HwAttrs MMCSDInitCfg[MMCSD_CNT] = | |||
101 | { | 101 | { |
102 | 2, | 102 | 2, |
103 | #if defined (__aarch64__) | 103 | #if defined (__aarch64__) |
104 | CSL_MMCSD0_CTL_CFG_BASE, | 104 | CSL_MMC1_CTL_CFG_BASE, |
105 | CSL_MMCSD0_SS_CFG_BASE , /* SS Registers */ | 105 | CSL_MMC1_SS_CFG_BASE , /* SS Registers */ |
106 | CSL_MMCSD0_SS_CFG_BASE + 0x100, | 106 | CSL_MMC1_SS_CFG_BASE + 0x100, |
107 | CSL_GIC0_INTR_MMCSD0_BUS_EMMCSDSS_INTR, /* Corresponds to MPU_IRQ_86 (32 + MPU_IRQ_86) */ | 107 | CSL_GIC0_INTR_MMC1_BUS_EMMCSDSS_INTR, /* Corresponds to MPU_IRQ_86 (32 + MPU_IRQ_86) */ |
108 | 0, | 108 | 0, |
109 | #else | 109 | #else |
110 | CSL_MMCSD0_CTL_CFG_BASE, | 110 | CSL_MMC1_CTL_CFG_BASE, |
111 | CSL_MMCSD0_SS_CFG_BASE , /* SS Registers */ | 111 | CSL_MMC1_SS_CFG_BASE , /* SS Registers */ |
112 | CSL_MMCSD0_SS_CFG_BASE + 0x100, | 112 | CSL_MMC1_SS_CFG_BASE + 0x100, |
113 | CSL_MCU0_INTR_MAIN2MCU_LVL_INTR0_OUTL_0 +22, /* intNum: Choosing random values 21 & 22 */ | 113 | CSL_MCU0_INTR_MAIN2MCU_LVL_INTR0_OUTL_0 +22, /* intNum: Choosing random values 21 & 22 */ |
114 | 0, /* eventNum: Corresponds to MAIN2MCU_INTRTR_LVL_IN_28, or bus_emmcsdss_intr (0) for DMSC firmware */ | 114 | 0, /* eventNum: Corresponds to MAIN2MCU_INTRTR_LVL_IN_28, or bus_emmcsdss_intr (0) for DMSC firmware */ |
115 | #endif | 115 | #endif |