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authorArun Uppuleti2019-04-05 11:32:15 -0500
committerArun Uppuleti2019-04-05 11:32:15 -0500
commit638d87958ff3572fba600434fac4431de42b871c (patch)
tree792bfd62257dc050e230456ce6fb87282c175dc9
parent74db059c48ca5a903dab9cfbf665fd8693de8296 (diff)
downloadserdes_diag-638d87958ff3572fba600434fac4431de42b871c.tar.gz
serdes_diag-638d87958ff3572fba600434fac4431de42b871c.tar.xz
serdes_diag-638d87958ff3572fba600434fac4431de42b871c.zip
Maxwell Serdes Diag integration
Signed-off-by: Arun Uppuleti <auppuleti@ti.com>
Diffstat
-rw-r--r--build/makefile.mk51
-rw-r--r--docs/am65xx/Serdes_Diag_User_Guide.docxbin0 -> 719990 bytes
-rw-r--r--serdes_diag_component.mk195
-rw-r--r--src/am65xx/serdes_diag_k3.c2080
-rw-r--r--src/am65xx/serdes_diag_k3.h490
-rw-r--r--src/src_files_common.mk22
-rw-r--r--test/am65xx/makefile_BER51
-rw-r--r--test/am65xx/makefile_EYE51
-rw-r--r--test/am65xx/serdes_diag_linker_r5.lds83
-rw-r--r--test/am65xx/serdes_diag_platform.h94
-rw-r--r--test/am65xx/serdes_diag_test.c316
-rw-r--r--test/am65xx/serdes_diag_test_init.c237
-rw-r--r--test/src/serdes_diag_test.h6
-rw-r--r--test/src/serdes_diag_test_main.c8
14 files changed, 3683 insertions, 1 deletions
diff --git a/build/makefile.mk b/build/makefile.mk
new file mode 100644
index 0000000..d65f5f1
--- /dev/null
+++ b/build/makefile.mk
@@ -0,0 +1,51 @@
1#
2# Copyright (c) 2016-2018, Texas Instruments Incorporated
3# All rights reserved.
4#
5# Redistribution and use in source and binary forms, with or without
6# modification, are permitted provided that the following conditions
7# are met:
8#
9# * Redistributions of source code must retain the above copyright
10# notice, this list of conditions and the following disclaimer.
11#
12# * Redistributions in binary form must reproduce the above copyright
13# notice, this list of conditions and the following disclaimer in the
14# documentation and/or other materials provided with the distribution.
15#
16# * Neither the name of Texas Instruments Incorporated nor the names of
17# its contributors may be used to endorse or promote products derived
18# from this software without specific prior written permission.
19#
20# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
21# AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
22# THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
23# PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
24# CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
25# EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
26# PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
27# OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
28# WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
29# OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
30# EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
31#
32
33include $(PDK_INSTALL_PATH)/ti/build/Rules.make
34include $(PDK_SERDES_DIAG_COMP_PATH)/src/src_files_common.mk
35
36MODULE_NAME = serdes_diag
37
38# Common source files across all platforms and cores
39
40# List all the external components/interfaces, whose interface header files
41# need to be included for this component
42INCLUDE_EXTERNAL_INTERFACES = pdk
43
44# Include common make files
45ifeq ($(MAKERULEDIR), )
46#Makerule path not defined, define this and assume relative path from ROOTDIR
47 MAKERULEDIR := $(ROOTDIR)/ti/build/makerules
48 export MAKERULEDIR
49endif
50include $(MAKERULEDIR)/common.mk
51# Nothing beyond this point
diff --git a/docs/am65xx/Serdes_Diag_User_Guide.docx b/docs/am65xx/Serdes_Diag_User_Guide.docx
new file mode 100644
index 0000000..8430bac
--- /dev/null
+++ b/docs/am65xx/Serdes_Diag_User_Guide.docx
Binary files differ
diff --git a/serdes_diag_component.mk b/serdes_diag_component.mk
new file mode 100644
index 0000000..a5506b3
--- /dev/null
+++ b/serdes_diag_component.mk
@@ -0,0 +1,195 @@
1#
2# Copyright (c) 2019, Texas Instruments Incorporated
3# All rights reserved.
4#
5# Redistribution and use in source and binary forms, with or without
6# modification, are permitted provided that the following conditions
7# are met:
8#
9# * Redistributions of source code must retain the above copyright
10# notice, this list of conditions and the following disclaimer.
11#
12# * Redistributions in binary form must reproduce the above copyright
13# notice, this list of conditions and the following disclaimer in the
14# documentation and/or other materials provided with the distribution.
15#
16# * Neither the name of Texas Instruments Incorporated nor the names of
17# its contributors may be used to endorse or promote products derived
18# from this software without specific prior written permission.
19#
20# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
21# AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
22# THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
23# PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
24# CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
25# EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
26# PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
27# OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
28# WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
29# OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
30# EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
31#
32
33# File: serdes_diag_component.mk
34# This file is component include make file of Serdes Diag library.
35# List of variables set in this file and their purpose:
36# <mod>_RELPATH - This is the relative path of the module, typically from
37# top-level directory of the package
38# <mod>_PATH - This is the absolute path of the module. It derives from
39# absolute path of the top-level directory (set in env.mk)
40# and relative path set above
41# <mod>_INCLUDE - This is the path that has interface header files of the
42# module. This can be multiple directories (space separated)
43# <mod>_PKG_LIST - Names of the modules (and sub-modules) that are a part
44# part of this module, including itself.
45# <mod>_BOARD_DEPENDENCY - "yes": means the code for this module depends on
46# board and the compiled obj/lib has to be kept
47# under <board> directory
48# "no" or "" or if this variable is not defined: means
49# this module has no board dependent code and hence
50# the obj/libs are not kept under <board> dir.
51# <mod>_CORE_DEPENDENCY - "yes": means the code for this module depends on
52# core and the compiled obj/lib has to be kept
53# under <core> directory
54# "no" or "" or if this variable is not defined: means
55# this module has no core dependent code and hence
56# the obj/libs are not kept under <core> dir.
57# <mod>_APP_STAGE_FILES - List of source files that belongs to the module
58# <mod>, but that needs to be compiled at application
59# build stage (in the context of the app). This is
60# primarily for link time configurations or if the
61# source file is dependent on options/defines that are
62# application dependent. This can be left blank or
63# not defined at all, in which case, it means there
64# no source files in the module <mod> that are required
65# to be compiled in the application build stage.
66#
67ifeq ($(serdes_diag_component_make_include), )
68
69# under other list
70drvserdes_diag_BOARDLIST = am65xx_evm am65xx_idk
71drvserdes_diag_SOCLIST = am65xx
72drvserdes_diag_am574x_CORELIST = c66x a15_0 ipu1_0
73drvserdes_diag_am572x_CORELIST = c66x a15_0 ipu1_0
74drvserdes_diag_am571x_CORELIST = c66x a15_0 ipu1_0
75drvserdes_diag_am437x_CORELIST = a9host
76drvserdes_diag_am335x_CORELIST = a8host
77drvserdes_diag_k2g_CORELIST = c66x a15_0
78drvserdes_diag_dra72x_CORELIST = a15_0 ipu1_0
79drvserdes_diag_dra75x_CORELIST = a15_0 ipu1_0
80drvserdes_diag_dra78x_CORELIST = ipu1_0
81drvserdes_diag_omapl137_CORELIST = c674x arm9_0
82drvserdes_diag_omapl138_CORELIST = c674x arm9_0
83drvserdes_diag_c6657_CORELIST = c66x
84drvserdes_diag_am65xx_CORELIST = mcu1_0
85
86############################
87# serdes_diag package
88# List of components included under serdes_diag lib
89# The components included here are built and will be part of serdes_diag lib
90############################
91serdes_diag_LIB_LIST = serdes_diag
92drvserdes_diag_LIB_LIST = $(serdes_diag_LIB_LIST)
93
94############################
95# serdes_diag examples
96# List of examples under serdes_diag
97# All the tests mentioned in list are built when test target is called
98# List below all examples for allowed values
99############################
100serdes_diag_EXAMPLE_LIST = serdes_diag_BER_app serdes_diag_EYE_app
101drvserdes_diag_EXAMPLE_LIST = $(serdes_diag_EXAMPLE_LIST)
102
103#
104# serdes_diag Modules
105#
106
107# serdes_diag LIB
108serdes_diag_COMP_LIST = serdes_diag
109serdes_diag_RELPATH = ti/diag/serdes_diag
110serdes_diag_PATH = $(PDK_SERDES_DIAG_COMP_PATH)
111serdes_diag_LIBNAME = ti.diag.serdes_diag
112serdes_diag_LIBPATH = $(serdes_diag_PATH)/lib
113serdes_diag_OBJPATH = $(serdes_diag_RELPATH)/serdes_diag
114serdes_diag_MAKEFILE = -f build/makefile.mk
115serdes_diag_BOARD_DEPENDENCY = no
116serdes_diag_CORE_DEPENDENCY = no
117serdes_diag_SOC_DEPENDENCY = yes
118serdes_diag_PKG_LIST = serdes_diag
119serdes_diag_INCLUDE = $(serdes_diag_PATH)
120serdes_diag_SOCLIST = $(drvserdes_diag_SOCLIST)
121serdes_diag_$(SOC)_CORELIST = $(drvserdes_diag_$(SOC)_CORELIST)
122export serdes_diag_COMP_LIST
123export serdes_diag_RELPATH
124export serdes_diag_PATH
125export serdes_diag_LIBNAME
126export serdes_diag_LIBPATH
127export serdes_diag_OBJPATH
128export serdes_diag_MAKEFILE
129export serdes_diag_BOARD_DEPENDENCY
130export serdes_diag_CORE_DEPENDENCY
131export serdes_diag_SOC_DEPENDENCY
132export serdes_diag_PKG_LIST
133export serdes_diag_INCLUDE
134export serdes_diag_SOCLIST
135export serdes_diag_$(SOC)_CORELIST
136
137# serdes_diag unit test app BER
138serdes_diag_BER_app_COMP_LIST = serdes_diag_BER_app
139serdes_diag_BER_app_RELPATH = ti/diag/serdes_diag/test/am65xx
140serdes_diag_BER_app_PATH = $(PDK_SERDES_DIAG_COMP_PATH)/test/am65xx
141serdes_diag_BER_app_BOARD_DEPENDENCY = yes
142serdes_diag_BER_app_CORE_DEPENDENCY = no
143serdes_diag_BER_app_XDC_CONFIGURO = no
144serdes_diag_BER_app_MAKEFILE = -f makefile_BER BAREMETAL=yes
145serdes_diag_BER_app_PKG_LIST = serdes_diag_BER_app
146serdes_diag_BER_app_INCLUDE = $(serdes_diag_BER_app_PATH)
147serdes_diag_BER_app_BOARDLIST = am65xx_evm am65xx_idk
148serdes_diag_BER_app_$(SOC)_CORELIST = $(drvserdes_diag_$(SOC)_CORELIST)
149
150export serdes_diag_BER_app_COMP_LIST
151export serdes_diag_BER_app_$(SOC)_CORELIST
152export serdes_diag_BER_app_RELPATH
153export serdes_diag_BER_app_PATH
154export serdes_diag_BER_app_BOARD_DEPENDENCY
155export serdes_diag_BER_app_CORE_DEPENDENCY
156export serdes_diag_BER_app_XDC_CONFIGURO
157export serdes_diag_BER_app_MAKEFILE
158export serdes_diag_BER_app_PKG_LIST
159export serdes_diag_BER_app_INCLUDE
160export serdes_diag_BER_app_BOARDLIST
161
162# serdes_diag unit test app EYE
163serdes_diag_EYE_app_COMP_LIST = serdes_diag_EYE_app
164serdes_diag_EYE_app_RELPATH = ti/diag/serdes_diag/test/am65xx
165serdes_diag_EYE_app_PATH = $(PDK_SERDES_DIAG_COMP_PATH)/test/am65xx
166serdes_diag_EYE_app_BOARD_DEPENDENCY = yes
167serdes_diag_EYE_app_CORE_DEPENDENCY = no
168serdes_diag_EYE_app_XDC_CONFIGURO = no
169serdes_diag_EYE_app_MAKEFILE = -f makefile_EYE BAREMETAL=yes
170serdes_diag_EYE_app_PKG_LIST = serdes_diag_EYE_app
171serdes_diag_EYE_app_INCLUDE = $(serdes_diag_EYE_app_PATH)
172serdes_diag_EYE_app_BOARDLIST = am65xx_evm am65xx_idk
173serdes_diag_EYE_app_$(SOC)_CORELIST = $(drvserdes_diag_$(SOC)_CORELIST)
174
175export serdes_diag_EYE_app_COMP_LIST
176export serdes_diag_EYE_app_RELPATH
177export serdes_diag_EYE_app_PATH
178export serdes_diag_EYE_app_BOARD_DEPENDENCY
179export serdes_diag_EYE_app_CORE_DEPENDENCY
180export serdes_diag_EYE_app_XDC_CONFIGURO
181export serdes_diag_EYE_app_MAKEFILE
182export serdes_diag_EYE_app_PKG_LIST
183export serdes_diag_EYE_app_INCLUDE
184export serdes_diag_EYE_app_BOARDLIST
185export serdes_diag_EYE_app_$(SOC)_CORELIST
186
187
188
189export drvserdes_diag_LIB_LIST
190export serdes_diag_LIB_LIST
191export serdes_diag_EXAMPLE_LIST
192export drvserdes_diag_EXAMPLE_LIST
193
194serdes_diag_component_make_include := 1
195endif
diff --git a/src/am65xx/serdes_diag_k3.c b/src/am65xx/serdes_diag_k3.c
new file mode 100644
index 0000000..0b52036
--- /dev/null
+++ b/src/am65xx/serdes_diag_k3.c
@@ -0,0 +1,2080 @@
1/**
2 * @file serdes_diag.h
3 *
4 * @brief
5 * Header file for functional layer of DIAGNOSTIC SERDES DIAG.
6 *
7 * It contains the various enumerations, structure definitions and function
8 * declarations
9 *
10 * \par
11 * ============================================================================
12 * @n (C) Copyright 2014, Texas Instruments, Inc.
13 *
14 * Redistribution and use in source and binary forms, with or without
15 * modification, are permitted provided that the following conditions
16 * are met:
17 *
18 * Redistributions of source code must retain the above copyright
19 * notice, this list of conditions and the following disclaimer.
20 *
21 * Redistributions in binary form must reproduce the above copyright
22 * notice, this list of conditions and the following disclaimer in the
23 * documentation and/or other materials provided with the
24 * distribution.
25 *
26 * Neither the name of Texas Instruments Incorporated nor the names of
27 * its contributors may be used to endorse or promote products derived
28 * from this software without specific prior written permission.
29 *
30 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
31 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
32 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
33 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
34 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
35 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
36 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
37 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
38 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
39 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
40 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
41 *
42*/
43
44/** ============================================================================
45 *
46 * @defgroup SERDES_DIAG SERDES DIAG
47 * @ingroup SERDES_DIAG_API
48 *
49 * @section Introduction
50 *
51 * @subsection xxx Overview
52 * A bi-directional BER Test (TX and RX enabled at both ends) can be run across the various TX
53 * filter coefficients (CM, C1 and C2) by using the Serdes_Diag_SweepCMC1C2 API in combination with
54 * synchronizing the TX and RX using DSS. The Serdes Diag package contains serdes_dss.js which
55 * controls the TX/RX synchronization using DSS.
56 *
57 * @subsection References
58 *
59 * ============================================================================
60 */
61
62#include <stdio.h>
63#include <stdint.h>
64#include <string.h>
65#include <ti/csl/soc.h>
66#include <ti/csl/csl.h>
67#include <ti/csl/csl_serdes.h>
68#include <ti/diag/serdes_diag/src/am65xx/serdes_diag_k3.h>
69
70extern void CSL_serdesCycleDelay (uint64_t count);
71
72/* Global Variables used for Synchronization */
73volatile uint16_t serdes_diag_eye_scan_errors_array[SERDES_DIAG_MAX_ARRAY][SERDES_DIAG_MAX_DLY];
74
75volatile uint32_t serdes_diag_dss_lock_key = 0xDEADBEEF;
76volatile uint32_t serdes_diag_dss_unlock_key = 0xBEEFFACE;
77
78/* start locked */
79volatile uint32_t serdes_diag_dss_stall_key0 = 0xDEADBEEF;
80/* start locked */
81volatile uint32_t serdes_diag_dss_stall_key1 = 0xDEADBEEF;
82/* start locked */
83volatile uint32_t serdes_diag_dss_stall_key2 = 0xDEADBEEF;
84/* start locked */
85volatile uint32_t serdes_diag_dss_stall_key3 = 0xDEADBEEF;
86
87volatile uint32_t serdes_diag_dss_stall_flag_set = 0xCAFECAFE;
88volatile uint32_t serdes_diag_dss_stall_flag_clear = 0xCAFEDEAD;
89
90/* start with flag cleared */
91volatile uint32_t serdes_diag_dss_stall_flag0 = 0xCAFEDEAD;
92/* start with flag cleared */
93volatile uint32_t serdes_diag_dss_stall_flag1 = 0xCAFEDEAD;
94/* start with flag cleared */
95volatile uint32_t serdes_diag_dss_stall_flag2 = 0xCAFEDEAD;
96/* start with flag cleared */
97volatile uint32_t serdes_diag_dss_stall_flag3 = 0xCAFEDEAD;
98
99volatile uint32_t serdes_diag_dss_test_complete_flag_set = 0xA5A5A5A5;
100/* start with flag cleared */
101volatile uint32_t serdes_diag_dss_test_complete_flag = 0x5A5A5A5A;
102
103CSL_SerdesTbusDump tbusLaneDump;
104CSL_SerdesTbusDump tbusCMUDump;
105
106/** @addtogroup SERDES_DIAG
107 @{ */
108/** ============================================================================
109 * @n@b Serdes_Diag_SetFESLoopback
110 *
111 * @b Description
112 * @n Function to set the Serdes in FEP Loopback mode
113 *
114 * @b Arguments
115 * @verbatim
116 baseAddr Serdes IP base address
117 *
118 * <b> Return Value </b>
119 * @n None
120 *
121 * <b> Pre Condition </b>
122 * @n None
123 *
124 * <b> Post Condition </b>
125 * @n None
126 *
127 * @b Reads
128 * @n None
129 *
130 * <b> Usage Constraints: </b>
131 * @n None
132 *
133 * @b Example
134 * @verbatim
135
136 @endverbatim
137 * ===========================================================================
138 */
139void Serdes_Diag_SetFESLoopback(uint32_t baseAddr, uint32_t laneNum)
140{
141
142 CSL_FINSR(*(volatile uint32_t *)(baseAddr + 0x200*(laneNum+1) + 0x54),16,16, (uint32_t)0x1);
143}
144
145/** @addtogroup SERDES_DIAG
146 @{ */
147/** ============================================================================
148 * @n@b Serdes_Diag_SetFEPLoopback
149 *
150 * @b Description
151 * @n Function to set the Serdes in FEP Loopback mode
152 *
153 * @b Arguments
154 * @verbatim
155 baseAddr Serdes IP base address
156 *
157 * <b> Return Value </b>
158 * @n None
159 *
160 * <b> Pre Condition </b>
161 * @n None
162 *
163 * <b> Post Condition </b>
164 * @n None
165 *
166 * @b Reads
167 * @n None
168 *
169 * <b> Usage Constraints: </b>
170 * @n None
171 *
172 * @b Example
173 * @verbatim
174
175 @endverbatim
176 * ===========================================================================
177 */
178void Serdes_Diag_SetFEPLoopback(uint32_t baseAddr, uint32_t laneNum)
179{
180
181 /* rxclk_lb_ena_o to 1 */
182 /* dmux_txb_sel_o_2_0 = 5 */
183 /* ahb_tx_clk_brch1_div_sel_o = 0 */
184 /* ahb_tx_clk_brch1_src_sel_o = 2 */
185 /* ahb_tx_pcs_clk_div_en_o =0 */
186 /* clock_gen_override_o = 1 */
187 CSL_FINSR(*(volatile uint32_t *)(baseAddr + 0x200*(laneNum+1) + 0x54),18,18, (uint32_t)0x1);
188
189 CSL_serdesCycleDelay(2000);
190
191 CSL_FINSR(*(volatile uint32_t *)(baseAddr + 0x200*(laneNum+1) + 0x12c),28,26,5);
192 CSL_FINSR(*(volatile uint32_t *)(baseAddr + 0x200*(laneNum+1) + 0x98),15,14,0);
193 CSL_FINSR(*(volatile uint32_t *)(baseAddr + 0x200*(laneNum+1) + 0x0),2,0,2);
194 CSL_FINSR(*(volatile uint32_t *)(baseAddr + 0x200*(laneNum+1) + 0x3c),24,24,1);
195}
196
197/** @addtogroup SERDES_DIAG
198 @{ */
199/** ============================================================================
200 * @n@b Serdes_Diag_SetENCLoopback
201 *
202 * @b Description
203 * @n Function to set the Serdes in ENC Loopback mode
204 *
205 * @b Arguments
206 * @verbatim
207 baseAddr Serdes IP base address
208 *
209 * <b> Return Value </b>
210 * @n None
211 *
212 * <b> Pre Condition </b>
213 * @n None
214 *
215 * <b> Post Condition </b>
216 * @n None
217 *
218 * @b Reads
219 * @n None
220 *
221 * <b> Usage Constraints: </b>
222 * @n None
223 *
224 * @b Example
225 * @verbatim
226
227 @endverbatim
228 * ===========================================================================
229 */
230void Serdes_Diag_SetENCLoopback(uint32_t baseAddr, uint32_t laneNum)
231{
232
233 /*rx_src_o = 0x1
234 ahb_rx_clk_brch1_src_sel_o = 1
235 ahb_rx_clk_brch2_src_sel_o = 1
236 ahb_rx_clk_brch3_src_sel_o = 3
237 ahb_rx_clk_brch4_src_sel_o = 3
238 clock_gen_override_o = 1 */
239
240 CSL_FINSR(*(volatile uint32_t *)(baseAddr + 0x200*(laneNum+1) + 0x12c),8,8,1);
241 CSL_FINSR(*(volatile uint32_t *)(baseAddr + 0x200*(laneNum+1) + 0x0),10,8,1);
242 CSL_FINSR(*(volatile uint32_t *)(baseAddr + 0x200*(laneNum+1) + 0x0),14,12,1);
243 CSL_FINSR(*(volatile uint32_t *)(baseAddr + 0x200*(laneNum+1) + 0x0),18,16,3);
244 CSL_FINSR(*(volatile uint32_t *)(baseAddr + 0x200*(laneNum+1) + 0x0),22,20,3);
245 CSL_FINSR(*(volatile uint32_t *)(baseAddr + 0x200*(laneNum+1) + 0x3c),24,24,1);
246}
247
248/** @addtogroup SERDES_DIAG
249 @{ */
250/** ============================================================================
251 * @n@b Serdes_Diag_SetFEP1p5Loopback
252 *
253 * @b Description
254 * @n Function to set the Serdes in FEP1p5 Loopback mode
255 *
256 * @b Arguments
257 * @verbatim
258 baseAddr Serdes IP base address
259 *
260 * <b> Return Value </b>
261 * @n None
262 *
263 * <b> Pre Condition </b>
264 * @n None
265 *
266 * <b> Post Condition </b>
267 * @n None
268 *
269 * @b Reads
270 * @n None
271 *
272 * <b> Usage Constraints: </b>
273 * @n None
274 *
275 * @b Example
276 * @verbatim
277
278 @endverbatim
279 * ===========================================================================
280 */
281void Serdes_Diag_SetFEP1p5Loopback(uint32_t baseAddr, uint32_t laneNum)
282{
283
284 CSL_FINSR(*(volatile uint32_t *)(baseAddr + 0x200*(laneNum+1) + 0x04c),23,22,0); //Mode = 0 to disable symbol alignment
285
286 // rxclk_lb_ena_o = 1
287 // dmux_txb_sel_o = 6
288 // ahb_tx_clk_brch1_div_sel_o = 0
289 // ahb_tx_clk_brch1_src_sel_o = 2
290 // clock_gen_override_o = 1
291 CSL_FINSR(*(volatile uint32_t *)(baseAddr + 0x200*(laneNum+1) + 0x54),18,18, (uint32_t)0x1);
292 CSL_serdesCycleDelay(2000);
293 CSL_FINSR(*(volatile uint32_t *)(baseAddr + 0x200*(laneNum+1) + 0x12c),28,26,6);
294 CSL_FINSR(*(volatile uint32_t *)(baseAddr + 0x200*(laneNum+1) + 0x98),15,14,0);
295 CSL_FINSR(*(volatile uint32_t *)(baseAddr + 0x200*(laneNum+1) + 0x0),2,0,2);
296 CSL_FINSR(*(volatile uint32_t *)(baseAddr + 0x200*(laneNum+1) + 0x3c),24,24,1);
297}
298
299void Serdes_Diag_PCIeCtrlOverride(const SERDES_DIAG_BER_INIT_T *berParamsInit)
300{
301
302 int laneNum, stat;
303 /* override value for ln_ctrl_i[25:0]:
304 lnX_txdetectrx_lb_i(lnX_ctrl_i[0]) - 0x1(PIPE LOOPBACK - Put PCIe in Loopback once phystatus is done) - not needed,
305 lnX_txelecidle_i(lnX_ctrl_i[1]) - 0x1(lnX_txelecidle_i must be asserted in P0s and P1),
306 lnX_txswing_i(lnX_ctrl_i[7]) - 0x0(Full swing),
307 lnX_block_align_control_i(lnX_ctrl_i[8]) - 0x1(Controls whether the PHY performs Block alignment in PCIe Gen3 mode),
308 lnX_txstart_block_i(lnX_ctrl_i[9]) - 0x1(This signal allows the MAC to tell the PHY the starting byte for a 128b block) - not needed,
309 lnX_txdata_valid_i(lnX_ctrl_i[11]) - 0x1(indicates the PHY will use the data),
310 lnX_txdeemph_i(lnX_ctrl_i[34:17]) - Gen3:TxDeemph[5:0] - C-1 precursor coefficient */
311
312// CSL_serdesAssertReset(berParamsInit->baseAddr, berParamsInit->phyType, berParamsInit->laneMask);
313//
314// CSL_SerdesConfigCMC1C2(berParamsInit->baseAddr, laneNum, cm,
315// 6, c2, berParamsInit->phyType);
316//
317// CSL_serdesDeassertReset(berParamsInit->baseAddr,
318// berParamsInit->phyType,
319// berParamsInit->laneMask);
320 for(laneNum=0;laneNum<SERDES_DIAG_MAX_LANES;laneNum++)
321 {
322 if ((berParamsInit->laneMask & (1<<laneNum))!=0)
323 {
324 CSL_FINSR(*(volatile uint32_t *)(SERDES_DIAG_LANE_MAP(berParamsInit->baseAddr, laneNum, 0x140)), 31, 6, (uint32_t)0x0010902);
325
326 /* Override values for ln_ctrl_i[42:26] */
327 CSL_FINSR(*(volatile uint32_t *)(SERDES_DIAG_LANE_MAP(berParamsInit->baseAddr, laneNum, 0x144)), 15, 0, (uint32_t)0x0);
328
329 /* override value for ln_ctrl_i[43] */
330 CSL_FINSR(*(volatile uint32_t *)(SERDES_DIAG_LANE_MAP(berParamsInit->baseAddr, laneNum, 0x148)), 20, 20, (uint32_t)0x0);
331
332 /* override value for ln_ctrl_i[47] - lnX_rx_standby_i - Puts Rx into standby mode in P0 state */
333 CSL_FINSR(*(volatile uint32_t *)(SERDES_DIAG_LANE_MAP(berParamsInit->baseAddr, laneNum, 0x148)), 8, 8, (uint32_t)0x0);
334
335 if (berParamsInit->pcieGenType == SERDES_DIAG_PCIE_GEN3)
336 {
337 /* Set lnX_ctrl_i[46:44] PCIe clock freq of PCS-MAC to 250MHz */
338 CSL_FINSR(*(volatile uint32_t *)(SERDES_DIAG_LANE_MAP(berParamsInit->baseAddr, laneNum, 0x148)), 23,21,2);
339 /* Set lnX_ctrl_i[49:48] bus width for 32 bit */
340 CSL_FINSR(*(volatile uint32_t *)(SERDES_DIAG_LANE_MAP(berParamsInit->baseAddr, laneNum, 0x148)), 25,24,2);
341 }
342 else if (berParamsInit->pcieGenType == SERDES_DIAG_PCIE_GEN2)
343 {
344 /* Set lnX_ctrl_i[46:44] PCIe clock freq of PCS-MAC to 250MHz */
345 CSL_FINSR(*(volatile uint32_t *)(SERDES_DIAG_LANE_MAP(berParamsInit->baseAddr, laneNum, 0x148)), 23,21,2);
346 /* Set lnX_ctrl_i[49:48] bus width for 32 bit */
347 CSL_FINSR(*(volatile uint32_t *)(SERDES_DIAG_LANE_MAP(berParamsInit->baseAddr, laneNum, 0x148)), 25,24,1);
348 }
349 else if (berParamsInit->pcieGenType == SERDES_DIAG_PCIE_GEN1)
350 {
351 /* Set lnX_ctrl_i[46:44] PCIe clock freq of PCS-MAC to 250MHz */
352 CSL_FINSR(*(volatile uint32_t *)(SERDES_DIAG_LANE_MAP(berParamsInit->baseAddr, laneNum, 0x148)), 23,21,2);
353 /* Set lnX_ctrl_i[49:48] bus width for 32 bit */
354 CSL_FINSR(*(volatile uint32_t *)(SERDES_DIAG_LANE_MAP(berParamsInit->baseAddr, laneNum, 0x148)), 25,24,0);
355 }
356
357 /* Set lnX_pd_i[2:0] to P1 for PCIe mode */
358// CSL_FINSR(*(volatile uint32_t *)(SERDES_DIAG_LANE_MAP(berParamsInit->baseAddr, laneNum, 0x140)), 5,4,2);
359 CSL_FINSR(*(volatile uint32_t *)(SERDES_DIAG_LANE_MAP(berParamsInit->baseAddr, laneNum, 0x140)), 5,4,0);
360
361 /* Set lnX_rate_i[1:0] for PCIe initial bringup rate */
362// CSL_FINSR(*(volatile uint32_t *)(SERDES_DIAG_LANE_MAP(berParamsInit->baseAddr, laneNum, 0x140)), 3,2,0);
363
364 /* Make sure ln_rstn is still in reset state 0x0 */
365 do
366 {
367 stat = (CSL_serdesReadSelectedTbus(berParamsInit->baseAddr, laneNum+1, 0x1) & 0x040)>>6;
368 } while(stat == 1);
369
370 /* Set lnX_rate_i[1:0] for PCIe Gen2 data rate */
371 if (berParamsInit->pcieGenType == SERDES_DIAG_PCIE_GEN3)
372 {
373 CSL_FINSR(*(volatile uint32_t *)(SERDES_DIAG_LANE_MAP(berParamsInit->baseAddr, laneNum, 0x140)), 3,2,2);
374 }
375 else if (berParamsInit->pcieGenType == SERDES_DIAG_PCIE_GEN2)
376 {
377 CSL_FINSR(*(volatile uint32_t *)(SERDES_DIAG_LANE_MAP(berParamsInit->baseAddr, laneNum, 0x140)), 3,2,1);
378 }
379 else if (berParamsInit->pcieGenType == SERDES_DIAG_PCIE_GEN1)
380 {
381 CSL_FINSR(*(volatile uint32_t *)(SERDES_DIAG_LANE_MAP(berParamsInit->baseAddr, laneNum, 0x140)), 3,2,0);
382 }
383
384 CSL_serdesEnableLanes(berParamsInit->baseAddr, laneNum);
385 CSL_serdesCycleDelay(300000);
386
387 /* override ln_rstn to 0x1 to bring it out of reset */
388 CSL_FINSR(*(volatile uint32_t *)(SERDES_DIAG_LANE_MAP(berParamsInit->baseAddr, laneNum, 0x140)), 1,1,1);
389
390 /* Set Lane override enable to override all the settings */
391 CSL_FINSR(*(volatile uint32_t *)(SERDES_DIAG_LANE_MAP(berParamsInit->baseAddr, laneNum, 0x140)), 0,0,1);
392 CSL_serdesCycleDelay(300000);
393
394 /* check “ln_ok” status, for PCIe and USB we wait for de-assertion of “phystatus */
395 do
396 {
397 stat = (CSL_serdesReadSelectedTbus(berParamsInit->baseAddr, laneNum+1, 0x7) & 0x002)>>1;
398 } while(stat == 1);
399
400// /* Set lnX_pd_i[2:0] to P0 for BER mode PCIe and USB only */
401// CSL_FINSR(*(volatile uint32_t *)(SERDES_DIAG_LANE_MAP(berParamsInit->baseAddr, laneNum, 0x140)), 5,4,0);
402// CSL_serdesCycleDelay(300000);
403
404// /* Force Receiver in Reset to prevent adaptation */
405// CSL_FINSR(*(volatile uint32_t *)(SERDES_DIAG_LANE_MAP(berParamsInit->baseAddr, laneNum, 0x13c)), 17,16,2); /* Reset Receiver */
406
407 /* Add 300us delay */
408 CSL_serdesCycleDelay(300000);
409 }
410 }
411}
412
413void Serdes_Diag_USBCtrlOverride(const SERDES_DIAG_BER_INIT_T *berParamsInit)
414{
415 int stat, laneNum;
416 for(laneNum=0;laneNum<SERDES_DIAG_MAX_LANES;laneNum++)
417 {
418 if ((berParamsInit->laneMask & (1<<laneNum))!=0)
419 {
420 /* override value for ln_ctrl_i[25:0]: */
421 CSL_FINSR(*(volatile uint32_t *)(SERDES_DIAG_LANE_MAP(berParamsInit->baseAddr, laneNum, 0x140)), 31, 6, (uint32_t)0x0000802);
422
423 /* Override values for ln_ctrl_i[42:26] */
424 CSL_FINSR(*(volatile uint32_t *)(SERDES_DIAG_LANE_MAP(berParamsInit->baseAddr, laneNum, 0x144)), 15, 0, (uint32_t)0x0);
425
426 /* override value for ln_ctrl_i[43] */
427 CSL_FINSR(*(volatile uint32_t *)(SERDES_DIAG_LANE_MAP(berParamsInit->baseAddr, laneNum, 0x148)), 20, 20, (uint32_t)0x0);
428
429 /* override value for ln_ctrl_i[46:44] - lnX_pclk_rate_i - select 250Mhz for PCIe */
430 CSL_FINSR(*(volatile uint32_t *)(SERDES_DIAG_LANE_MAP(berParamsInit->baseAddr, laneNum, 0x148)), 23, 21, (uint32_t)0x2); //test 0x1 for 125MHz
431
432 /* override value for ln_ctrl_i[47] - lnX_rx_standby_i - Puts Rx into standby mode in P0 state */
433 CSL_FINSR(*(volatile uint32_t *)(SERDES_DIAG_LANE_MAP(berParamsInit->baseAddr, laneNum, 0x148)), 8, 8, (uint32_t)0x0);
434
435 /* Set lnX_ctrl_i[49:48] bus width for 16 bit */
436 CSL_FINSR(*(volatile uint32_t *)(SERDES_DIAG_LANE_MAP(berParamsInit->baseAddr, laneNum, 0x148)), 25,24,1);
437
438 /* Set lnX_ctrl_i[56] and [51] */
439 CSL_FINSR(*(volatile uint32_t *)(SERDES_DIAG_LANE_MAP(berParamsInit->baseAddr, laneNum, 0x148)), 9,9,0x1);
440 CSL_FINSR(*(volatile uint32_t *)(SERDES_DIAG_LANE_MAP(berParamsInit->baseAddr, laneNum, 0x148)), 14,14,0x1);
441
442 /* Set lnX_pd_i[2:0] to P2 for USB mode */
443 CSL_FINSR(*(volatile uint32_t *)(SERDES_DIAG_LANE_MAP(berParamsInit->baseAddr, laneNum, 0x140)), 5,4,3);
444
445 /* Set lnX_rate_i[1:0] for USB initial bringup rate */
446 CSL_FINSR(*(volatile uint32_t *)(SERDES_DIAG_LANE_MAP(berParamsInit->baseAddr, laneNum, 0x140)), 3,2,1);
447
448 /* FEP and FES specific settings */
449 if (berParamsInit->loopbackType == CSL_SERDES_LOOPBACK_FEP || berParamsInit->loopbackType == CSL_SERDES_LOOPBACK_FES)
450 {
451 CSL_FINSR(*(volatile uint32_t *)(SERDES_DIAG_LANE_MAP(berParamsInit->baseAddr, laneNum, 0x3C)), 24,24,1); // clock gen override default 0
452 CSL_FINSR(*(volatile uint32_t *)(SERDES_DIAG_LANE_MAP(berParamsInit->baseAddr, laneNum, 0x00)), 18,16,1); // RX_CLK_BRCH3_SRC_sel default 0
453 CSL_FINSR(*(volatile uint32_t *)(SERDES_DIAG_LANE_MAP(berParamsInit->baseAddr, laneNum, 0x00)), 19,19,1); // RX_CLK_BRCH3_div_sel default 1
454 }
455
456 /* Make sure ln_rstn is still in reset state 0x0 */
457 do
458 {
459 stat = (CSL_serdesReadSelectedTbus(berParamsInit->baseAddr, laneNum+1, 0x1) & 0x040)>>6;
460 } while(stat == 1);
461
462 CSL_serdesEnableLanes(berParamsInit->baseAddr, laneNum);
463 CSL_serdesCycleDelay(300000);
464
465 /* override ln_rstn to 0x1 to bring it out of reset */
466 CSL_FINSR(*(volatile uint32_t *)(SERDES_DIAG_LANE_MAP(berParamsInit->baseAddr, laneNum, 0x140)), 1,1,1);
467
468 /* Set Lane override enable to override all the settings */
469 CSL_FINSR(*(volatile uint32_t *)(SERDES_DIAG_LANE_MAP(berParamsInit->baseAddr, laneNum, 0x140)), 0,0,1);
470 CSL_serdesCycleDelay(300000);
471
472 /* check “ln_ok” status, for PCIe and USB we wait for de-assertion of “phystatus */
473 do
474 {
475 stat = (CSL_serdesReadSelectedTbus(berParamsInit->baseAddr, laneNum+1, 0x7) & 0x002)>>1;
476 } while(stat == 1);
477
478 /* Set lnX_pd_i[2:0] to P0 for BER mode PCIe and USB only */
479 CSL_FINSR(*(volatile uint32_t *)(SERDES_DIAG_LANE_MAP(berParamsInit->baseAddr, laneNum, 0x140)), 5,4,0);
480 CSL_serdesCycleDelay(300000);
481
482 /* PIPE loopback settings */
483 if(berParamsInit->loopbackType == CSL_SERDES_LOOPBACK_PIPE)
484 {
485 /* override value for ln_ctrl_i[0] for PIPE loopback */
486 CSL_FINSR(*(volatile uint32_t *)(SERDES_DIAG_LANE_MAP(berParamsInit->baseAddr, laneNum, 0x140)), 6, 6, (uint32_t)0x1);
487 }
488 }
489 }
490}
491
492void Serdes_Diag_SGMIICtrlOverride(const SERDES_DIAG_BER_INIT_T *berParamsInit)
493{
494 int iTemp = berParamsInit->laneCtrlRate, stat, laneNum;
495 if(iTemp ==2) iTemp = 3;
496
497 for(laneNum=0;laneNum<SERDES_DIAG_MAX_LANES;laneNum++)
498 {
499 if ((berParamsInit->laneMask & (1<<laneNum))!=0)
500 {
501 /* Set ln_ctrl_i[3:0] bit 0 for 10b data */
502 CSL_FINSR(*(volatile uint32_t *)(SERDES_DIAG_LANE_MAP(berParamsInit->baseAddr, laneNum, 0x140)), 6,6,1);
503 /* Set ln_ctrl_i[7:6] for 10b data */
504 CSL_FINSR(*(volatile uint32_t *)(SERDES_DIAG_LANE_MAP(berParamsInit->baseAddr, laneNum, 0x140)), 13,12,0);
505 /* Set lnX_rate_i[1:0] for SGMII data rate */
506 CSL_FINSR(*(volatile uint32_t *)(SERDES_DIAG_LANE_MAP(berParamsInit->baseAddr, laneNum, 0x140)), 20,18,iTemp);
507 CSL_FINSR(*(volatile uint32_t *)(SERDES_DIAG_LANE_MAP(berParamsInit->baseAddr, laneNum, 0x140)), 3,2,iTemp);
508 /* Set lnX_pd_i[2:0] to P0 for SGMII mode */
509 CSL_FINSR(*(volatile uint32_t *)(SERDES_DIAG_LANE_MAP(berParamsInit->baseAddr, laneNum, 0x140)), 5,4,0);
510
511 /* Make sure ln_rstn is still in reset state 0x0 */
512 do
513 {
514 stat = (CSL_serdesReadSelectedTbus(berParamsInit->baseAddr, laneNum+1, 0x1) & 0x040)>>6;
515 } while(stat == 1);
516
517 // CSL_serdesEnableLanes(berParamsInit->baseAddr, laneNum);
518 CSL_serdesCycleDelay(300000);
519
520 /* Set Lane override enable to override all the settings */
521 CSL_FINSR(*(volatile uint32_t *)(SERDES_DIAG_LANE_MAP(berParamsInit->baseAddr, laneNum, 0x140)), 1,0,1);
522 CSL_serdesCycleDelay(300000);
523
524 /* override ln_rstn to 0x1 to bring it out of reset */
525 CSL_FINSR(*(volatile uint32_t *)(SERDES_DIAG_LANE_MAP(berParamsInit->baseAddr, laneNum, 0x140)), 1,1,1);
526
527 /* check “ln_ok” status, for PCIe and USB we wait for de-assertion of “phystatus */
528 do
529 {
530 stat = (CSL_serdesReadSelectedTbus(berParamsInit->baseAddr, laneNum+1, 0x8) & 0x010)>>4;
531 } while(stat == 0);
532
533 //Hardcoding AHB_TX_LN_DIV_SEL_O for quarter rate (only needed for quarter rate)
534 if(iTemp == 3)
535 {
536 CSL_FINSR(*(volatile uint32_t *)(SERDES_DIAG_LANE_MAP(berParamsInit->baseAddr, laneNum, 0x1A0)), 31,29,0x7);
537 }
538 }
539 }
540}
541
542
543/** @addtogroup SERDES_DIAG
544 @{ */
545/** ============================================================================
546 * @n@b Serdes_Diag_BERTest_TX
547 *
548 * @b Description
549 * @n This API is used for setting up the Transmitter PRBS generator.
550 *
551 * @b Arguments
552 * @verbatim
553 berParamsInit Structure to the BER Initialization Parameters
554 *
555 * <b> Return Value </b>
556 * @n None
557 *
558 * <b> Pre Condition </b>
559 * @n None
560 *
561 * <b> Post Condition </b>
562 * @n None
563 *
564 * @b Reads
565 * @n None
566 *
567 * <b> Usage Constraints: </b>
568 * @n None
569 *
570 * @b Example
571 * @verbatim
572
573 Serdes_Diag_BERTest_TX(&berParamsInit);
574
575 @endverbatim
576 * ===========================================================================
577 */
578SERDES_DIAG_STAT Serdes_Diag_BERTestTX(const SERDES_DIAG_BER_INIT_T *berParamsInit)
579{
580 uint32_t laneNum, stat;
581
582 /* Clear Bit 29 of lane 004 to 0 bist_gen_cdn */
583 for(laneNum=0;laneNum<SERDES_DIAG_MAX_LANES;laneNum++)
584 {
585 if ((berParamsInit->laneMask & (1<<laneNum))!=0)
586 {
587 CSL_FINSR(*(volatile uint32_t *)(SERDES_DIAG_LANE_MAP(berParamsInit->baseAddr, laneNum, 0x4)),29,29,0);
588 }
589 }
590
591 /* Set 28 [bist_tx_clock_enable] of lane 004 to 1 */
592 /* Set 31 [bist_rx_clock_enable] of lane 00c to 1 */
593 /* Set 27 [bist_chk_data_mode] of lane 00c to 1 for PRBS pattern */
594
595 for(laneNum=0;laneNum<SERDES_DIAG_MAX_LANES;laneNum++)
596 {
597 if ((berParamsInit->laneMask & (1<<laneNum))!=0)
598 {
599 CSL_FINSR(*(volatile uint32_t *)(SERDES_DIAG_LANE_MAP(berParamsInit->baseAddr, laneNum, 0x04)),28,28,berParamsInit->bistTxClkEn);
600 CSL_FINSR(*(volatile uint32_t *)(SERDES_DIAG_LANE_MAP(berParamsInit->baseAddr, laneNum, 0x0c)),31,31,berParamsInit->bistRxClkEn);
601 if (berParamsInit->prbsPattern == SERDES_UDP)
602 {
603 CSL_FINSR(*(volatile uint32_t *)(SERDES_DIAG_LANE_MAP(berParamsInit->baseAddr, laneNum, 0x0c)),27,27,0); //UDP mode
604 }
605 else
606 {
607 CSL_FINSR(*(volatile uint32_t *)(SERDES_DIAG_LANE_MAP(berParamsInit->baseAddr, laneNum, 0x0c)),27,27,1); //PRBS mode
608 }
609
610 /* [bist_gen_mode8B] */
611 /* [bist_rate_o] */
612 /* [bist_gen_word] */
613 if (berParamsInit->phyType == CSL_SERDES_PHY_TYPE_PCIe)
614 {
615 if (berParamsInit->prbsPattern == SERDES_UDP || berParamsInit->loopbackType == CSL_SERDES_LOOPBACK_TX_TO_BERT)
616 {
617 CSL_FINSR(*(volatile uint32_t *)(SERDES_DIAG_LANE_MAP(berParamsInit->baseAddr, laneNum, 0x04)),26,26,0); //UDP mode
618 }
619 else
620 {
621 CSL_FINSR(*(volatile uint32_t *)(SERDES_DIAG_LANE_MAP(berParamsInit->baseAddr, laneNum, 0x04)),26,26,1); //PRBS mode
622 }
623
624 /* Set Bus Width to 8 bit interface for PCIe GEN 1 */
625 if(berParamsInit->pcieGenType == SERDES_DIAG_PCIE_GEN1)
626 {
627 CSL_FINSR(*(volatile uint32_t *)(SERDES_DIAG_LANE_MAP(berParamsInit->baseAddr, laneNum, 0x04)),25,24,0);
628 CSL_FINSR(*(volatile uint32_t *)(SERDES_DIAG_LANE_MAP(berParamsInit->baseAddr, laneNum, 0x04)),30,30,0);
629 }
630 /* Set BUS Width to 16 bit interface for PCIe GEN 2 */
631 else if(berParamsInit->pcieGenType == SERDES_DIAG_PCIE_GEN2)
632 {
633 CSL_FINSR(*(volatile uint32_t *)(SERDES_DIAG_LANE_MAP(berParamsInit->baseAddr, laneNum, 0x04)),25,24,1);
634 CSL_FINSR(*(volatile uint32_t *)(SERDES_DIAG_LANE_MAP(berParamsInit->baseAddr, laneNum, 0x04)),30,30,1);
635 }
636 /* Set BUS Width to 32 bit interface for PCIe GEN 3 */
637 else if(berParamsInit->pcieGenType == SERDES_DIAG_PCIE_GEN3)
638 {
639 CSL_FINSR(*(volatile uint32_t *)(SERDES_DIAG_LANE_MAP(berParamsInit->baseAddr, laneNum, 0x04)),25,24,2);
640 CSL_FINSR(*(volatile uint32_t *)(SERDES_DIAG_LANE_MAP(berParamsInit->baseAddr, laneNum, 0x04)),30,30,1);
641 }
642 }
643
644 /* Set BUS Width to 10 bit interface for SGMII */
645 else if(berParamsInit->phyType == CSL_SERDES_PHY_TYPE_SGMII)
646 {
647 CSL_FINSR(*(volatile uint32_t *)(SERDES_DIAG_LANE_MAP(berParamsInit->baseAddr, laneNum, 0x04)),26,26,0);
648 CSL_FINSR(*(volatile uint32_t *)(SERDES_DIAG_LANE_MAP(berParamsInit->baseAddr, laneNum, 0x04)),30,30,0);
649 }
650
651 /* Set BUS Width to 20 bit interface for USB */
652 else if(berParamsInit->phyType == CSL_SERDES_PHY_TYPE_USB)
653 {
654 CSL_FINSR(*(volatile uint32_t *)(SERDES_DIAG_LANE_MAP(berParamsInit->baseAddr, laneNum, 0x04)),26,26,0);
655 CSL_FINSR(*(volatile uint32_t *)(SERDES_DIAG_LANE_MAP(berParamsInit->baseAddr, laneNum, 0x04)),25,24,0);
656 CSL_FINSR(*(volatile uint32_t *)(SERDES_DIAG_LANE_MAP(berParamsInit->baseAddr, laneNum, 0x04)),30,30,1);
657 }
658 }
659 }
660
661 /* Clear Bit 31 of lane 004 to 0 bist_gen_en_o */
662 for(laneNum=0;laneNum<SERDES_DIAG_MAX_LANES;laneNum++)
663 {
664 if ((berParamsInit->laneMask & (1<<laneNum))!=0)
665 {
666 CSL_FINSR(*(volatile uint32_t *)(SERDES_DIAG_LANE_MAP(berParamsInit->baseAddr, laneNum, 0x4)),31,31,0);
667 }
668 }
669
670 /* Set Bit 29:28 to PRBS pattern on LANE 00c - Field 0-PRBS7, 1-PRBS15, 2-PRBS23, 3-PRBS31 */
671 /* bist_chk_lfsr_length */
672 for(laneNum=0;laneNum<SERDES_DIAG_MAX_LANES;laneNum++)
673 {
674 if ((berParamsInit->laneMask & (1<<laneNum))!=0)
675 {
676 if (!(berParamsInit->prbsPattern == SERDES_UDP))
677 {
678 CSL_FINSR(*(volatile uint32_t *)(SERDES_DIAG_LANE_MAP(berParamsInit->baseAddr, laneNum, 0x0c)),29,28,berParamsInit->prbsPattern);
679 }
680 }
681 }
682
683 /* SET BIT 9 and bit 8 of comlane 000 to 1 */
684 /* 1 bist_gen_inv_prbs */
685 /* 1 bist_chk_inv_prbs */
686 CSL_FINSR(*(volatile uint32_t *)(SERDES_DIAG_COMLANE_MAP(berParamsInit->baseAddr, 0x0)),9,9,1);
687 CSL_FINSR(*(volatile uint32_t *)(SERDES_DIAG_COMLANE_MAP(berParamsInit->baseAddr, 0x0)),8,8,1);
688
689 /* Set LANE 10 bits 9:0 to 0x283 */
690 /* bist_chk_pream0 */
691 /* Set LANE 10 bits 25:16 to 0x17C */
692 /* bist_chk_pream1 */
693 for(laneNum=0;laneNum<SERDES_DIAG_MAX_LANES;laneNum++)
694 {
695 if ((berParamsInit->laneMask & (1<<laneNum))!=0)
696 {
697 if(berParamsInit->phyType == CSL_SERDES_PHY_TYPE_USB || berParamsInit->phyType == CSL_SERDES_PHY_TYPE_PCIe)
698 {
699 CSL_FINSR(*(volatile uint32_t *)(SERDES_DIAG_LANE_MAP(berParamsInit->baseAddr, laneNum, 0x10)),9,0,0x1bc);
700 CSL_FINSR(*(volatile uint32_t *)(SERDES_DIAG_LANE_MAP(berParamsInit->baseAddr, laneNum, 0x10)),25,16,0x1bc);
701 }
702 else
703 {
704 CSL_FINSR(*(volatile uint32_t *)(SERDES_DIAG_LANE_MAP(berParamsInit->baseAddr, laneNum, 0x10)),9,0,0x283);
705 CSL_FINSR(*(volatile uint32_t *)(SERDES_DIAG_LANE_MAP(berParamsInit->baseAddr, laneNum, 0x10)),25,16,0x17c);
706 }
707 }
708 }
709
710 /*bist_chk_udp Lane 0x14 bits 31:0 and lane 0x18 bits 7:0 to 0x0 */
711 /*bist_gen_en_low Lane 0x08 bits 23:8 to 0x0 */
712 /*bist_gen_en_high Lane 0x08 and lane 0x0c bits 31:24, bits 7:0 to 0x0 */
713 /*bist_chk_insert_word Lane 0x18 and lane 0x1c bits 31:8, bits 15:0 to 0x0 */
714 /*bist_chk_insert_length Lane 0x10 bits 12:10 to 0x0 */
715 /*bist_gen_insert_count Lane 0x08 bits 6:4 to 0x0 */
716 /*bist_gen_insert_delay Lane 0xc bits 19:16 to 0x0 */
717 for(laneNum=0;laneNum<SERDES_DIAG_MAX_LANES;laneNum++)
718 {
719 if ((berParamsInit->laneMask & (1<<laneNum))!=0)
720 {
721 if (berParamsInit->prbsPattern == SERDES_UDP)
722 {
723 *(volatile uint32_t *)(SERDES_DIAG_LANE_MAP(berParamsInit->baseAddr, laneNum, 0x14)) = (uint32_t)0xAAAAAAAA;
724 CSL_FINSR(*(volatile uint32_t *)(SERDES_DIAG_LANE_MAP(berParamsInit->baseAddr, laneNum, 0x18)), 7,0,0xAA);
725 }
726 else
727 {
728 *(volatile uint32_t *)(SERDES_DIAG_LANE_MAP(berParamsInit->baseAddr, laneNum, 0x14)) = (uint32_t)0x0;
729 CSL_FINSR(*(volatile uint32_t *)(SERDES_DIAG_LANE_MAP(berParamsInit->baseAddr, laneNum, 0x18)), 7,0,0x0);
730 }
731
732 CSL_FINSR(*(volatile uint32_t *)(SERDES_DIAG_LANE_MAP(berParamsInit->baseAddr, laneNum, 0x08)), 23,8,0x0);
733
734 CSL_FINSR(*(volatile uint32_t *)(SERDES_DIAG_LANE_MAP(berParamsInit->baseAddr, laneNum, 0x08)), 31,24,0x0);
735 CSL_FINSR(*(volatile uint32_t *)(SERDES_DIAG_LANE_MAP(berParamsInit->baseAddr, laneNum, 0x0c)), 7,0,0x0);
736
737 CSL_FINSR(*(volatile uint32_t *)(SERDES_DIAG_LANE_MAP(berParamsInit->baseAddr, laneNum, 0x18)), 31,8,0x0);
738 CSL_FINSR(*(volatile uint32_t *)(SERDES_DIAG_LANE_MAP(berParamsInit->baseAddr, laneNum, 0x1c)), 15,0,0x0);
739
740 CSL_FINSR(*(volatile uint32_t *)(SERDES_DIAG_LANE_MAP(berParamsInit->baseAddr, laneNum, 0x10)), 12,10,0x0);
741
742 CSL_FINSR(*(volatile uint32_t *)(SERDES_DIAG_LANE_MAP(berParamsInit->baseAddr, laneNum, 0x8)), 6,4,0x0);
743
744 CSL_FINSR(*(volatile uint32_t *)(SERDES_DIAG_LANE_MAP(berParamsInit->baseAddr, laneNum, 0xc)), 19,8,0x0);
745 }
746 }
747
748 /* Wait a minimum of 20ns let us put 50ns just in case */
749 CSL_serdesCycleDelay(50);
750
751 /* Step 4. Deassert bist_gen_cdn by setting 1 on bit 29 of lane 004 */
752 for(laneNum=0;laneNum<SERDES_DIAG_MAX_LANES;laneNum++)
753 {
754 if ((berParamsInit->laneMask & (1<<laneNum))!=0)
755 {
756 CSL_FINSR(*(volatile uint32_t *)(SERDES_DIAG_LANE_MAP(berParamsInit->baseAddr, laneNum, 0x4)), 29,29,1);
757 }
758 }
759
760 /* Step 5. Set Lane 0x12c */
761 /* dmux_txa_sel Lane 0x12c [13:12] 0x3 */
762 /* dmux_txb_sel Lane 0x12c [28:26] 0x0 */
763 for(laneNum=0;laneNum<SERDES_DIAG_MAX_LANES;laneNum++)
764 {
765 if ((berParamsInit->laneMask & (1<<laneNum))!=0)
766 {
767 if(berParamsInit->phyType == CSL_SERDES_PHY_TYPE_PCIe)
768 {
769 if(berParamsInit->pcieGenType == SERDES_DIAG_PCIE_GEN1 || berParamsInit->pcieGenType == SERDES_DIAG_PCIE_GEN2)
770 {
771 CSL_FINSR(*(volatile uint32_t *)(SERDES_DIAG_LANE_MAP(berParamsInit->baseAddr, laneNum, 0x12c)), 13,12,3);
772
773 if (berParamsInit->prbsPattern == SERDES_UDP || berParamsInit->loopbackType == CSL_SERDES_LOOPBACK_TX_TO_BERT)
774 {
775 CSL_FINSR(*(volatile uint32_t *)(SERDES_DIAG_LANE_MAP(berParamsInit->baseAddr, laneNum, 0x12c)),28,26,7);
776 }
777 else
778 {
779 CSL_FINSR(*(volatile uint32_t *)(SERDES_DIAG_LANE_MAP(berParamsInit->baseAddr, laneNum, 0x12c)),28,26,0);
780 }
781 }
782 else if(berParamsInit->pcieGenType == SERDES_DIAG_PCIE_GEN3)
783 {
784 CSL_FINSR(*(volatile uint32_t *)(SERDES_DIAG_LANE_MAP(berParamsInit->baseAddr, laneNum, 0x12c)), 13,12,2);
785 if (berParamsInit->prbsPattern == SERDES_UDP || berParamsInit->loopbackType == CSL_SERDES_LOOPBACK_TX_TO_BERT)
786 {
787 CSL_FINSR(*(volatile uint32_t *)(SERDES_DIAG_LANE_MAP(berParamsInit->baseAddr, laneNum, 0x12c)),28,26,7);
788 }
789 else
790 {
791 CSL_FINSR(*(volatile uint32_t *)(SERDES_DIAG_LANE_MAP(berParamsInit->baseAddr, laneNum, 0x12c)),28,26,0);
792 }
793 }
794 }
795 else if (berParamsInit->phyType == CSL_SERDES_PHY_TYPE_USB)
796 {
797 CSL_FINSR(*(volatile uint32_t *)(SERDES_DIAG_LANE_MAP(berParamsInit->baseAddr, laneNum, 0x12c)), 13,12,3);
798 if (berParamsInit->prbsPattern == SERDES_UDP || berParamsInit->loopbackType == CSL_SERDES_LOOPBACK_TX_TO_BERT)
799 {
800 CSL_FINSR(*(volatile uint32_t *)(SERDES_DIAG_LANE_MAP(berParamsInit->baseAddr, laneNum, 0x12c)),28,26,7);
801 }
802 else
803 {
804 CSL_FINSR(*(volatile uint32_t *)(SERDES_DIAG_LANE_MAP(berParamsInit->baseAddr, laneNum, 0x12c)),28,26,0);
805 }
806 }
807 else
808 {
809 CSL_FINSR(*(volatile uint32_t *)(SERDES_DIAG_LANE_MAP(berParamsInit->baseAddr, laneNum, 0x12c)), 13,12,2);
810 CSL_FINSR(*(volatile uint32_t *)(SERDES_DIAG_LANE_MAP(berParamsInit->baseAddr, laneNum, 0x12c)),28,26,7);
811 }
812 }
813 }
814
815 /* Step 6a. Wait a minimum of 20ns let us put 50ns just in case */
816 CSL_serdesCycleDelay(50);
817
818 /* Step 6.b Assert bist_gen_en by setting bit 31 of lane 004 */
819 for(laneNum=0;laneNum<SERDES_DIAG_MAX_LANES;laneNum++)
820 {
821 if ((berParamsInit->laneMask & (1<<laneNum))!=0)
822 {
823 CSL_FINSR(*(volatile uint32_t *)(SERDES_DIAG_LANE_MAP(berParamsInit->baseAddr, laneNum, 0x4)), 31,31,1);
824 }
825 }
826
827 /* If NES loopback mode, set the NES bit
828 * This is used for EYE diagram test in NES mode */
829 if (berParamsInit->loopbackType == CSL_SERDES_LOOPBACK_NES)
830 {
831 for(laneNum=0;laneNum<SERDES_DIAG_MAX_LANES;laneNum++)
832 {
833 if ((berParamsInit->laneMask & (1<<laneNum))!=0)
834 {
835 CSL_FINSR(*(volatile uint32_t *)(SERDES_DIAG_LANE_MAP(berParamsInit->baseAddr, laneNum, 0x54)),17,17, (uint32_t)0x1);
836 }
837 }
838 }
839
840 /* For USB mode, after asserting bist_gen_en, it begins to send the LFPS burst. Poll for bist_lfps_done */
841 if (berParamsInit->phyType == CSL_SERDES_PHY_TYPE_USB)
842 {
843 for(laneNum=0;laneNum<SERDES_DIAG_MAX_LANES;laneNum++)
844 {
845 if ((berParamsInit->laneMask & (1<<laneNum))!=0)
846 {
847 stat = CSL_FEXTR(*(volatile uint32_t *)(SERDES_DIAG_LANE_MAP(berParamsInit->baseAddr, laneNum, 0x040)), 9, 9);
848 while(stat !=1)
849 {
850 stat = CSL_FEXTR(*(volatile uint32_t *)(SERDES_DIAG_LANE_MAP(berParamsInit->baseAddr, laneNum, 0x040)), 9, 9);
851 }
852 }
853 }
854
855 /* assert bist_gen_send_pream to begin sending training preamble */
856 for(laneNum=0;laneNum<SERDES_DIAG_MAX_LANES;laneNum++)
857 {
858 if ((berParamsInit->laneMask & (1<<laneNum))!=0)
859 {
860 CSL_FINSR(*(volatile uint32_t *)(SERDES_DIAG_LANE_MAP(berParamsInit->baseAddr, laneNum, 0x8)),3,3,1);
861 }
862
863 /* poll for bist_pream_started */
864 for(laneNum=0;laneNum<SERDES_DIAG_MAX_LANES;laneNum++)
865 {
866 if ((berParamsInit->laneMask & (1<<laneNum))!=0)
867 {
868 stat = CSL_FEXTR(*(volatile uint32_t *)(SERDES_DIAG_LANE_MAP(berParamsInit->baseAddr, laneNum, 0x040)), 10, 10);
869 while(stat !=1)
870 {
871 stat = CSL_FEXTR(*(volatile uint32_t *)(SERDES_DIAG_LANE_MAP(berParamsInit->baseAddr, laneNum, 0x040)), 10, 10);
872 }
873 }
874 }
875 }
876 }
877
878 /* Step 7. Wait a miniumum of 2us for the analog TX/RX paths to obtain the bit lock on to the training pattern */
879 /* While this is ocurring set bchk_en lane 00c bit 21 to 0, bchk_clr bit 22 to 1, bchk_src bits 25:24 to 3 [ONLY FOR PHYB 6:5 is 0x3; else 0x2] */
880 CSL_serdesCycleDelay(2000);
881 for(laneNum=0;laneNum<SERDES_DIAG_MAX_LANES;laneNum++)
882 {
883 if ((berParamsInit->laneMask & (1<<laneNum))!=0)
884 {
885 CSL_FINSR(*(volatile uint32_t *)(SERDES_DIAG_LANE_MAP(berParamsInit->baseAddr, laneNum, 0x0c)), 21,21,0);
886 CSL_FINSR(*(volatile uint32_t *)(SERDES_DIAG_LANE_MAP(berParamsInit->baseAddr, laneNum, 0x0c)), 22,22,1);
887 CSL_FINSR(*(volatile uint32_t *)(SERDES_DIAG_LANE_MAP(berParamsInit->baseAddr, laneNum, 0x0c)), 25,24,3);
888 }
889 }
890
891 CSL_serdesCycleDelay(5000000); /* adding the rest of the delay ~ 30us */
892
893 /* Clear bist_gen_send_pream to switch to transmitting PRBS data for USB */
894 for(laneNum=0;laneNum<SERDES_DIAG_MAX_LANES;laneNum++)
895 {
896 if ((berParamsInit->laneMask & (1<<laneNum))!=0)
897 {
898 if(berParamsInit->phyType == CSL_SERDES_PHY_TYPE_USB)
899 {
900 /* ahb_pma_ln_dr_sd_usb_mode = 0x1 */
901 CSL_FINSR(*(volatile uint32_t *)(SERDES_DIAG_LANE_MAP(berParamsInit->baseAddr, laneNum, 0x194)),11,10,1);
902 /* qd_clk_lane_clk_sel_o = 0x1 */
903 CSL_FINSR(*(volatile uint32_t *)(SERDES_DIAG_COMLANE_MAP(berParamsInit->baseAddr, 0x34)),20,20,1);
904
905 CSL_FINSR(*(volatile uint32_t *)(SERDES_DIAG_LANE_MAP(berParamsInit->baseAddr, laneNum, 0x8)),3,3,0);
906 }
907 }
908 }
909
910 return SERDES_DIAG_SETUP_OK;
911}
912
913
914/** @addtogroup SERDES_DIAG
915 @{ */
916/** ============================================================================
917 * @n@b Serdes_Diag_BERTest
918 *
919 * @b Description
920 * @n This API is used for running the BER test for a specific duration.
921 *
922 * @b Arguments
923 * @verbatim
924 berParamsInit Structure to the BER Initialization Parameters
925 *pBERval Pointer to the BER values structure
926 *
927 * <b> Return Value </b>
928 * @n None
929 *
930 * <b> Pre Condition </b>
931 * @n None
932 *
933 * <b> Post Condition </b>
934 * @n None
935 *
936 * @b Reads
937 * @n None
938 *
939 * <b> Usage Constraints: </b>
940 * @n None
941 *
942 * @b Example
943 * @verbatim
944
945 Serdes_Diag_BERTest(&berParamsInit, &pBERval);
946
947 @endverbatim
948 * ===========================================================================
949 */
950SERDES_DIAG_STAT Serdes_Diag_BERTest(const SERDES_DIAG_BER_INIT_T *berParamsInit,
951 SERDES_DIAG_BER_VAL_T *pBERval,
952 CSL_SerdesTapOffsets *pTapOffsets)
953{
954 uint32_t laneNum,temp,any_lane_valid=0, stat;
955 uint64_t llWaitTillTime;
956 uint64_t llCurTscVal;
957
958 volatile uint32_t iDone;
959
960 /* Clear Bist Valid */
961 for(laneNum=0;laneNum<SERDES_DIAG_MAX_LANES;laneNum++)
962 {
963 if ((berParamsInit->laneMask & (1<<laneNum))!=0)
964 {
965 pBERval->bistValid[laneNum] = 0;
966 }
967 }
968
969 /* Clear Bit 29 of lane 004 to 0 bist_gen_cdn */
970 for(laneNum=0;laneNum<SERDES_DIAG_MAX_LANES;laneNum++)
971 {
972 if ((berParamsInit->laneMask & (1<<laneNum))!=0)
973 {
974 if(berParamsInit->bistTxMode == SERDES_DIAG_TX_MODE_CONTINUOUS)
975 {
976 CSL_FINSR(*(volatile uint32_t *)(SERDES_DIAG_LANE_MAP(berParamsInit->baseAddr, laneNum, 0x4)),29,29,1);
977 }
978 else
979 {
980 CSL_FINSR(*(volatile uint32_t *)(SERDES_DIAG_LANE_MAP(berParamsInit->baseAddr, laneNum, 0x4)),29,29,0);
981 }
982 }
983 }
984
985 /* Set 28 [bist_tx_clock_enable] of lane 004 to 1 */
986 /* Set 31 [bist_rx_clock_enable] of lane 00c to 1 */
987 /* Set 27 [bist_chk_data_mode] of lane 00c to 1 for PRBS pattern */
988
989 for(laneNum=0;laneNum<SERDES_DIAG_MAX_LANES;laneNum++)
990 {
991 if ((berParamsInit->laneMask & (1<<laneNum))!=0)
992 {
993 CSL_FINSR(*(volatile uint32_t *)(SERDES_DIAG_LANE_MAP(berParamsInit->baseAddr, laneNum, 0x04)),28,28,berParamsInit->bistTxClkEn);
994 CSL_FINSR(*(volatile uint32_t *)(SERDES_DIAG_LANE_MAP(berParamsInit->baseAddr, laneNum, 0x0c)),31,31,berParamsInit->bistRxClkEn);
995 if (berParamsInit->prbsPattern == SERDES_UDP)
996 {
997 CSL_FINSR(*(volatile uint32_t *)(SERDES_DIAG_LANE_MAP(berParamsInit->baseAddr, laneNum, 0x0c)),27,27,0); //UDP mode
998 }
999 else
1000 {
1001 CSL_FINSR(*(volatile uint32_t *)(SERDES_DIAG_LANE_MAP(berParamsInit->baseAddr, laneNum, 0x0c)),27,27,1); //PRBS mode
1002 }
1003
1004 /* [bist_gen_mode8B] */
1005 /* [bist_rate_o] */
1006 /* [bist_gen_word] */
1007 if (berParamsInit->phyType == CSL_SERDES_PHY_TYPE_PCIe)
1008 {
1009
1010 if (berParamsInit->prbsPattern == SERDES_UDP)
1011 {
1012 CSL_FINSR(*(volatile uint32_t *)(SERDES_DIAG_LANE_MAP(berParamsInit->baseAddr, laneNum, 0x04)),26,26,0); //UDP mode
1013 }
1014 else
1015 {
1016 CSL_FINSR(*(volatile uint32_t *)(SERDES_DIAG_LANE_MAP(berParamsInit->baseAddr, laneNum, 0x04)),26,26,1); //PRBS mode
1017 }
1018
1019 /* Set Bus Width to 8 bit interface for PCIe GEN 1 */
1020 if(berParamsInit->pcieGenType == SERDES_DIAG_PCIE_GEN1)
1021 {
1022 CSL_FINSR(*(volatile uint32_t *)(SERDES_DIAG_LANE_MAP(berParamsInit->baseAddr, laneNum, 0x04)),25,24,0);
1023 CSL_FINSR(*(volatile uint32_t *)(SERDES_DIAG_LANE_MAP(berParamsInit->baseAddr, laneNum, 0x04)),30,30,0);
1024 }
1025 /* Set BUS Width to 16 bit interface for PCIe GEN 2 */
1026 else if(berParamsInit->pcieGenType == SERDES_DIAG_PCIE_GEN2)
1027 {
1028 CSL_FINSR(*(volatile uint32_t *)(SERDES_DIAG_LANE_MAP(berParamsInit->baseAddr, laneNum, 0x04)),25,24,1);
1029 CSL_FINSR(*(volatile uint32_t *)(SERDES_DIAG_LANE_MAP(berParamsInit->baseAddr, laneNum, 0x04)),30,30,1);
1030 }
1031 /* Set BUS Width to 32 bit interface for PCIe GEN 3 */
1032 else if(berParamsInit->pcieGenType == SERDES_DIAG_PCIE_GEN3)
1033 {
1034 CSL_FINSR(*(volatile uint32_t *)(SERDES_DIAG_LANE_MAP(berParamsInit->baseAddr, laneNum, 0x04)),25,24,2);
1035 CSL_FINSR(*(volatile uint32_t *)(SERDES_DIAG_LANE_MAP(berParamsInit->baseAddr, laneNum, 0x04)),30,30,1);
1036 }
1037 }
1038
1039 /* Set BUS Width to 10 bit interface for SGMII */
1040 else if(berParamsInit->phyType == CSL_SERDES_PHY_TYPE_SGMII)
1041 {
1042 CSL_FINSR(*(volatile uint32_t *)(SERDES_DIAG_LANE_MAP(berParamsInit->baseAddr, laneNum, 0x04)),26,26,0);
1043 CSL_FINSR(*(volatile uint32_t *)(SERDES_DIAG_LANE_MAP(berParamsInit->baseAddr, laneNum, 0x04)),30,30,0);
1044 }
1045
1046 /* Set BUS Width to 20 bit interface for USB */
1047 else if(berParamsInit->phyType == CSL_SERDES_PHY_TYPE_USB)
1048 {
1049 if (berParamsInit->prbsPattern == SERDES_UDP)
1050 {
1051 CSL_FINSR(*(volatile uint32_t *)(SERDES_DIAG_LANE_MAP(berParamsInit->baseAddr, laneNum, 0x04)),26,26,0); //UDP mode
1052 }
1053 else
1054 {
1055 CSL_FINSR(*(volatile uint32_t *)(SERDES_DIAG_LANE_MAP(berParamsInit->baseAddr, laneNum, 0x04)),26,26,1); //PRBS mode
1056 }
1057
1058 CSL_FINSR(*(volatile uint32_t *)(SERDES_DIAG_LANE_MAP(berParamsInit->baseAddr, laneNum, 0x04)),25,24,0);
1059 CSL_FINSR(*(volatile uint32_t *)(SERDES_DIAG_LANE_MAP(berParamsInit->baseAddr, laneNum, 0x04)),30,30,1);
1060 }
1061 }
1062 }
1063
1064 /* Clear Bit 31 of lane 004 to 0 bist_gen_en_o */
1065 for(laneNum=0;laneNum<SERDES_DIAG_MAX_LANES;laneNum++)
1066 {
1067 if ((berParamsInit->laneMask & (1<<laneNum))!=0)
1068 {
1069 if(!(berParamsInit->bistTxMode == SERDES_DIAG_TX_MODE_CONTINUOUS))
1070 {
1071 CSL_FINSR(*(volatile uint32_t *)(SERDES_DIAG_LANE_MAP(berParamsInit->baseAddr, laneNum, 0x4)),31,31,0);
1072 }
1073 }
1074 }
1075
1076 /* SET BIT 3 [bist_gen_send_pream]of lane 008 to 0 */
1077 for(laneNum=0;laneNum<SERDES_DIAG_MAX_LANES;laneNum++)
1078 {
1079 if ((berParamsInit->laneMask & (1<<laneNum))!=0)
1080 {
1081 if(berParamsInit->phyType == CSL_SERDES_PHY_TYPE_PCIe)
1082 {
1083 CSL_FINSR(*(volatile uint32_t *)(SERDES_DIAG_LANE_MAP(berParamsInit->baseAddr, laneNum, 0x8)),3,3,1);
1084 }
1085 else
1086 {
1087 CSL_FINSR(*(volatile uint32_t *)(SERDES_DIAG_LANE_MAP(berParamsInit->baseAddr, laneNum, 0x8)),3,3,0);
1088 }
1089 }
1090 }
1091
1092 /* Set Bit 29:28 to PRBS pattern on LANE 00c - Field 0-PRBS7, 1-PRBS15, 2-PRBS23, 3-PRBS31 */
1093 /* bist_chk_lfsr_length */
1094 for(laneNum=0;laneNum<SERDES_DIAG_MAX_LANES;laneNum++)
1095 {
1096 if ((berParamsInit->laneMask & (1<<laneNum))!=0)
1097 {
1098 if (!(berParamsInit->prbsPattern == SERDES_UDP))
1099 {
1100 CSL_FINSR(*(volatile uint32_t *)(SERDES_DIAG_LANE_MAP(berParamsInit->baseAddr, laneNum, 0x0c)),29,28,berParamsInit->prbsPattern);
1101 }
1102 }
1103 }
1104
1105 /* SET BIT 9 and bit 8 of comlane 000 to 1 */
1106 /* 1 bist_gen_inv_prbs */
1107 /* 1 bist_chk_inv_prbs */
1108 CSL_FINSR(*(volatile uint32_t *)(SERDES_DIAG_COMLANE_MAP(berParamsInit->baseAddr, 0x0)),9,9,1);
1109 CSL_FINSR(*(volatile uint32_t *)(SERDES_DIAG_COMLANE_MAP(berParamsInit->baseAddr, 0x0)),8,8,1);
1110
1111 /* Set LANE 10 bits 9:0 to 0x283 */
1112 /* bist_chk_pream0 */
1113 /* Set LANE 10 bits 25:16 to 0x17C */
1114 /* bist_chk_pream1 */
1115 for(laneNum=0;laneNum<SERDES_DIAG_MAX_LANES;laneNum++)
1116 {
1117 if ((berParamsInit->laneMask & (1<<laneNum))!=0)
1118 {
1119 if(berParamsInit->phyType == CSL_SERDES_PHY_TYPE_USB || berParamsInit->phyType == CSL_SERDES_PHY_TYPE_PCIe)
1120 {
1121 CSL_FINSR(*(volatile uint32_t *)(SERDES_DIAG_LANE_MAP(berParamsInit->baseAddr, laneNum, 0x10)),9,0,0x1bc);
1122 CSL_FINSR(*(volatile uint32_t *)(SERDES_DIAG_LANE_MAP(berParamsInit->baseAddr, laneNum, 0x10)),25,16,0x1bc);
1123 }
1124 else
1125 {
1126 CSL_FINSR(*(volatile uint32_t *)(SERDES_DIAG_LANE_MAP(berParamsInit->baseAddr, laneNum, 0x10)),9,0,0x283);
1127 CSL_FINSR(*(volatile uint32_t *)(SERDES_DIAG_LANE_MAP(berParamsInit->baseAddr, laneNum, 0x10)),25,16,0x17c);
1128 }
1129 }
1130 }
1131
1132 /*bist_chk_udp Lane 0x14 bits 31:0 and lane 0x18 bits 7:0 to 0x0 */
1133 /*bist_gen_en_low Lane 0x08 bits 23:8 to 0x0 */
1134 /*bist_gen_en_high Lane 0x08 and lane 0x0c bits 31:24, bits 7:0 to 0x0 */
1135 /*bist_chk_insert_word Lane 0x18 and lane 0x1c bits 31:8, bits 15:0 to 0x0 */
1136 /*bist_chk_insert_length Lane 0x10 bits 12:10 to 0x0 */
1137 /*bist_gen_insert_count Lane 0x08 bits 6:4 to 0x0 */
1138 /*bist_gen_insert_delay Lane 0xc bits 19:16 to 0x0 */
1139 for(laneNum=0;laneNum<SERDES_DIAG_MAX_LANES;laneNum++)
1140 {
1141 if ((berParamsInit->laneMask & (1<<laneNum))!=0)
1142 {
1143 if (berParamsInit->prbsPattern == SERDES_UDP)
1144 {
1145 *(volatile uint32_t *)(SERDES_DIAG_LANE_MAP(berParamsInit->baseAddr, laneNum, 0x14)) = (uint32_t)0xAAAAAAAA;
1146 CSL_FINSR(*(volatile uint32_t *)(SERDES_DIAG_LANE_MAP(berParamsInit->baseAddr, laneNum, 0x18)), 7,0,0xAA);
1147 }
1148 else
1149 {
1150 *(volatile uint32_t *)(SERDES_DIAG_LANE_MAP(berParamsInit->baseAddr, laneNum, 0x14)) = (uint32_t)0x0;
1151 CSL_FINSR(*(volatile uint32_t *)(SERDES_DIAG_LANE_MAP(berParamsInit->baseAddr, laneNum, 0x18)), 7,0,0x0);
1152 }
1153
1154 CSL_FINSR(*(volatile uint32_t *)(SERDES_DIAG_LANE_MAP(berParamsInit->baseAddr, laneNum, 0x08)), 23,8,0x0);
1155
1156 CSL_FINSR(*(volatile uint32_t *)(SERDES_DIAG_LANE_MAP(berParamsInit->baseAddr, laneNum, 0x08)), 31,24,0x0);
1157 CSL_FINSR(*(volatile uint32_t *)(SERDES_DIAG_LANE_MAP(berParamsInit->baseAddr, laneNum, 0x0c)), 7,0,0x0);
1158
1159 CSL_FINSR(*(volatile uint32_t *)(SERDES_DIAG_LANE_MAP(berParamsInit->baseAddr, laneNum, 0x18)), 31,8,0x0);
1160 CSL_FINSR(*(volatile uint32_t *)(SERDES_DIAG_LANE_MAP(berParamsInit->baseAddr, laneNum, 0x1c)), 15,0,0x0);
1161
1162 CSL_FINSR(*(volatile uint32_t *)(SERDES_DIAG_LANE_MAP(berParamsInit->baseAddr, laneNum, 0x10)), 12,10,0x0);
1163
1164 CSL_FINSR(*(volatile uint32_t *)(SERDES_DIAG_LANE_MAP(berParamsInit->baseAddr, laneNum, 0x8)), 6,4,0x0);
1165
1166 CSL_FINSR(*(volatile uint32_t *)(SERDES_DIAG_LANE_MAP(berParamsInit->baseAddr, laneNum, 0xc)), 19,8,0x0);
1167 }
1168 }
1169
1170
1171 /*Force att and boost if flag is set */
1172 if (berParamsInit->forceAttBoost)
1173 {
1174 CSL_FINSR(*(volatile uint32_t *)(SERDES_DIAG_COMRXEQ_MAP(berParamsInit->baseAddr, 0xC)), 23,16,0x4C); /* calibration gen3 default FF*/
1175 CSL_FINSR(*(volatile uint32_t *)(SERDES_DIAG_COMRXEQ_MAP(berParamsInit->baseAddr, 0x34)), 18,16,berParamsInit->forceAttVal); /* att Gen 3 default 2*/ //0
1176 CSL_FINSR(*(volatile uint32_t *)(SERDES_DIAG_COMRXEQ_MAP(berParamsInit->baseAddr, 0x4c)), 3,0,berParamsInit->forceBoostVal); /* Gen 3 boost start default C*/
1177 CSL_FINSR(*(volatile uint32_t *)(SERDES_DIAG_COMRXEQ_MAP(berParamsInit->baseAddr, 0x8)), 7,0,0x4C); /* csr_rxeq_init_run_rate3_o*/
1178 }
1179
1180 /* Wait a minimum of 20ns let us put 50ns just in case */
1181 CSL_serdesCycleDelay(5000000);
1182
1183 /* Step 4. Deassert bist_gen_cdn by setting 1 on bit 29 of lane 004 */
1184 for(laneNum=0;laneNum<SERDES_DIAG_MAX_LANES;laneNum++)
1185 {
1186 if ((berParamsInit->laneMask & (1<<laneNum))!=0)
1187 {
1188 CSL_FINSR(*(volatile uint32_t *)(SERDES_DIAG_LANE_MAP(berParamsInit->baseAddr, laneNum, 0x4)), 29,29,1);
1189 }
1190 }
1191
1192 /* Step 5. Set Lane 0x12c */
1193 /* dmux_txa_sel Lane 0x12c [13:12] 0x3 */
1194 /* dmux_txb_sel Lane 0x12c [28:26] 0x0 */
1195 for(laneNum=0;laneNum<SERDES_DIAG_MAX_LANES;laneNum++)
1196 {
1197 if ((berParamsInit->laneMask & (1<<laneNum))!=0)
1198 {
1199 if(berParamsInit->phyType == CSL_SERDES_PHY_TYPE_PCIe)
1200 {
1201 if(berParamsInit->pcieGenType == SERDES_DIAG_PCIE_GEN1 || berParamsInit->pcieGenType == SERDES_DIAG_PCIE_GEN2)
1202 {
1203 CSL_FINSR(*(volatile uint32_t *)(SERDES_DIAG_LANE_MAP(berParamsInit->baseAddr, laneNum, 0x12c)), 13,12,3);
1204 if (berParamsInit->prbsPattern == SERDES_UDP)
1205 {
1206 CSL_FINSR(*(volatile uint32_t *)(SERDES_DIAG_LANE_MAP(berParamsInit->baseAddr, laneNum, 0x12c)),28,26,7);
1207 }
1208 else
1209 {
1210 CSL_FINSR(*(volatile uint32_t *)(SERDES_DIAG_LANE_MAP(berParamsInit->baseAddr, laneNum, 0x12c)),28,26,0);
1211 }
1212 }
1213 else if(berParamsInit->pcieGenType == SERDES_DIAG_PCIE_GEN3)
1214 {
1215 CSL_FINSR(*(volatile uint32_t *)(SERDES_DIAG_LANE_MAP(berParamsInit->baseAddr, laneNum, 0x12c)), 13,12,2);
1216 if (berParamsInit->prbsPattern == SERDES_UDP)
1217 {
1218 CSL_FINSR(*(volatile uint32_t *)(SERDES_DIAG_LANE_MAP(berParamsInit->baseAddr, laneNum, 0x12c)),28,26,7);
1219 }
1220 else
1221 {
1222 CSL_FINSR(*(volatile uint32_t *)(SERDES_DIAG_LANE_MAP(berParamsInit->baseAddr, laneNum, 0x12c)),28,26,0);
1223 }
1224 }
1225 }
1226 else if (berParamsInit->phyType == CSL_SERDES_PHY_TYPE_USB)
1227 {
1228 CSL_FINSR(*(volatile uint32_t *)(SERDES_DIAG_LANE_MAP(berParamsInit->baseAddr, laneNum, 0x12c)), 13,12,3);
1229
1230 if (berParamsInit->prbsPattern == SERDES_UDP)
1231 {
1232 CSL_FINSR(*(volatile uint32_t *)(SERDES_DIAG_LANE_MAP(berParamsInit->baseAddr, laneNum, 0x12c)),28,26,7);
1233 }
1234 else
1235 {
1236 CSL_FINSR(*(volatile uint32_t *)(SERDES_DIAG_LANE_MAP(berParamsInit->baseAddr, laneNum, 0x12c)),28,26,0);
1237 }
1238 }
1239 else
1240 {
1241 CSL_FINSR(*(volatile uint32_t *)(SERDES_DIAG_LANE_MAP(berParamsInit->baseAddr, laneNum, 0x12c)), 13,12,2);
1242 CSL_FINSR(*(volatile uint32_t *)(SERDES_DIAG_LANE_MAP(berParamsInit->baseAddr, laneNum, 0x12c)),28,26,7);
1243 }
1244 }
1245 }
1246
1247 /* Step 6a. Wait a minimum of 20ns let us put 50ns just in case */
1248 CSL_serdesCycleDelay(5000000);
1249
1250 /* Step 6.b Assert bist_gen_en by setting bit 31 of lane 004 */
1251 for(laneNum=0;laneNum<SERDES_DIAG_MAX_LANES;laneNum++)
1252 {
1253 if ((berParamsInit->laneMask & (1<<laneNum))!=0)
1254 {
1255 CSL_FINSR(*(volatile uint32_t *)(SERDES_DIAG_LANE_MAP(berParamsInit->baseAddr, laneNum, 0x4)), 31,31,1);
1256 }
1257 }
1258
1259 /* If NES loopback mode, set the NES bit
1260 * This is used for EYE diagram test in NES mode */
1261 if (berParamsInit->loopbackType == CSL_SERDES_LOOPBACK_NES)
1262 {
1263 for(laneNum=0;laneNum<SERDES_DIAG_MAX_LANES;laneNum++)
1264 {
1265 if ((berParamsInit->laneMask & (1<<laneNum))!=0)
1266 {
1267 CSL_FINSR(*(volatile uint32_t *)(SERDES_DIAG_LANE_MAP(berParamsInit->baseAddr, laneNum, 0x54)),17,17, (uint32_t)0x1);
1268 }
1269 }
1270 }
1271
1272 /* For USB mode, after asserting bist_gen_en, it begins to send the LFPS burst. Poll for bist_lfps_done */
1273 if (berParamsInit->phyType == CSL_SERDES_PHY_TYPE_USB)
1274 {
1275 for(laneNum=0;laneNum<SERDES_DIAG_MAX_LANES;laneNum++)
1276 {
1277 if ((berParamsInit->laneMask & (1<<laneNum))!=0)
1278 {
1279 stat = CSL_FEXTR(*(volatile uint32_t *)(SERDES_DIAG_LANE_MAP(berParamsInit->baseAddr, laneNum, 0x040)), 9, 9);
1280 while(stat !=1)
1281 {
1282 stat = CSL_FEXTR(*(volatile uint32_t *)(SERDES_DIAG_LANE_MAP(berParamsInit->baseAddr, laneNum, 0x040)), 9, 9);
1283 }
1284 }
1285 }
1286
1287 /* assert bist_gen_send_pream to begin sending training preamble */
1288 for(laneNum=0;laneNum<SERDES_DIAG_MAX_LANES;laneNum++)
1289 {
1290 if ((berParamsInit->laneMask & (1<<laneNum))!=0)
1291 {
1292 CSL_FINSR(*(volatile uint32_t *)(SERDES_DIAG_LANE_MAP(berParamsInit->baseAddr, laneNum, 0x8)),3,3,1);
1293 }
1294 }
1295
1296 /* poll for bist_pream_started */
1297 for(laneNum=0;laneNum<SERDES_DIAG_MAX_LANES;laneNum++)
1298 {
1299 if ((berParamsInit->laneMask & (1<<laneNum))!=0)
1300 {
1301 stat = CSL_FEXTR(*(volatile uint32_t *)(SERDES_DIAG_LANE_MAP(berParamsInit->baseAddr, laneNum, 0x040)), 10, 10);
1302 while(stat !=1)
1303 {
1304 stat = CSL_FEXTR(*(volatile uint32_t *)(SERDES_DIAG_LANE_MAP(berParamsInit->baseAddr, laneNum, 0x040)), 10, 10);
1305 }
1306 }
1307 }
1308 }
1309
1310 /* Step 7. Wait a miniumum of 2us for the analog TX/RX paths to obtain the bit lock on to the training pattern */
1311 /* While this is ocurring set bchk_en lane 00c bit 21 to 0, bchk_clr bit 22 to 1, bchk_src bits 25:24 to 3 [ONLY FOR PHYB 6:5 is 0x3; else 0x2] */
1312 CSL_serdesCycleDelay(500000);
1313 for(laneNum=0;laneNum<SERDES_DIAG_MAX_LANES;laneNum++)
1314 {
1315 if ((berParamsInit->laneMask & (1<<laneNum))!=0)
1316 {
1317 CSL_FINSR(*(volatile uint32_t *)(SERDES_DIAG_LANE_MAP(berParamsInit->baseAddr, laneNum, 0x0c)), 21,21,0);
1318 CSL_FINSR(*(volatile uint32_t *)(SERDES_DIAG_LANE_MAP(berParamsInit->baseAddr, laneNum, 0x0c)), 22,22,1);
1319 CSL_FINSR(*(volatile uint32_t *)(SERDES_DIAG_LANE_MAP(berParamsInit->baseAddr, laneNum, 0x0c)), 25,24,3);
1320 }
1321 }
1322
1323 llWaitTillTime = berParamsInit->timeoutLoops;
1324// llWaitTillTime = CSL_tscRead() + berParamsInit->timeoutLoops;
1325
1326 CSL_serdesCycleDelay(500000); /* adding the rest of the delay ~ 30us */
1327
1328 /*Step 9. Assert bchk_en by setting bit 21 to 1 of LANE 00c */
1329 for(laneNum=0;laneNum<SERDES_DIAG_MAX_LANES;laneNum++)
1330 {
1331 if ((berParamsInit->laneMask & (1<<laneNum))!=0)
1332 {
1333 CSL_FINSR(*(volatile uint32_t *)(SERDES_DIAG_LANE_MAP(berParamsInit->baseAddr, laneNum, 0x0c)), 21,21,1);
1334 }
1335 }
1336
1337 /* Step 9A Toggle SIGDET Overlay so the we reset the receiver to the new BIST pattern */
1338 if(!(berParamsInit->loopbackType == CSL_SERDES_LOOPBACK_NES))
1339 {
1340 for(laneNum=0;laneNum<SERDES_DIAG_MAX_LANES;laneNum++)
1341 {
1342 if ((berParamsInit->laneMask & (1<<laneNum))!=0)
1343 {
1344 CSL_serdesResetReceiver(berParamsInit->baseAddr, laneNum);
1345 }
1346 }
1347 }
1348
1349
1350 /* Read ln_stat_o RX Valid signal */
1351 for(laneNum=0;laneNum<SERDES_DIAG_MAX_LANES;laneNum++)
1352 {
1353 if ((berParamsInit->laneMask & (1<<laneNum))!=0)
1354 {
1355 if(berParamsInit->phyType == CSL_SERDES_PHY_TYPE_PCIe)
1356 {
1357 stat = (CSL_serdesReadSelectedTbus(berParamsInit->baseAddr, laneNum+1, 0x7) & 0x80)>>7;
1358
1359 while ((stat != 1))// && (llWaitTillTime != 0))
1360 {
1361 stat = (CSL_serdesReadSelectedTbus(berParamsInit->baseAddr, laneNum+1, 0x7) & 0x80)>>7;
1362// llWaitTillTime--;
1363//
1364// if(llWaitTillTime==0)
1365// {
1366// break;
1367// } /*current time exceeded timeoutLoops offset */
1368 }
1369 }
1370 else if (berParamsInit->phyType == CSL_SERDES_PHY_TYPE_SGMII)
1371 {
1372 stat = (CSL_serdesReadSelectedTbus(berParamsInit->baseAddr, laneNum+1, 0x7) & 0x10)>>4;
1373
1374 while ((stat != 1))// && (llWaitTillTime != 0))
1375 {
1376 stat = (CSL_serdesReadSelectedTbus(berParamsInit->baseAddr, laneNum+1, 0x7) & 0x10)>>4;
1377// llWaitTillTime--;
1378//
1379// if(llWaitTillTime==0)
1380// {
1381// break;
1382// } /*current time exceeded timeoutLoops offset */
1383 }
1384 }
1385 }
1386 }
1387
1388 /* Clear bist_gen_send_pream to switch to transmitting PRBS data for USB */
1389 for(laneNum=0;laneNum<SERDES_DIAG_MAX_LANES;laneNum++)
1390 {
1391 if ((berParamsInit->laneMask & (1<<laneNum))!=0)
1392 {
1393 if(berParamsInit->phyType == CSL_SERDES_PHY_TYPE_USB)
1394 {
1395 /* ahb_pma_ln_dr_sd_usb_mode = 0x1 */
1396 CSL_FINSR(*(volatile uint32_t *)(SERDES_DIAG_LANE_MAP(berParamsInit->baseAddr, laneNum, 0x194)),11,10,1);
1397 /* qd_clk_lane_clk_sel_o = 0x1 */
1398 CSL_FINSR(*(volatile uint32_t *)(SERDES_DIAG_COMLANE_MAP(berParamsInit->baseAddr, 0x34)),20,20,1);
1399 /* pcs_rate_o = 0x1 */
1400 // CSL_FINSR(*(volatile uint32_t *)(SERDES_DIAG_CMU_MAP(berParamsInit->baseAddr, 0x7c)),26,25,0); //CODE_CHANGE Do not enable
1401
1402 CSL_serdesCycleDelay(50000);
1403 }
1404
1405 if(berParamsInit->phyType == CSL_SERDES_PHY_TYPE_PCIe || berParamsInit->phyType == CSL_SERDES_PHY_TYPE_USB)
1406 {
1407 CSL_FINSR(*(volatile uint32_t *)(SERDES_DIAG_LANE_MAP(berParamsInit->baseAddr, laneNum, 0x8)),3,3,0);
1408 }
1409 }
1410 }
1411
1412 /* Step 9B. Force an RXEQ re-calibration with PRBS data to ensure that sufficient
1413 * patterns are observed for the EBB
1414 */
1415 CSL_FINSR(*(volatile uint32_t *)(SERDES_DIAG_COMRXEQ_MAP(berParamsInit->baseAddr, 0x0)),6,6,1);
1416 CSL_serdesCycleDelay(300000);
1417 CSL_FINSR(*(volatile uint32_t *)(SERDES_DIAG_COMRXEQ_MAP(berParamsInit->baseAddr, 0x0)),6,6,0);
1418
1419
1420 CSL_serdesTbusLaneDump(berParamsInit->baseAddr, &tbusLaneDump);
1421 CSL_serdesTbusCMUDump(berParamsInit->baseAddr, &tbusCMUDump);
1422
1423 /*Step 10. The PHY will indicate that it has succesfully detected PRBS
1424 when bist_rx_synch is asserted (read bit 1 of tbus data at address 0xAD) */
1425 /*Wait 20mS max. Anything greater than 10uS seems to hi ber anyway. */
1426 llWaitTillTime = berParamsInit->timeoutLoops;//CSL_tscRead() + berParamsInit->timeoutLoops;
1427 llCurTscVal = llWaitTillTime;
1428 uint8_t temp_counter = 0;
1429
1430 do
1431 {
1432 for(laneNum=0;laneNum<SERDES_DIAG_MAX_LANES;laneNum++)
1433 {
1434 if ((berParamsInit->laneMask & (1<<laneNum))!=0)
1435 {
1436 pBERval->bistValid[laneNum]= (CSL_serdesReadSelectedTbus(berParamsInit->baseAddr, laneNum+1, 0xAD) & 0x002) >> 1;
1437
1438// if (((*(volatile uint32_t *)(berParamsInit->baseAddr + 0x1fc0 + 0x34))&(1<<laneNum)) == 0)
1439// {
1440// pBERval->bistValid[laneNum] = 0;
1441// }
1442 }
1443 }
1444
1445 for(laneNum=0,temp=1;laneNum<SERDES_DIAG_MAX_LANES;laneNum++)
1446 {
1447 if ((berParamsInit->laneMask & (1<<laneNum))!=0)
1448 {
1449 temp &= pBERval->bistValid[laneNum];
1450 }
1451 }
1452
1453 llCurTscVal--;// = CSL_tscRead();
1454 if(temp != 1)
1455 {
1456 if(temp_counter >10)
1457 {
1458 temp = 1;
1459 }
1460 CSL_serdesCycleDelay(300000);
1461 temp_counter = temp_counter + 1;
1462 }
1463
1464 } while ((!temp) && llCurTscVal);//(llWaitTillTime>llCurTscVal));
1465
1466 /* If bist_rx_synch = 1 for any of the lanes, then any_lane_valid is set
1467 and we will go through the BER sweep for all lane*/
1468 for(laneNum=0;laneNum<SERDES_DIAG_MAX_LANES;laneNum++)
1469 {
1470 if ((berParamsInit->laneMask & (1<<laneNum))!=0)
1471 {
1472 any_lane_valid |= pBERval->bistValid[laneNum];
1473 }
1474 }
1475
1476 /*Step 8. Deassert bchk_clr by clearing bit 22 to 0 of LANE 00c */
1477 for(laneNum=0;laneNum<SERDES_DIAG_MAX_LANES;laneNum++)
1478 {
1479 if ((berParamsInit->laneMask & (1<<laneNum))!=0)
1480 {
1481 CSL_FINSR(*(volatile uint32_t *)(SERDES_DIAG_LANE_MAP(berParamsInit->baseAddr, laneNum, 0x0c)), 22,22,0);
1482 }
1483 }
1484
1485 /*11. Waiting for testtime to measure BER.
1486 Don't wait for invalid lanes or if all lanes hit max errors */
1487// pBERval->runTime[0] = CSL_tscRead();
1488 if (any_lane_valid)
1489 {
1490 CSL_serdesCycleDelay(berParamsInit->bertesttime);
1491 }
1492
1493// llCurTscVal = CSL_tscRead();
1494// /*Capture run time for test */
1495// pBERval->runTime[0] = llCurTscVal - pBERval->runTime[0];
1496
1497// CSL_SerdesTbusDump pTbusDump;
1498// CSL_serdesTbusDump(berParamsInit->baseAddr, &pTbusDump);
1499
1500 /*Get the DLPF values */
1501 for(laneNum=0;laneNum<SERDES_DIAG_MAX_LANES;laneNum++)
1502 {
1503 if ((berParamsInit->laneMask & (1<<laneNum))!=0)
1504 {
1505 pBERval->pma[laneNum] = (CSL_serdesReadSelectedTbus(berParamsInit->baseAddr, laneNum+1, 0x29) & 0x03ff) >> 0;
1506 pBERval->cdr[laneNum] = (CSL_serdesReadSelectedTbus(berParamsInit->baseAddr, laneNum+1, 0x28) & 0x01fe) >> 1;
1507 }
1508 }
1509
1510 /*14. Veriy that pBERval->val is 0; tbus address is 0C, bit locations are */
1511 for(laneNum=0;laneNum<SERDES_DIAG_MAX_LANES;laneNum++)
1512 {
1513 if ((berParamsInit->laneMask & (1<<laneNum))!=0)
1514 {
1515 if(pBERval->bistValid[laneNum])
1516 {
1517 pBERval->val[laneNum] = (CSL_serdesReadSelectedTbus(berParamsInit->baseAddr, laneNum+1, 0xaf) & 0x00f) << 12;
1518 pBERval->val[laneNum] |= (CSL_serdesReadSelectedTbus(berParamsInit->baseAddr, laneNum+1, 0xae) & 0xfff);
1519 }
1520 else
1521 {
1522 pBERval->val[laneNum] = 0x1ffff;
1523 }
1524
1525 pBERval->att[laneNum] = (CSL_serdesReadSelectedTbus(berParamsInit->baseAddr, laneNum+1, 0x40) & 0x070) >> 4;
1526 pBERval->boost[laneNum] = (CSL_serdesReadSelectedTbus(berParamsInit->baseAddr, laneNum+1, 0x44) & 0x078) >> 3;
1527 pBERval->dfe1[laneNum] = (CSL_serdesReadSelectedTbus(berParamsInit->baseAddr, laneNum+1, 0x4D) & 0x00ff) >> 0; //dfe slicer tap value
1528 pBERval->dfe2[laneNum] = (CSL_serdesReadSelectedTbus(berParamsInit->baseAddr, laneNum+1, 0x4C) & 0x00ff) >> 0; //tap value scaled
1529 pBERval->dfe3[laneNum] = (CSL_serdesReadSelectedTbus(berParamsInit->baseAddr, laneNum+1, 0x4A) & 0x007) >> 0; //dfe computation state
1530 pBERval->dfe4[laneNum] = (CSL_serdesReadSelectedTbus(berParamsInit->baseAddr, laneNum+1, 0x4A) & 0x03F8) >> 3; //dfe computation dlev
1531 pBERval->dfe5[laneNum] = (CSL_serdesReadSelectedTbus(berParamsInit->baseAddr, laneNum+1, 0x40) & 0x180) >> 7; //gain
1532
1533 pBERval->cdfe1[laneNum] = CSL_FEXTR(*(volatile uint32_t *)(SERDES_DIAG_LANE_MAP(berParamsInit->baseAddr, laneNum, 0x154)), 7, 0); //csr_dfe_dlev_a_i
1534 pBERval->cdfe2[laneNum] = CSL_FEXTR(*(volatile uint32_t *)(SERDES_DIAG_LANE_MAP(berParamsInit->baseAddr, laneNum, 0x154)), 15, 8); //csr_dfe_dlev_b_i
1535 pBERval->cdfe3[laneNum] = CSL_FEXTR(*(volatile uint32_t *)(SERDES_DIAG_LANE_MAP(berParamsInit->baseAddr, laneNum, 0x170)), 7, 0); //csr_dfe_tap_val_rate3_i
1536 }
1537 }
1538
1539 /* To verify bist works, insert bist errors intentionally */
1540 for(laneNum=0;laneNum<SERDES_DIAG_MAX_LANES;laneNum++)
1541 {
1542 if ((berParamsInit->laneMask & (1<<laneNum))!=0)
1543 {
1544 CSL_FINSR(*(volatile uint32_t *)(SERDES_DIAG_LANE_MAP(berParamsInit->baseAddr, laneNum, 0x4)),27,27,1);
1545 }
1546 }
1547
1548 CSL_serdesCycleDelay(50);
1549 temp = 1, temp_counter = 0;
1550
1551 /* Within 50ns the PHY will indicate a successful exit from the BIST by deasserting bist_rx_synch_o.
1552 * At this point, bist_rx_errors_o is guaranteed to be static */
1553 for(laneNum=0;laneNum<SERDES_DIAG_MAX_LANES;laneNum++)
1554 {
1555 if ((berParamsInit->laneMask & (1<<laneNum))!=0)
1556 {
1557 pBERval->bistValidTemp[laneNum]= (CSL_serdesReadSelectedTbus(berParamsInit->baseAddr, laneNum+1, 0xAD) & 0x002) >> 1;
1558 while(pBERval->bistValidTemp[laneNum] !=1 && (!temp))
1559 {
1560 pBERval->bistValidTemp[laneNum]= (CSL_serdesReadSelectedTbus(berParamsInit->baseAddr, laneNum+1, 0xAD) & 0x002) >> 1;
1561
1562 if(temp != 1)
1563 {
1564 if(temp_counter >10)
1565 {
1566 temp = 1;
1567 }
1568 CSL_serdesCycleDelay(300000);
1569 temp_counter = temp_counter + 1;
1570 }
1571 }
1572 }
1573 }
1574
1575 /* Verify bist_rx_errors_0 is non-zero(check after BISt error insertion).
1576 * This verifies that no bit errors were measured during the testing sequence */
1577 for(laneNum=0;laneNum<SERDES_DIAG_MAX_LANES;laneNum++)
1578 {
1579 if ((berParamsInit->laneMask & (1<<laneNum))!=0)
1580 {
1581 pBERval->valTemp[laneNum] = (CSL_serdesReadSelectedTbus(berParamsInit->baseAddr, laneNum+1, 0xae) & 0xfff);
1582 pBERval->valTemp[laneNum] |= (CSL_serdesReadSelectedTbus(berParamsInit->baseAddr, laneNum+1, 0xaf) & 0x00f) << 12;
1583 }
1584 }
1585
1586
1587 /*15. To return to normal mode set dmux_txa_sel and dmux_txb_sel to 0
1588 by setting bits 13:12 of lane 12c and 28:26 of lane 12c respectively */
1589 /*12. Deassert bchk_en by clearing bit 21 of LANE 00c */
1590 for(laneNum=0;laneNum<SERDES_DIAG_MAX_LANES;laneNum++)
1591 {
1592 if ((berParamsInit->laneMask & (1<<laneNum))!=0)
1593 {
1594 CSL_FINSR(*(volatile uint32_t *)(SERDES_DIAG_LANE_MAP(berParamsInit->baseAddr, laneNum, 0x0c)), 21,21,0);
1595 }
1596 }
1597
1598 /* Clear bist_gen_en by clearing bit 31 of lane 004 */
1599 for(laneNum=0;laneNum<SERDES_DIAG_MAX_LANES;laneNum++)
1600 {
1601 if ((berParamsInit->laneMask & (1<<laneNum))!=0)
1602 {
1603 if(!(berParamsInit->bistTxMode == SERDES_DIAG_TX_MODE_CONTINUOUS))
1604 {
1605 CSL_FINSR(*(volatile uint32_t *)(SERDES_DIAG_LANE_MAP(berParamsInit->baseAddr, laneNum, 0x4)), 31,31,0);
1606 }
1607 }
1608 }
1609
1610 for(laneNum=0;laneNum<SERDES_DIAG_MAX_LANES;laneNum++)
1611 {
1612 if ((berParamsInit->laneMask & (1<<laneNum))!=0)
1613 {
1614 CSL_FINSR(*(volatile uint32_t *)(SERDES_DIAG_LANE_MAP(berParamsInit->baseAddr, laneNum, 0x4)),27,27,0); //turn off err gen
1615 }
1616 }
1617
1618 for(laneNum=0;laneNum<SERDES_DIAG_MAX_LANES;laneNum++)
1619 {
1620 if ((berParamsInit->laneMask & (1<<laneNum))!=0)
1621 {
1622 if(!(berParamsInit->bistTxMode == SERDES_DIAG_TX_MODE_CONTINUOUS))
1623 {
1624 CSL_FINSR(*(volatile uint32_t *)(SERDES_DIAG_LANE_MAP(berParamsInit->baseAddr, laneNum, 0x12c)), 13,12,0);
1625 }
1626 }
1627 }
1628
1629 for(laneNum=0;laneNum<SERDES_DIAG_MAX_LANES;laneNum++)
1630 {
1631 if ((berParamsInit->laneMask & (1<<laneNum))!=0)
1632 {
1633 if(!(berParamsInit->bistTxMode == SERDES_DIAG_TX_MODE_CONTINUOUS))
1634 {
1635 CSL_FINSR(*(volatile uint32_t *)(SERDES_DIAG_LANE_MAP(berParamsInit->baseAddr, laneNum, 0x12c)),28,26,0);
1636 }
1637 }
1638 }
1639
1640 return SERDES_DIAG_SETUP_OK;
1641}
1642
1643void Serdes_Diag_SweepBER(const SERDES_DIAG_BER_INIT_T *berParamsInit,
1644 SERDES_DIAG_SWEEP_T *pDiagSweep,
1645 CSL_SerdesTapOffsets *pTapOffsets,
1646 const SERDES_DIAG_TX_COEFF_T *diag_tx_coeff)
1647{
1648 uint32_t laneNum, count = 0, sweep1, sweep2;
1649 SERDES_DIAG_BER_VAL_T pBERval;
1650
1651 memset(&pBERval, 0, sizeof(pBERval));
1652
1653 /* sweep through tx parameters and find the best BER range */
1654 for (sweep1 = berParamsInit->sweepStart1; sweep1 <= berParamsInit->sweepEnd1; sweep1++)
1655 {
1656 for (sweep2 = berParamsInit->sweepStart2; sweep2 <= berParamsInit->sweepEnd2; sweep2++)
1657 {
1658 for(laneNum = 0; laneNum < berParamsInit->numLanes; laneNum++)
1659 {
1660 if ((berParamsInit->laneMask & (1<<laneNum))!=0)
1661 {
1662 if(berParamsInit->phyType == CSL_SERDES_PHY_TYPE_PCIe)
1663 {
1664 if(berParamsInit->pcieGenType == SERDES_DIAG_PCIE_GEN1 || berParamsInit->pcieGenType == SERDES_DIAG_PCIE_GEN2)
1665 {
1666 if(berParamsInit->sweepTxRx == SERDES_DIAG_SWEEP_TX)
1667 {
1668 CSL_FINSR(*(volatile uint32_t *)(SERDES_DIAG_LANE_MAP(berParamsInit->baseAddr, laneNum, 0x140)), 23, 23, (uint32_t)sweep1);//c1);
1669 }
1670 else if(berParamsInit->sweepTxRx == SERDES_DIAG_SWEEP_RX)
1671 {
1672 CSL_FINSR(*(volatile uint32_t *)(SERDES_DIAG_COMRXEQ_MAP(berParamsInit->baseAddr, 0xc)), 15, 8, 0x4c);
1673 CSL_FINSR(*(volatile uint32_t *)(SERDES_DIAG_COMRXEQ_MAP(berParamsInit->baseAddr, 0x34)), 10, 8, (uint32_t)sweep1); //attenuation on sweep1
1674 CSL_FINSR(*(volatile uint32_t *)(SERDES_DIAG_COMRXEQ_MAP(berParamsInit->baseAddr, 0x48)), 3, 0, (uint32_t)sweep2); //boost on sweep2
1675 CSL_FINSR(*(volatile uint32_t *)(SERDES_DIAG_COMRXEQ_MAP(berParamsInit->baseAddr, 0x4)), 31, 24, 0x4c);
1676 }
1677 }
1678 else if (berParamsInit->pcieGenType == SERDES_DIAG_PCIE_GEN3)
1679 {
1680 if(berParamsInit->sweepTxRx == SERDES_DIAG_SWEEP_TX)
1681 {
1682 printf("sweep CM, C1 presets are %d %d \n", SERDES_DIAG_PRESET_CM_MAP(sweep1), SERDES_DIAG_PRESET_C1_MAP(sweep1));
1683 CSL_FINSR(*(volatile uint32_t *)(SERDES_DIAG_LANE_MAP(berParamsInit->baseAddr, laneNum, 0x140)), 28, 23, (uint32_t)SERDES_DIAG_PRESET_CM_MAP(sweep1));
1684 CSL_FINSR(*(volatile uint32_t *)(SERDES_DIAG_LANE_MAP(berParamsInit->baseAddr, laneNum, 0x144)), 8, 3, (uint32_t)SERDES_DIAG_PRESET_C1_MAP(sweep1));
1685 }
1686 else if(berParamsInit->sweepTxRx == SERDES_DIAG_SWEEP_RX)
1687 {
1688 CSL_FINSR(*(volatile uint32_t *)(SERDES_DIAG_COMRXEQ_MAP(berParamsInit->baseAddr, 0xc)), 23, 16, 0x4c);
1689 CSL_FINSR(*(volatile uint32_t *)(SERDES_DIAG_COMRXEQ_MAP(berParamsInit->baseAddr, 0x34)), 18, 16, (uint32_t)sweep1); //attenuation on sweep1
1690 CSL_FINSR(*(volatile uint32_t *)(SERDES_DIAG_COMRXEQ_MAP(berParamsInit->baseAddr, 0x4c)), 3, 0, (uint32_t)sweep2); //boost on sweep2
1691 CSL_FINSR(*(volatile uint32_t *)(SERDES_DIAG_COMRXEQ_MAP(berParamsInit->baseAddr, 0x8)), 7, 0, 0x4c);
1692 }
1693
1694 CSL_FINSR(*(volatile uint32_t *)(SERDES_DIAG_LANE_MAP(berParamsInit->baseAddr, laneNum, 0x6c)), 5, 3, 0x0); //Default is 7 ahb_pma_ln_agc_thsel_gen3_o
1695 CSL_FINSR(*(volatile uint32_t *)(SERDES_DIAG_COMRXEQ_MAP(berParamsInit->baseAddr, 0xc)), 23, 16, 0x4f);
1696 CSL_FINSR(*(volatile uint32_t *)(SERDES_DIAG_COMRXEQ_MAP(berParamsInit->baseAddr, 0x8)), 7, 0, 0x4f);
1697 CSL_FINSR(*(volatile uint32_t *)(SERDES_DIAG_COMRXEQ_MAP(berParamsInit->baseAddr, 0x1C)), 15, 12, 0x0); //Default is 1 csr_final_boost_adjust_val_o
1698 CSL_FINSR(*(volatile uint32_t *)(SERDES_DIAG_COMRXEQ_MAP(berParamsInit->baseAddr, 0x88)), 23,22, 0x0); //Default is 3 csr_rxeq_sr_rx_att_boost_norm_o
1699 CSL_FINSR(*(volatile uint32_t *)(SERDES_DIAG_COMRXEQ_MAP(berParamsInit->baseAddr, 0x4c)), 3, 0, 0x9); //boost on sweep2
1700 }
1701 }
1702 if(berParamsInit->phyType == CSL_SERDES_PHY_TYPE_USB)
1703 {
1704 if(berParamsInit->sweepTxRx == SERDES_DIAG_SWEEP_TX)
1705 {
1706 CSL_FINSR(*(volatile uint32_t *)(SERDES_DIAG_LANE_MAP(berParamsInit->baseAddr, laneNum, 0x140)), 23, 23, (uint32_t)sweep1);//c1
1707 }
1708 else if(berParamsInit->sweepTxRx == SERDES_DIAG_SWEEP_RX)
1709 {
1710 CSL_FINSR(*(volatile uint32_t *)(SERDES_DIAG_COMRXEQ_MAP(berParamsInit->baseAddr, 0xC)), 7,0,0xC); /* calibration Rate1 default FF*/
1711 CSL_FINSR(*(volatile uint32_t *)(SERDES_DIAG_COMRXEQ_MAP(berParamsInit->baseAddr, 0x34)), 2,0,sweep1); /* att Rate1 default 2*/ //0
1712 CSL_FINSR(*(volatile uint32_t *)(SERDES_DIAG_COMRXEQ_MAP(berParamsInit->baseAddr, 0x44)), 3,0,sweep2); /* Rate1 boost start default C*/
1713 CSL_FINSR(*(volatile uint32_t *)(SERDES_DIAG_COMRXEQ_MAP(berParamsInit->baseAddr, 0x4)), 23,16,0xC); /* csr_rxeq_init_run_rate1_o*/
1714
1715 CSL_FINSR(*(volatile uint32_t *)(SERDES_DIAG_COMRXEQ_MAP(berParamsInit->baseAddr, 0xC)), 15,8,0xC); /* calibration Rate2 default FF*/
1716 CSL_FINSR(*(volatile uint32_t *)(SERDES_DIAG_COMRXEQ_MAP(berParamsInit->baseAddr, 0x34)), 10,8,sweep1); /* att Rate2 default 2*/ //0
1717 CSL_FINSR(*(volatile uint32_t *)(SERDES_DIAG_COMRXEQ_MAP(berParamsInit->baseAddr, 0x48)), 3,0,sweep2); /* Rate2 boost start default C*/
1718 CSL_FINSR(*(volatile uint32_t *)(SERDES_DIAG_COMRXEQ_MAP(berParamsInit->baseAddr, 0x4)), 31,24,0xC); /* csr_rxeq_init_run_rate2_o*/
1719 }
1720 }
1721 if(berParamsInit->phyType == CSL_SERDES_PHY_TYPE_SGMII)
1722 {
1723 CSL_FINSR(*(volatile uint32_t *)(SERDES_DIAG_LANE_MAP(berParamsInit->baseAddr, laneNum, 0x07C)), 15, 12, (uint32_t)SERDES_DIAG_PRESET_CM_MAP(sweep1));
1724 CSL_FINSR(*(volatile uint32_t *)(SERDES_DIAG_LANE_MAP(berParamsInit->baseAddr, laneNum, 0x07C)), 7, 3, (uint32_t)SERDES_DIAG_PRESET_C1_MAP(sweep1));
1725 }
1726 }
1727 }
1728
1729 CSL_serdesCycleDelay(200000);
1730
1731 if(berParamsInit->sweepTxRx == SERDES_DIAG_SWEEP_TX)
1732 {
1733 if(berParamsInit->phyType == CSL_SERDES_PHY_TYPE_USB)
1734 {
1735 pDiagSweep->sweep1[count] = sweep1;
1736 pDiagSweep->sweep2[count] = sweep1;
1737 }
1738 else
1739 {
1740 pDiagSweep->sweep1[count] = SERDES_DIAG_PRESET_CM_MAP(sweep1);
1741 pDiagSweep->sweep2[count] = SERDES_DIAG_PRESET_C1_MAP(sweep1);
1742 }
1743 }
1744 else if(berParamsInit->sweepTxRx == SERDES_DIAG_SWEEP_RX)
1745 {
1746 pDiagSweep->sweep1[count] = sweep1;
1747 pDiagSweep->sweep2[count] = sweep2;
1748 }
1749
1750 Serdes_Diag_BERTest(berParamsInit, &pBERval,pTapOffsets);
1751
1752 pDiagSweep->runTime[count] = pBERval.runTime[0];
1753
1754 for(laneNum=0;laneNum<SERDES_DIAG_MAX_LANES;laneNum++)
1755 {
1756 if ((berParamsInit->laneMask & (1<<laneNum))!=0)
1757 {
1758 switch(laneNum)
1759 {
1760 case 0:
1761
1762 pDiagSweep->berlane0[count] = pBERval.val[laneNum];
1763 pDiagSweep->bistValid0[count] = pBERval.bistValid[laneNum];
1764 pDiagSweep->att0[count] = pBERval.att[laneNum];
1765 pDiagSweep->boost0[count] = pBERval.boost[laneNum];
1766
1767 pDiagSweep->dfe1_0[count] = pBERval.dfe1[laneNum];
1768 pDiagSweep->dfe2_0[count] = pBERval.dfe2[laneNum];
1769 pDiagSweep->dfe3_0[count] = pBERval.dfe3[laneNum];
1770 pDiagSweep->dfe4_0[count] = pBERval.dfe4[laneNum];
1771 pDiagSweep->dfe5_0[count] = pBERval.dfe5[laneNum];
1772
1773 pDiagSweep->cdfe1_0[count] = pBERval.cdfe1[laneNum];
1774 pDiagSweep->cdfe2_0[count] = pBERval.cdfe2[laneNum];
1775 pDiagSweep->cdfe3_0[count] = pBERval.cdfe3[laneNum];
1776 pDiagSweep->cdfe4_0[count] = pBERval.cdfe4[laneNum];
1777 pDiagSweep->cdfe5_0[count] = pBERval.cdfe5[laneNum];
1778
1779 pDiagSweep->cdr0[count] = pBERval.cdr[laneNum];
1780 pDiagSweep->pma0[count] = pBERval.pma[laneNum];
1781
1782 pDiagSweep->dlevp0[count] = pBERval.dlevp[laneNum];
1783 pDiagSweep->dlevn0[count] = pBERval.dlevn[laneNum];
1784 pDiagSweep->dlevavg0[count] = pBERval.dlevavg[laneNum];
1785 pDiagSweep->delay0[count] = pBERval.delay[laneNum];
1786 break;
1787
1788 case 1:
1789
1790 pDiagSweep->berlane1[count] = pBERval.val[laneNum];
1791 pDiagSweep->bistValid1[count] = pBERval.bistValid[laneNum];
1792 pDiagSweep->att1[count] = pBERval.att[laneNum];
1793 pDiagSweep->boost1[count] = pBERval.boost[laneNum];
1794
1795 pDiagSweep->dfe1_1[count] = pBERval.dfe1[laneNum];
1796 pDiagSweep->dfe2_1[count] = pBERval.dfe2[laneNum];
1797 pDiagSweep->dfe3_1[count] = pBERval.dfe3[laneNum];
1798 pDiagSweep->dfe4_1[count] = pBERval.dfe4[laneNum];
1799 pDiagSweep->dfe5_1[count] = pBERval.dfe5[laneNum];
1800
1801 pDiagSweep->cdfe1_1[count] = pBERval.cdfe1[laneNum];
1802 pDiagSweep->cdfe2_1[count] = pBERval.cdfe2[laneNum];
1803 pDiagSweep->cdfe3_1[count] = pBERval.cdfe3[laneNum];
1804 pDiagSweep->cdfe4_1[count] = pBERval.cdfe4[laneNum];
1805 pDiagSweep->cdfe5_1[count] = pBERval.cdfe5[laneNum];
1806
1807 pDiagSweep->cdr1[count] = pBERval.cdr[laneNum];
1808 pDiagSweep->pma1[count] = pBERval.pma[laneNum];
1809
1810 pDiagSweep->dlevp1[count] = pBERval.dlevp[laneNum];
1811 pDiagSweep->dlevn1[count] = pBERval.dlevn[laneNum];
1812 pDiagSweep->dlevavg1[count] = pBERval.dlevavg[laneNum];
1813 pDiagSweep->delay1[count] = pBERval.delay[laneNum];
1814 break;
1815
1816 case 2:
1817
1818 pDiagSweep->berlane2[count] = pBERval.val[laneNum];
1819 pDiagSweep->bistValid2[count] = pBERval.bistValid[laneNum];
1820 pDiagSweep->att2[count] = pBERval.att[laneNum];
1821 pDiagSweep->boost2[count] = pBERval.boost[laneNum];
1822
1823 pDiagSweep->dfe1_2[count] = pBERval.dfe1[laneNum];
1824 pDiagSweep->dfe2_2[count] = pBERval.dfe2[laneNum];
1825 pDiagSweep->dfe3_2[count] = pBERval.dfe3[laneNum];
1826 pDiagSweep->dfe4_2[count] = pBERval.dfe4[laneNum];
1827 pDiagSweep->dfe5_2[count] = pBERval.dfe5[laneNum];
1828
1829 pDiagSweep->cdfe1_2[count] = pBERval.cdfe1[laneNum];
1830 pDiagSweep->cdfe2_2[count] = pBERval.cdfe2[laneNum];
1831 pDiagSweep->cdfe3_2[count] = pBERval.cdfe3[laneNum];
1832 pDiagSweep->cdfe4_2[count] = pBERval.cdfe4[laneNum];
1833 pDiagSweep->cdfe5_2[count] = pBERval.cdfe5[laneNum];
1834
1835 pDiagSweep->cdr2[count] = pBERval.cdr[laneNum];
1836 pDiagSweep->pma2[count] = pBERval.pma[laneNum];
1837
1838 pDiagSweep->dlevp2[count] = pBERval.dlevp[laneNum];
1839 pDiagSweep->dlevn2[count] = pBERval.dlevn[laneNum];
1840 pDiagSweep->dlevavg2[count] = pBERval.dlevavg[laneNum];
1841 pDiagSweep->delay2[count] = pBERval.delay[laneNum];
1842 break;
1843
1844 case 3:
1845
1846 pDiagSweep->berlane3[count] = pBERval.val[laneNum];
1847 pDiagSweep->bistValid3[count] = pBERval.bistValid[laneNum];
1848 pDiagSweep->att3[count] = pBERval.att[laneNum];
1849 pDiagSweep->boost3[count] = pBERval.boost[laneNum];
1850
1851 pDiagSweep->dfe1_3[count] = pBERval.dfe1[laneNum];
1852 pDiagSweep->dfe2_3[count] = pBERval.dfe2[laneNum];
1853 pDiagSweep->dfe3_3[count] = pBERval.dfe3[laneNum];
1854 pDiagSweep->dfe4_3[count] = pBERval.dfe4[laneNum];
1855 pDiagSweep->dfe5_3[count] = pBERval.dfe5[laneNum];
1856
1857 pDiagSweep->cdfe1_3[count] = pBERval.cdfe1[laneNum];
1858 pDiagSweep->cdfe2_3[count] = pBERval.cdfe2[laneNum];
1859 pDiagSweep->cdfe3_3[count] = pBERval.cdfe3[laneNum];
1860 pDiagSweep->cdfe4_3[count] = pBERval.cdfe4[laneNum];
1861 pDiagSweep->cdfe5_3[count] = pBERval.cdfe5[laneNum];
1862
1863 pDiagSweep->cdr3[count] = pBERval.cdr[laneNum];
1864 pDiagSweep->pma3[count] = pBERval.pma[laneNum];
1865
1866 pDiagSweep->dlevp3[count] = pBERval.dlevp[laneNum];
1867 pDiagSweep->dlevn3[count] = pBERval.dlevn[laneNum];
1868 pDiagSweep->dlevavg3[count] = pBERval.dlevavg[laneNum];
1869 pDiagSweep->delay3[count] = pBERval.delay[laneNum];
1870 break;
1871 }
1872 }
1873 }
1874 count++;
1875 }
1876 }
1877}
1878
1879SERDES_DIAG_STAT Serdes_Diag_EYETest(const SERDES_DIAG_BER_INIT_T *berParamsInit, uint32_t odd, uint32_t x_step_size, uint32_t y_step_size)
1880{
1881 uint32_t laneNum, stat, x_offset;
1882 int x_range_top, y_range_top, x_offset_loop, y_offset_loop, ber_val, y_offset;
1883
1884 // Calculate range(s) for setting BER array size
1885 x_range_top = 64/x_step_size;
1886 y_range_top = 176/y_step_size;
1887
1888 FILE *file1;
1889
1890 // NOTE: named this "flipped" since the {X,Y} are written in inverted order
1891 file1 = fopen("OnChipEye.txt","w");
1892
1893
1894 /* CSR_TXEQ_ADAPT_EN_O */
1895 CSL_FINSR(*(volatile uint32_t *)(SERDES_DIAG_COMRXEQ_MAP(berParamsInit->baseAddr, 0x34)),24,24,1);
1896 for(laneNum=0;laneNum<SERDES_DIAG_MAX_LANES;laneNum++)
1897 {
1898 if ((berParamsInit->laneMask & (1<<laneNum))!=0)
1899 {
1900 /* AHB_MSM_PMA_LN_PD_SLICER_IMON_BIAS_O */
1901 CSL_FINSR(*(volatile uint32_t *)(SERDES_DIAG_LANE_MAP(berParamsInit->baseAddr, laneNum, 0x17C)),7,6,0b01);
1902 /* AHB_MSM_PMA_LN_RST_SLICER_IMON_N_O */
1903 CSL_FINSR(*(volatile uint32_t *)(SERDES_DIAG_LANE_MAP(berParamsInit->baseAddr, laneNum, 0x17C)),21,20,0b01);
1904 /* AHB_MSM_PMA_LN_RST_SLICER_IMON_N_O */
1905 CSL_FINSR(*(volatile uint32_t *)(SERDES_DIAG_LANE_MAP(berParamsInit->baseAddr, laneNum, 0x17C)),21,20,0b11);
1906 /* AHB_MSM_PMA_LN_RST_S2P_IMON_ASYNC_O */
1907 CSL_FINSR(*(volatile uint32_t *)(SERDES_DIAG_LANE_MAP(berParamsInit->baseAddr, laneNum, 0x17C)),31,30,0b01);
1908 }
1909 }
1910
1911 /* Wait 1s (very approximately) */
1912 CSL_serdesCycleDelay(1000000);
1913
1914 /* Poll for TBUS rxeq_ctrl_rxeq_done_i */
1915 for(laneNum=0;laneNum<SERDES_DIAG_MAX_LANES;laneNum++)
1916 {
1917 if ((berParamsInit->laneMask & (1<<laneNum))!=0)
1918 {
1919 do
1920 {
1921 stat = (CSL_serdesReadSelectedTbus(berParamsInit->baseAddr, laneNum+1, 0x51) & 0x800)>>11;
1922 } while(stat == 0);
1923 }
1924 }
1925
1926 // verify RXEQ finishing and RXSD status depending on the input argument; need the capability to skip
1927 // these steps for running eye monitor in NESLB
1928 if(berParamsInit->loopbackType != CSL_SERDES_LOOPBACK_NES)
1929 {
1930 /* Poll for TBUS pma_ln_rxsd_i */
1931 for(laneNum=0;laneNum<SERDES_DIAG_MAX_LANES;laneNum++)
1932 {
1933 if ((berParamsInit->laneMask & (1<<laneNum))!=0)
1934 {
1935 do
1936 {
1937 stat = (CSL_serdesReadSelectedTbus(berParamsInit->baseAddr, laneNum+1, 0x24) & 0x002)>>1;
1938 } while(stat == 0);
1939 }
1940 }
1941 }
1942
1943
1944 for(laneNum=0;laneNum<SERDES_DIAG_MAX_LANES;laneNum++)
1945 {
1946 if ((berParamsInit->laneMask & (1<<laneNum))!=0)
1947 {
1948 /* PMA_LN_EYE_DLY_OVR_EN_O */
1949 CSL_FINSR(*(volatile uint32_t *)(SERDES_DIAG_LANE_MAP(berParamsInit->baseAddr, laneNum, 0xFC)),29,29,1);
1950 /* PMA_LN_EYE_SGN_RST_OVR_EN_O */
1951 CSL_FINSR(*(volatile uint32_t *)(SERDES_DIAG_LANE_MAP(berParamsInit->baseAddr, laneNum, 0xFC)),30,30,1);
1952 }
1953 }
1954
1955 // Input sanity checking for even/odd data eye
1956 if ((odd != 0) && (odd != 1))
1957 {
1958 printf("Error: Input \"odd\" must = 1 or 0\n");
1959 return SERDES_DIAG_SETUP_OK;
1960 }
1961
1962 /* CSR_SLICER_EYE_O_EB_O */
1963 CSL_FINSR(*(volatile uint32_t *)(SERDES_DIAG_COMRXEQ_MAP(berParamsInit->baseAddr, 0x88)),7,7,odd);
1964 /* EYE_SCAN_WAIT_LEN_O_7_0 */
1965 CSL_FINSR(*(volatile uint32_t *)(SERDES_DIAG_COMLANE_MAP(berParamsInit->baseAddr, 0x34)),15,8,0x0);
1966 /* EYE_SCAN_WAIT_LEN_O_11_8 */
1967 CSL_FINSR(*(volatile uint32_t *)(SERDES_DIAG_COMLANE_MAP(berParamsInit->baseAddr, 0x34)),19,16,0x4);
1968 /* EYE_SCAN_COUNTER_EN_O */
1969 CSL_FINSR(*(volatile uint32_t *)(SERDES_DIAG_COMLANE_MAP(berParamsInit->baseAddr, 0x30)),8,8,0x1);
1970
1971 /* Set eye_scan_mask according to odd or even */
1972 if (odd == 0)
1973 {
1974 /* EYE_SCAN_MASK_O_7_0 */
1975 CSL_FINSR(*(volatile uint32_t *)(SERDES_DIAG_COMLANE_MAP(berParamsInit->baseAddr, 0x30)),23,16,0xFB);
1976 /* EYE_SCAN_MASK_O_15_8 */
1977 CSL_FINSR(*(volatile uint32_t *)(SERDES_DIAG_COMLANE_MAP(berParamsInit->baseAddr, 0x30)),31,24,0xFF);
1978 /* EYE_SCAN_MASK_O_19_16 */
1979 CSL_FINSR(*(volatile uint32_t *)(SERDES_DIAG_COMLANE_MAP(berParamsInit->baseAddr, 0x30)),31,24,0xF);
1980 }
1981 else
1982 {
1983 /* EYE_SCAN_MASK_O_7_0 */
1984 CSL_FINSR(*(volatile uint32_t *)(SERDES_DIAG_COMLANE_MAP(berParamsInit->baseAddr, 0x30)),23,16,0xFD);
1985 /* EYE_SCAN_MASK_O_15_8 */
1986 CSL_FINSR(*(volatile uint32_t *)(SERDES_DIAG_COMLANE_MAP(berParamsInit->baseAddr, 0x30)),31,24,0xFF);
1987 /* EYE_SCAN_MASK_O_19_16 */
1988 CSL_FINSR(*(volatile uint32_t *)(SERDES_DIAG_COMLANE_MAP(berParamsInit->baseAddr, 0x30)),31,24,0xF);
1989 }
1990
1991 /* EYE_SCAN_EYE_DATA_SHIFT_O */
1992 CSL_FINSR(*(volatile uint32_t *)(SERDES_DIAG_COMLANE_MAP(berParamsInit->baseAddr, 0x30)),13,10,0xA);
1993
1994 // Top level {X,Y} loops start here
1995 for (x_offset_loop = 0; x_offset_loop < x_range_top; x_offset_loop++)
1996 {
1997 x_offset = x_offset_loop * x_step_size;
1998 for(laneNum=0;laneNum<SERDES_DIAG_MAX_LANES;laneNum++)
1999 {
2000 if ((berParamsInit->laneMask & (1<<laneNum))!=0)
2001 {
2002 /* PMA_LN_EYE_DLY_O_7_0 */
2003 CSL_FINSR(*(volatile uint32_t *)(SERDES_DIAG_LANE_MAP(berParamsInit->baseAddr, laneNum, 0x64)),7,0,x_offset);
2004 /* PMA_LN_EYE_DLY_O_8_8 */
2005 CSL_FINSR(*(volatile uint32_t *)(SERDES_DIAG_LANE_MAP(berParamsInit->baseAddr, laneNum, 0x64)),8,8,0x1);
2006 /* PMA_LN_EYE_SGN_RST_O */
2007 CSL_FINSR(*(volatile uint32_t *)(SERDES_DIAG_LANE_MAP(berParamsInit->baseAddr, laneNum, 0x64)),10,10,0x1);
2008 /* PMA_LN_EYE_SGN_RST_O */
2009 CSL_FINSR(*(volatile uint32_t *)(SERDES_DIAG_LANE_MAP(berParamsInit->baseAddr, laneNum, 0x64)),10,10,0x0);
2010 }
2011 }
2012
2013 for (y_offset_loop = 80/y_step_size; y_offset_loop < y_range_top; y_offset_loop++)
2014 {
2015 y_offset = y_offset_loop * y_step_size;
2016 for(laneNum=0;laneNum<SERDES_DIAG_MAX_LANES;laneNum++)
2017 {
2018 if ((berParamsInit->laneMask & (1<<laneNum))!=0)
2019 {
2020 /* AHB_PMA_LN_DR_SLICER_HOLD_TAP_O */
2021 CSL_FINSR(*(volatile uint32_t *)(SERDES_DIAG_LANE_MAP(berParamsInit->baseAddr, laneNum, 0x184)),7,6,0b11);
2022 /* AHB_PMA_LN_DR_SLICER_VSCAN_0_O */
2023 CSL_FINSR(*(volatile uint32_t *)(SERDES_DIAG_LANE_MAP(berParamsInit->baseAddr, laneNum, 0x18C)),16,16,0b01);
2024 /* AHB_PMA_LN_DR_SLICER_VSCAN_8_1_O */
2025 CSL_FINSR(*(volatile uint32_t *)(SERDES_DIAG_LANE_MAP(berParamsInit->baseAddr, laneNum, 0x18C)),15,8,y_offset);
2026 /* AHB_PMA_LN_DR_SLICER_HOLD_TAP_O */
2027 CSL_FINSR(*(volatile uint32_t *)(SERDES_DIAG_LANE_MAP(berParamsInit->baseAddr, laneNum, 0x184)),7,6,0b01);
2028 }
2029 }
2030
2031 /* EYE_SCAN_RUN_O = 0x1 */
2032 CSL_FINSR(*(volatile uint32_t *)(SERDES_DIAG_COMLANE_MAP(berParamsInit->baseAddr, 0x30)),9,9,0x1);
2033
2034 /* Poll for TBUS eye_scan_csr_eye_scan_cntr_ready_o */
2035 for(laneNum=0;laneNum<SERDES_DIAG_MAX_LANES;laneNum++)
2036 {
2037 if ((berParamsInit->laneMask & (1<<laneNum))!=0)
2038 {
2039 do
2040 {
2041 stat = (CSL_serdesReadSelectedTbus(berParamsInit->baseAddr, laneNum+1, 0xB2) & 0x001)>>0;
2042 } while(stat == 0);
2043 }
2044 }
2045
2046 /* EYE_SCAN_RUN_O = 0x0 */
2047 CSL_FINSR(*(volatile uint32_t *)(SERDES_DIAG_COMLANE_MAP(berParamsInit->baseAddr, 0x30)),9,9,0x0);
2048 for(laneNum=0;laneNum<SERDES_DIAG_MAX_LANES;laneNum++)
2049 {
2050 if ((berParamsInit->laneMask & (1<<laneNum))!=0)
2051 {
2052 ber_val = (CSL_serdesReadSelectedTbus(berParamsInit->baseAddr, laneNum+1, 0xB1) & 0x0FF)<<12;
2053 ber_val |= (CSL_serdesReadSelectedTbus(berParamsInit->baseAddr, laneNum+1, 0xB0) & 0xFFF);
2054 }
2055 }
2056
2057 y_offset -= 80;
2058 if (y_offset < 0)
2059 {
2060 y_offset += 176;
2061 }
2062
2063 // Print the raw BER array to the file
2064 fprintf(file1,"%d, ",ber_val);
2065 }
2066
2067 // Newline as we increment the X offset
2068 fprintf(file1,"\n");
2069
2070 }
2071
2072 // Add an extra newline so we can see where each eye monitor print out has ended and manually parse it
2073 fprintf(file1,"\n");
2074
2075 fclose(file1);
2076
2077 return SERDES_DIAG_SETUP_OK;
2078}
2079
2080/* @} */
diff --git a/src/am65xx/serdes_diag_k3.h b/src/am65xx/serdes_diag_k3.h
new file mode 100644
index 0000000..d35b8f4
--- /dev/null
+++ b/src/am65xx/serdes_diag_k3.h
@@ -0,0 +1,490 @@
1/**
2 * @file serdes_diag.h
3 *
4 * @brief
5 * Header file for functional layer of DIAGNOSTIC SERDES DIAG.
6 *
7 * It contains the various enumerations, structure definitions and function
8 * declarations
9 *
10 * \par
11 * ============================================================================
12 * @n (C) Copyright 2014, Texas Instruments, Inc.
13 *
14 * Redistribution and use in source and binary forms, with or without
15 * modification, are permitted provided that the following conditions
16 * are met:
17 *
18 * Redistributions of source code must retain the above copyright
19 * notice, this list of conditions and the following disclaimer.
20 *
21 * Redistributions in binary form must reproduce the above copyright
22 * notice, this list of conditions and the following disclaimer in the
23 * documentation and/or other materials provided with the
24 * distribution.
25 *
26 * Neither the name of Texas Instruments Incorporated nor the names of
27 * its contributors may be used to endorse or promote products derived
28 * from this software without specific prior written permission.
29 *
30 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
31 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
32 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
33 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
34 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
35 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
36 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
37 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
38 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
39 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
40 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
41 *
42*/
43
44/** ============================================================================
45 *
46 * @defgroup SERDES_DIAG SERDES DIAG
47 * @ingroup SERDES_DIAG_API
48 *
49 * @section Introduction
50 *
51 * @subsection xxx Overview
52 * A bi-directional BER Test (TX and RX enabled at both ends) can be run across the various TX
53 * filter coefficients (CM, C1 and C2) by using the Serdes_Diag_SweepCMC1C2 API in combination with
54 * synchronizing the TX and RX using DSS. The Serdes Diag package contains serdes_dss.js which
55 * controls the TX/RX synchronization using DSS.
56 *
57 * @subsection References
58 *
59 * ============================================================================
60 */
61#ifndef _DIAG_SERDES_H_
62#define _DIAG_SERDES_H_
63
64#include <stdio.h>
65#include <stdint.h>
66#include <string.h>
67#include <ti/csl/soc.h>
68#include <ti/csl/csl.h>
69#include <ti/csl/csl_serdes.h>
70
71#define SERDES_DIAG_MAX_COEFF_RANGE 512
72#define SERDES_DIAG_MAX_LANES 1
73#define SERDES_DIAG_MAX_DLY 128
74#define SERDES_DIAG_MAX_ARRAY 256
75#define SERDES_DIAG_AVERAGE_DELAY 100
76
77static const uint8_t sweepcm[] =
78{ 0, 0, 0, 0, 0, 4, 5, 7, 5, 6};
79static const uint8_t sweepc1[] =
80{ 9, 6, 7, 5, 0, 0, 0, 7, 5, 0};
81
82#define SERDES_DIAG_PRESET_CM_MAP(preset) (sweepcm[preset])
83#define SERDES_DIAG_PRESET_C1_MAP(preset) (sweepc1[preset])
84
85#define SERDES_DIAG_CMU_MAP(baseAddr, offset) (baseAddr + offset)
86#define SERDES_DIAG_LANE_MAP(baseAddr, laneNum, offset) ((baseAddr) + 0x200*(laneNum + 1) + offset)
87#define SERDES_DIAG_COMLANE_MAP(baseAddr, offset) (baseAddr + 0xa00 + offset)
88#define SERDES_DIAG_COMRXEQ_MAP(baseAddr, offset) (baseAddr + 0x1400 + offset)
89
90typedef struct SERDES_DIAG_SWEEP
91{
92 uint32_t sweep1[SERDES_DIAG_MAX_COEFF_RANGE];
93 uint32_t sweep2[SERDES_DIAG_MAX_COEFF_RANGE];
94 uint32_t sweep3[SERDES_DIAG_MAX_COEFF_RANGE];
95 uint64_t runTime[SERDES_DIAG_MAX_COEFF_RANGE];
96
97 uint32_t berlane0[SERDES_DIAG_MAX_COEFF_RANGE];
98 uint32_t berlane1[SERDES_DIAG_MAX_COEFF_RANGE];
99 uint32_t berlane2[SERDES_DIAG_MAX_COEFF_RANGE];
100 uint32_t berlane3[SERDES_DIAG_MAX_COEFF_RANGE];
101
102 uint32_t bistValid0[SERDES_DIAG_MAX_COEFF_RANGE];
103 uint32_t bistValid1[SERDES_DIAG_MAX_COEFF_RANGE];
104 uint32_t bistValid2[SERDES_DIAG_MAX_COEFF_RANGE];
105 uint32_t bistValid3[SERDES_DIAG_MAX_COEFF_RANGE];
106
107 uint32_t att0[SERDES_DIAG_MAX_COEFF_RANGE];
108 uint32_t att1[SERDES_DIAG_MAX_COEFF_RANGE];
109 uint32_t att2[SERDES_DIAG_MAX_COEFF_RANGE];
110 uint32_t att3[SERDES_DIAG_MAX_COEFF_RANGE];
111
112 uint32_t boost0[SERDES_DIAG_MAX_COEFF_RANGE];
113 uint32_t boost1[SERDES_DIAG_MAX_COEFF_RANGE];
114 uint32_t boost2[SERDES_DIAG_MAX_COEFF_RANGE];
115 uint32_t boost3[SERDES_DIAG_MAX_COEFF_RANGE];
116
117 uint32_t pma0[SERDES_DIAG_MAX_COEFF_RANGE];
118 uint32_t pma1[SERDES_DIAG_MAX_COEFF_RANGE];
119 uint32_t pma2[SERDES_DIAG_MAX_COEFF_RANGE];
120 uint32_t pma3[SERDES_DIAG_MAX_COEFF_RANGE];
121
122 uint32_t cdr0[SERDES_DIAG_MAX_COEFF_RANGE];
123 uint32_t cdr1[SERDES_DIAG_MAX_COEFF_RANGE];
124 uint32_t cdr2[SERDES_DIAG_MAX_COEFF_RANGE];
125 uint32_t cdr3[SERDES_DIAG_MAX_COEFF_RANGE];
126
127 int32_t dfe1_0[SERDES_DIAG_MAX_COEFF_RANGE];
128 int32_t dfe2_0[SERDES_DIAG_MAX_COEFF_RANGE];
129 int32_t dfe3_0[SERDES_DIAG_MAX_COEFF_RANGE];
130 int32_t dfe4_0[SERDES_DIAG_MAX_COEFF_RANGE];
131 int32_t dfe5_0[SERDES_DIAG_MAX_COEFF_RANGE];
132
133 int32_t dfe1_1[SERDES_DIAG_MAX_COEFF_RANGE];
134 int32_t dfe2_1[SERDES_DIAG_MAX_COEFF_RANGE];
135 int32_t dfe3_1[SERDES_DIAG_MAX_COEFF_RANGE];
136 int32_t dfe4_1[SERDES_DIAG_MAX_COEFF_RANGE];
137 int32_t dfe5_1[SERDES_DIAG_MAX_COEFF_RANGE];
138
139 int32_t dfe1_2[SERDES_DIAG_MAX_COEFF_RANGE];
140 int32_t dfe2_2[SERDES_DIAG_MAX_COEFF_RANGE];
141 int32_t dfe3_2[SERDES_DIAG_MAX_COEFF_RANGE];
142 int32_t dfe4_2[SERDES_DIAG_MAX_COEFF_RANGE];
143 int32_t dfe5_2[SERDES_DIAG_MAX_COEFF_RANGE];
144
145 int32_t dfe1_3[SERDES_DIAG_MAX_COEFF_RANGE];
146 int32_t dfe2_3[SERDES_DIAG_MAX_COEFF_RANGE];
147 int32_t dfe3_3[SERDES_DIAG_MAX_COEFF_RANGE];
148 int32_t dfe4_3[SERDES_DIAG_MAX_COEFF_RANGE];
149 int32_t dfe5_3[SERDES_DIAG_MAX_COEFF_RANGE];
150
151 int32_t cdfe1_0[SERDES_DIAG_MAX_COEFF_RANGE];
152 int32_t cdfe2_0[SERDES_DIAG_MAX_COEFF_RANGE];
153 int32_t cdfe3_0[SERDES_DIAG_MAX_COEFF_RANGE];
154 int32_t cdfe4_0[SERDES_DIAG_MAX_COEFF_RANGE];
155 int32_t cdfe5_0[SERDES_DIAG_MAX_COEFF_RANGE];
156
157 int32_t cdfe1_1[SERDES_DIAG_MAX_COEFF_RANGE];
158 int32_t cdfe2_1[SERDES_DIAG_MAX_COEFF_RANGE];
159 int32_t cdfe3_1[SERDES_DIAG_MAX_COEFF_RANGE];
160 int32_t cdfe4_1[SERDES_DIAG_MAX_COEFF_RANGE];
161 int32_t cdfe5_1[SERDES_DIAG_MAX_COEFF_RANGE];
162
163 int32_t cdfe1_2[SERDES_DIAG_MAX_COEFF_RANGE];
164 int32_t cdfe2_2[SERDES_DIAG_MAX_COEFF_RANGE];
165 int32_t cdfe3_2[SERDES_DIAG_MAX_COEFF_RANGE];
166 int32_t cdfe4_2[SERDES_DIAG_MAX_COEFF_RANGE];
167 int32_t cdfe5_2[SERDES_DIAG_MAX_COEFF_RANGE];
168
169 int32_t cdfe1_3[SERDES_DIAG_MAX_COEFF_RANGE];
170 int32_t cdfe2_3[SERDES_DIAG_MAX_COEFF_RANGE];
171 int32_t cdfe3_3[SERDES_DIAG_MAX_COEFF_RANGE];
172 int32_t cdfe4_3[SERDES_DIAG_MAX_COEFF_RANGE];
173 int32_t cdfe5_3[SERDES_DIAG_MAX_COEFF_RANGE];
174
175 uint32_t dlevp0[SERDES_DIAG_MAX_COEFF_RANGE];
176 uint32_t dlevp1[SERDES_DIAG_MAX_COEFF_RANGE];
177 uint32_t dlevp2[SERDES_DIAG_MAX_COEFF_RANGE];
178 uint32_t dlevp3[SERDES_DIAG_MAX_COEFF_RANGE];
179
180 uint32_t dlevn0[SERDES_DIAG_MAX_COEFF_RANGE];
181 uint32_t dlevn1[SERDES_DIAG_MAX_COEFF_RANGE];
182 uint32_t dlevn2[SERDES_DIAG_MAX_COEFF_RANGE];
183 uint32_t dlevn3[SERDES_DIAG_MAX_COEFF_RANGE];
184
185 uint32_t dlevavg0[SERDES_DIAG_MAX_COEFF_RANGE];
186 uint32_t dlevavg1[SERDES_DIAG_MAX_COEFF_RANGE];
187 uint32_t dlevavg2[SERDES_DIAG_MAX_COEFF_RANGE];
188 uint32_t dlevavg3[SERDES_DIAG_MAX_COEFF_RANGE];
189
190 int32_t dll_c0[SERDES_DIAG_MAX_COEFF_RANGE];
191 int32_t dll_c1[SERDES_DIAG_MAX_COEFF_RANGE];
192 int32_t dll_c2[SERDES_DIAG_MAX_COEFF_RANGE];
193 int32_t dll_c3[SERDES_DIAG_MAX_COEFF_RANGE];
194
195 int32_t dll_f0[SERDES_DIAG_MAX_COEFF_RANGE];
196 int32_t dll_f1[SERDES_DIAG_MAX_COEFF_RANGE];
197 int32_t dll_f2[SERDES_DIAG_MAX_COEFF_RANGE];
198 int32_t dll_f3[SERDES_DIAG_MAX_COEFF_RANGE];
199
200 int32_t delay0[SERDES_DIAG_MAX_COEFF_RANGE];
201 int32_t delay1[SERDES_DIAG_MAX_COEFF_RANGE];
202 int32_t delay2[SERDES_DIAG_MAX_COEFF_RANGE];
203 int32_t delay3[SERDES_DIAG_MAX_COEFF_RANGE];
204
205 int32_t swing[SERDES_DIAG_MAX_COEFF_RANGE];
206 int32_t deemph[SERDES_DIAG_MAX_COEFF_RANGE];
207} SERDES_DIAG_SWEEP_T;
208
209typedef struct SERDES_DIAG_BER_VAL
210{
211 uint32_t val[SERDES_DIAG_MAX_LANES];
212 uint32_t valTemp[SERDES_DIAG_MAX_LANES];
213 uint32_t bistValid[SERDES_DIAG_MAX_LANES];
214 uint32_t bistValidTemp[SERDES_DIAG_MAX_LANES];
215 uint64_t runTime[SERDES_DIAG_MAX_LANES];
216 uint32_t att[SERDES_DIAG_MAX_LANES];
217 uint32_t boost[SERDES_DIAG_MAX_LANES];
218 uint32_t pma[SERDES_DIAG_MAX_LANES];
219 uint32_t cdr[SERDES_DIAG_MAX_LANES];
220 int32_t dfe1[SERDES_DIAG_MAX_LANES];
221 int32_t dfe2[SERDES_DIAG_MAX_LANES];
222 int32_t dfe3[SERDES_DIAG_MAX_LANES];
223 int32_t dfe4[SERDES_DIAG_MAX_LANES];
224 int32_t dfe5[SERDES_DIAG_MAX_LANES];
225 int32_t cdfe1[SERDES_DIAG_MAX_LANES];
226 int32_t cdfe2[SERDES_DIAG_MAX_LANES];
227 int32_t cdfe3[SERDES_DIAG_MAX_LANES];
228 int32_t cdfe4[SERDES_DIAG_MAX_LANES];
229 int32_t cdfe5[SERDES_DIAG_MAX_LANES];
230 int32_t dlevp[SERDES_DIAG_MAX_LANES];
231 int32_t dlevn[SERDES_DIAG_MAX_LANES];
232 int32_t dlevavg[SERDES_DIAG_MAX_LANES];
233 int32_t dllC[SERDES_DIAG_MAX_LANES];
234 int32_t dllF[SERDES_DIAG_MAX_LANES];
235 int32_t delay[SERDES_DIAG_MAX_LANES];
236} SERDES_DIAG_BER_VAL_T;
237
238typedef struct SERDES_DIAG_BOOST_ATT
239{
240 uint32_t att[SERDES_DIAG_MAX_COEFF_RANGE];
241 uint32_t boost[SERDES_DIAG_MAX_COEFF_RANGE];
242 uint32_t ber[SERDES_DIAG_MAX_COEFF_RANGE];
243} SERDES_DIAG_BOOST_ATT_T;
244
245/** ============================================================================
246 * @brief
247 *
248 * SERDES PHY Transmitter Coefficients Structure */
249typedef struct SERDES_DIAG_TX_COEFF
250{
251 uint32_t txAttStart;
252 uint32_t txAttEnd;
253 uint32_t txVregStart;
254 uint32_t txVregEnd;
255 uint32_t cmCoeffStart;
256 uint32_t cmCoeffEnd;
257 uint32_t c1CoeffStart;
258 uint32_t c1CoeffEnd;
259 uint32_t c2CoeffStart;
260 uint32_t c2CoeffEnd;
261 uint32_t txSwingStart;
262 uint32_t txSwingEnd;
263 uint32_t txDeemphStart;
264 uint32_t txDeemphEnd;
265 uint32_t presetStart;
266 uint32_t presetEnd;
267}SERDES_DIAG_TX_COEFF_T;
268
269/** ============================================================================
270 * @brief
271 *
272 * SERDES PHY Receiver Coefficients Structure */
273typedef struct SERDES_DIAG_RX_COEFF
274{
275 uint32_t rxAttStart;
276 uint32_t rxAttEnd;
277 uint32_t rxBoostStart;
278 uint32_t rxBoostEnd;
279}SERDES_DIAG_RX_COEFF_T;
280
281typedef struct SERDES_DIAG_EYE_OUTPUT
282{
283 /**< Eye Width in pico seconds */
284 uint32_t eyeWidth;
285 /**< Eye Height in mV */
286 uint32_t eyeHeight;
287}SERDES_DIAG_EYE_OUTPUT_T;
288
289typedef enum
290{
291 SERDES_DIAG_PCIE_GEN1 = 1,
292
293 SERDES_DIAG_PCIE_GEN2 = 2,
294
295 SERDES_DIAG_PCIE_GEN3 = 3
296} SERDES_DIAG_PCIE_TYPE;
297
298typedef enum
299{
300 SERDES_DIAG_SWEEP_TX = 1,
301
302 SERDES_DIAG_SWEEP_RX = 2
303} SERDES_DIAG_SWEEP_TX_RX;
304
305typedef enum
306{
307 /** BER Setup OK */
308 SERDES_DIAG_SETUP_OK = 0,
309
310 /** BER Setup Timeout */
311 SERDES_DIAG_SETUP_TIME_OUT = 1,
312
313 /* BER Invalid Bus Width Setup */
314 SERDES_DIAG_INVALID_BUS_WIDTH = 2,
315
316 /* BER Invalid PHY TYPE */
317 SERDES_DIAG_INVALID_PHY_TYPE = 3
318} SERDES_DIAG_STAT;
319
320typedef enum
321{
322 /** PRBS 7 Sequence */
323 SERDES_PRBS_7 = 0,
324
325 /** PRBS 15 Sequence */
326 SERDES_PRBS_15 = 1,
327
328 /* PRBS 23 Sequence */
329 SERDES_PRBS_23 = 2,
330
331 /* PRBS 31 Sequence */
332 SERDES_PRBS_31 = 3,
333
334 /* UDP Pattern */
335 SERDES_UDP = 4
336} SERDES_DIAG_PRBS_PATTERN;
337
338typedef enum
339{
340 /** BIST TX CLK Disable */
341 SERDES_DIAG_BIST_TX_CLK_DISABLED = 0,
342
343 /** BIST TX CLK Enable */
344 SERDES_DIAG_BIST_TX_CLK_ENABLED = 1
345} SERDES_DIAG_BIST_TX_CLK;
346
347typedef enum
348{
349 /** BIST RX CLK Disable */
350 SERDES_DIAG_BIST_RX_CLK_DISABLED = 0,
351
352 /** BIST RX CLK Enable */
353 SERDES_DIAG_BIST_RX_CLK_ENABLED = 1
354} SERDES_DIAG_BIST_RX_CLK;
355
356typedef enum
357{
358 SERDES_DIAG_TX_MODE_CONTINUOUS = 1,
359
360 SERDES_DIAG_TX_MODE_NORMAL = 0
361}SERDES_DIAG_TX_MODE;
362
363typedef struct SERDES_DIAG_BER_INIT
364{
365 /**< Serdes Base Address */
366 uint32_t baseAddr;
367 /**< Number of lanes to be configured */
368 uint32_t numLanes;
369 /**< BER Test Duration */
370 uint64_t bertesttime;
371 /**< PRBS Pattern Generator used */
372 SERDES_DIAG_PRBS_PATTERN prbsPattern;
373 /**< Time Out value before test iteration exits */
374 uint64_t timeoutLoops;
375 /**< Serdes PHY Type enumerator */
376 /**< PCIe Gen type Enumerator */
377 CSL_SerdesPhyType phyType;
378 SERDES_DIAG_PCIE_TYPE pcieGenType;
379 /**< BIST Generator Transmit Enable */
380 SERDES_DIAG_BIST_TX_CLK bistTxClkEn;
381 /**< BIST Generator Receiver Enable */
382 SERDES_DIAG_BIST_RX_CLK bistRxClkEn;
383 /**< Type of BIST Test Setup */
384 CSL_SerdesLoopback loopbackType;
385 /**< Polarity */
386 uint32_t polarity[SERDES_DIAG_MAX_LANES];
387 /**< Lane Control Rate */
388 CSL_SerdesLaneCtrlRate laneCtrlRate;
389 /**< Lane Mask */
390 uint8_t laneMask;
391 /**< Force Attenuation Boost Flag */
392 uint8_t forceAttBoost;
393 /**< Force Attenuation Value */
394 uint8_t forceAttVal;
395 /**< Force Boost Value */
396 uint8_t forceBoostVal;
397 /**< Sweep TX or RX flag */
398 SERDES_DIAG_SWEEP_TX_RX sweepTxRx;
399 /**< Sweep Start value */
400 uint32_t sweepStart1;
401 /**< Sweep End Value */
402 uint32_t sweepEnd1;
403 /**< Sweep Start value */
404 uint32_t sweepStart2;
405 /**< Sweep End Value */
406 uint32_t sweepEnd2;
407 /**< Tx Mode Value */
408 SERDES_DIAG_TX_MODE bistTxMode;
409} SERDES_DIAG_BER_INIT_T;
410
411typedef struct SERDES_DIAG_EYE_INIT
412{
413 /**< Serdes Base Address */
414 uint32_t baseAddr;
415 /**< Lane Number to be configured */
416 int32_t laneNum;
417 /**< Number of lanes to be configured */
418 int32_t numLanes;
419 /**< Serdes Phase Degree */
420 int32_t phaseNum;
421 /**< Serdes Test Gating Time */
422 uint64_t gateTime;
423 /**< Serdes voltage incremental offset */
424 int32_t vOffset;
425 /**< Serdes Time incremental offset */
426 int32_t tOffset;
427 /**< Serdes Eye Calibration Flag */
428 int32_t calibrateEye;
429 /**< Serdes PHY Type enumerator */
430 CSL_SerdesPhyType phyType;
431 /**< PCIe Gen type Enumerator */
432 SERDES_DIAG_PCIE_TYPE pcieGenType;
433 int32_t laneMask;
434 CSL_SerdesLinkRate linkRate;
435} SERDES_DIAG_EYE_INIT_T;
436
437
438extern volatile uint32_t serdes_diag_dss_lock_key;
439extern volatile uint32_t serdes_diag_dss_unlock_key;
440
441/* start locked */
442extern volatile uint32_t serdes_diag_dss_stall_key0;
443/* start locked */
444extern volatile uint32_t serdes_diag_dss_stall_key1;
445/* start locked */
446extern volatile uint32_t serdes_diag_dss_stall_key2;
447
448extern volatile uint32_t serdes_diag_dss_stall_flag_set;
449extern volatile uint32_t serdes_diag_dss_stall_flag_clear;
450
451/* start with flag cleared */
452extern volatile uint32_t serdes_diag_dss_stall_flag0;
453/* start with flag cleared */
454extern volatile uint32_t serdes_diag_dss_stall_flag1;
455/* start with flag cleared */
456extern volatile uint32_t serdes_diag_dss_stall_flag2;
457
458extern volatile uint32_t serdes_diag_dss_test_complete_flag_set;
459/* start with flag cleared */
460extern volatile uint32_t serdes_diag_dss_test_complete_flag;
461
462extern volatile uint16_t serdes_diag_eye_scan_errors_array[SERDES_DIAG_MAX_ARRAY]
463 [SERDES_DIAG_MAX_DLY];
464
465extern void CSL_serdesCycleDelay (uint64_t count);
466extern void Serdes_Diag_SetFESLoopback(uint32_t baseAddr, uint32_t laneNum);
467extern void Serdes_Diag_SetFEPLoopback(uint32_t baseAddr, uint32_t laneNum);
468extern void Serdes_Diag_SetFEP1p5Loopback(uint32_t baseAddr, uint32_t laneNum);
469extern void Serdes_Diag_PCIeCtrlOverride(const SERDES_DIAG_BER_INIT_T *berParamsInit);
470extern void Serdes_Diag_USBCtrlOverride(const SERDES_DIAG_BER_INIT_T *berParamsInit);
471extern void Serdes_Diag_SGMIICtrlOverride(const SERDES_DIAG_BER_INIT_T *berParamsInit);
472extern SERDES_DIAG_STAT Serdes_Diag_BERTestTX(const SERDES_DIAG_BER_INIT_T *berParamsInit);
473
474extern SERDES_DIAG_STAT Serdes_Diag_BERTest(const SERDES_DIAG_BER_INIT_T *berParamsInit,
475 SERDES_DIAG_BER_VAL_T *pBERval,
476 CSL_SerdesTapOffsets *pTapOffsets);
477
478extern void Serdes_Diag_SweepBER(const SERDES_DIAG_BER_INIT_T *berParamsInit,
479 SERDES_DIAG_SWEEP_T *pDiagCMC1C2,
480 CSL_SerdesTapOffsets *pTapOffsets,
481 const SERDES_DIAG_TX_COEFF_T *diag_tx_coeff);
482extern SERDES_DIAG_STAT Serdes_Diag_EYETest(const SERDES_DIAG_BER_INIT_T *berParamsInit,
483 uint32_t odd,
484 uint32_t x_step_size,
485 uint32_t y_step_size);
486
487
488#endif
489
490/* @} */
diff --git a/src/src_files_common.mk b/src/src_files_common.mk
new file mode 100644
index 0000000..26cd37f
--- /dev/null
+++ b/src/src_files_common.mk
@@ -0,0 +1,22 @@
1
2ifeq ($(SOC),$(filter $(SOC), k2h k2k k2l k2e k2g))
3
4PACKAGE_SRCS_COMMON += src/serdes_diag.c
5PACKAGE_SRCS_COMMON += serdes_diag.h
6
7SRCDIR = . src src/..
8INCDIR = . src src/..
9
10endif
11
12ifeq ($(SOC),$(filter $(SOC), am65xx))
13
14PACKAGE_SRCS_COMMON += src/am65xx/serdes_diag_k3.h
15
16SRCS_COMMON += serdes_diag_k3.c
17
18SRCDIR = . src src/am65xx
19INCDIR = . src src/am65xx
20
21endif
22
diff --git a/test/am65xx/makefile_BER b/test/am65xx/makefile_BER
new file mode 100644
index 0000000..25347a8
--- /dev/null
+++ b/test/am65xx/makefile_BER
@@ -0,0 +1,51 @@
1# Makefile for UART sample app
2include $(PDK_INSTALL_PATH)/ti/build/Rules.make
3ifeq ($(BAREMETAL),yes)
4BUILD_OS_TYPE=baremetal
5OS_FLAGS=-DBAREMETAL
6LNKFLAGS_LOCAL_mpu1_0 += --entry Entry
7# List all the external components/interfaces, whose interface header files
8# need to be included for this component
9INCLUDE_EXTERNAL_INTERFACES = pdk
10# List all the components required by the application
11COMP_LIST_COMMON = csl csl_init
12# List all the external components/interfaces, whose interface header files
13# need to be included for this component
14INCLUDE_EXTERNAL_INTERFACES = pdk
15# List all the components required by the application
16COMP_LIST_COMMON = csl serdes_diag
17
18else
19BUILD_OS_TYPE=tirtos
20OS_FLAGS=-DTIRTOS
21
22endif
23APP_NAME = serdes_diag_BER_app
24SRCDIR = . $(PDK_INSTALL_PATH)/ti/diag/serdes_diag/test/am65xx
25SRCDIR += $(PDK_INSTALL_PATH)/ti/diag/serdes_diag/test/src
26
27INCDIR = . src
28INCDIR += $(PDK_INSTALL_PATH)/ti/csl
29INCDIR += $(PDK_INSTALL_PATH)/ti/diag/serdes_diag/src/am65xx
30INCDIR += $(PDK_INSTALL_PATH)/ti/diag/serdes_diag/test/src
31INCDIR += $(PDK_INSTALL_PATH)/ti/diag/serdes_diag/test/am65xx
32
33# Common source files across all platforms and cores
34SRCS_COMMON += serdes_diag_test_init.c serdes_diag_test.c serdes_diag_test_main.c
35
36EXTERNAL_LNKCMD_FILE_LOCAL = $(pdk_PATH)/ti/diag/serdes_diag/test/am65xx/serdes_diag_linker_r5.lds
37
38PACKAGE_SRCS_COMMON = .
39CFLAGS_LOCAL_COMMON = $(PDK_CFLAGS) -DRUN_BER_TEST
40# Include common make files
41ifeq ($(MAKERULEDIR), )
42#Makerule path not defined, define this and assume relative path from ROOTDIR
43 MAKERULEDIR := $(ROOTDIR)/ti/build/makerules
44 export MAKERULEDIR
45endif
46include $(MAKERULEDIR)/common.mk
47
48# OBJs and libraries are built by using rule defined in rules_<target>.mk
49# and need not be explicitly specified here
50
51# Nothing beyond this point
diff --git a/test/am65xx/makefile_EYE b/test/am65xx/makefile_EYE
new file mode 100644
index 0000000..1630cde
--- /dev/null
+++ b/test/am65xx/makefile_EYE
@@ -0,0 +1,51 @@
1# Makefile for UART sample app
2include $(PDK_INSTALL_PATH)/ti/build/Rules.make
3ifeq ($(BAREMETAL),yes)
4BUILD_OS_TYPE=baremetal
5OS_FLAGS=-DBAREMETAL
6LNKFLAGS_LOCAL_mpu1_0 += --entry Entry
7# List all the external components/interfaces, whose interface header files
8# need to be included for this component
9INCLUDE_EXTERNAL_INTERFACES = pdk
10# List all the components required by the application
11COMP_LIST_COMMON = csl csl_init
12# List all the external components/interfaces, whose interface header files
13# need to be included for this component
14INCLUDE_EXTERNAL_INTERFACES = pdk
15# List all the components required by the application
16COMP_LIST_COMMON = csl serdes_diag
17
18else
19BUILD_OS_TYPE=tirtos
20OS_FLAGS=-DTIRTOS
21
22endif
23APP_NAME = serdes_diag_EYE_app
24SRCDIR = . $(PDK_INSTALL_PATH)/ti/diag/serdes_diag/test/am65xx
25SRCDIR += $(PDK_INSTALL_PATH)/ti/diag/serdes_diag/test/src
26
27INCDIR = . src
28INCDIR += $(PDK_INSTALL_PATH)/ti/csl
29INCDIR += $(PDK_INSTALL_PATH)/ti/diag/serdes_diag/src/am65xx
30INCDIR += $(PDK_INSTALL_PATH)/ti/diag/serdes_diag/test/src
31INCDIR += $(PDK_INSTALL_PATH)/ti/diag/serdes_diag/test/am65xx
32
33# Common source files across all platforms and cores
34SRCS_COMMON += serdes_diag_test_init.c serdes_diag_test.c serdes_diag_test_main.c
35
36EXTERNAL_LNKCMD_FILE_LOCAL = $(pdk_PATH)/ti/diag/serdes_diag/test/am65xx/serdes_diag_linker_r5.lds
37
38PACKAGE_SRCS_COMMON = .
39CFLAGS_LOCAL_COMMON = $(PDK_CFLAGS) -DRUN_EYE_SCAN_TEST
40# Include common make files
41ifeq ($(MAKERULEDIR), )
42#Makerule path not defined, define this and assume relative path from ROOTDIR
43 MAKERULEDIR := $(ROOTDIR)/ti/build/makerules
44 export MAKERULEDIR
45endif
46include $(MAKERULEDIR)/common.mk
47
48# OBJs and libraries are built by using rule defined in rules_<target>.mk
49# and need not be explicitly specified here
50
51# Nothing beyond this point
diff --git a/test/am65xx/serdes_diag_linker_r5.lds b/test/am65xx/serdes_diag_linker_r5.lds
new file mode 100644
index 0000000..126e043
--- /dev/null
+++ b/test/am65xx/serdes_diag_linker_r5.lds
@@ -0,0 +1,83 @@
1/*----------------------------------------------------------------------------*/
2/* File: serdes_diag_linker_r5.cmd */
3/* Description: */
4/* Link command file for AM65XX M4 MCU 0 view */
5/* TI ARM Compiler version 15.12.3 LTS or later */
6/* */
7/* Platform: QT */
8/* (c) Texas Instruments 2016, All rights reserved. */
9/*----------------------------------------------------------------------------*/
10
11
12/*----------------------------------------------------------------------------*/
13/* Linker Settings */
14
15/* Standard linker options */
16--retain="*(.intvecs)"
17--fill_value=0 /* Default hole fill value */
18--stack_size=0x2000 /* Default 4KB stack */
19--heap_size=0x2000 /* Default 4KB heap */
20--entry_point=_c_int00 /* Default C RTS boot.asm */
21
22/* Additional settings (if any) */
23
24/*----------------------------------------------------------------------------*/
25/* Memory Map */
26
27MEMORY
28{
29 VECTORS (X) : origin=0x41C7FFE0 length=0x00000020
30 /* MCU0_R5F local view */
31 MCU0_R5F_TCMA (X) : origin=0 length=0x8000
32 MCU0_R5F_TCMB0 (RW) : origin=0x40000000 length=0x4000
33 MCU0_R5F_TCMB1 (RW) : origin=0x40004000 length=0x4000
34
35 /* MCU0_R5F_0 SoC view */
36 MCU0_R5F0_TCMA (X) : origin=0x41000000 length=0x8000 /* 32KB */
37 MCU0_R5F0_TCMB0 (RW) : origin=0x41008000 length=0x4000 /* 16KB */
38 MCU0_R5F0_TCMB1 (RW) : origin=0x4100C000 length=0x4000 /* 16KB */
39
40 /* MCU0_R5F_1 SoC view */
41 MCU0_R5F1_ATCM (X) : origin=0x41400000 length=0x8000
42 MCU0_R5F1_BTCM (RW) : origin=0x41408000 length=0x8000
43 /* MCU0 share locations */
44 OCMRAM (RWIX) : origin=0x41C00000 length=0x80000 - 0x20 /* 512KB (less 32 bytes) */
45 /* Maxwell M4 locations */
46 MSMC3 (RWIX) : origin=0x70000000 length=0x200000 /* 2MB */
47 DDR (RWIX) : origin=0x80000000 length=0x100000000 /* 4GB */
48
49/* Additional memory settings */
50
51} /* end of MEMORY */
52
53/* Other settings */
54
55/*----------------------------------------------------------------------------*/
56/* Section Configuration */
57
58SECTIONS
59{
60 .intvecs : {} palign(8) > VECTORS
61 .text : {} palign(8) > OCMRAM
62 .const : {} palign(8) > OCMRAM
63 .cinit : {} palign(8) > OCMRAM
64 .pinit : {} palign(8) > OCMRAM
65 .bss : {} align(4) > OCMRAM
66 .data : {} palign(128) > OCMRAM
67 .sysmem : {} > OCMRAM
68 .stack : {} align(4) > OCMRAM (HIGH)
69 .inputDatMem: {} palign(128) > OCMRAM
70 .inDDR : {} palign(128) > DDR
71 .inmsmc : {} > MSMC3
72 .inOCRAM : {} palign(128) > OCMRAM
73
74
75/* Additional sections settings */
76
77} /* end of SECTIONS */
78
79/*----------------------------------------------------------------------------*/
80/* Misc linker settings */
81
82
83/*-------------------------------- END ---------------------------------------*/
diff --git a/test/am65xx/serdes_diag_platform.h b/test/am65xx/serdes_diag_platform.h
new file mode 100644
index 0000000..ccd5a29
--- /dev/null
+++ b/test/am65xx/serdes_diag_platform.h
@@ -0,0 +1,94 @@
1/*
2 *
3 * Copyright (C) 2015 Texas Instruments Incorporated - http://www.ti.com/
4 *
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:
9 *
10 * Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 *
13 * Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the
16 * distribution.
17 *
18 * Neither the name of Texas Instruments Incorporated nor the names of
19 * its contributors may be used to endorse or promote products derived
20 * from this software without specific prior written permission.
21 *
22 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
23 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
24 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
25 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
26 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
27 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
28 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
29 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
30 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
32 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 *
34*/
35
36/*
37 * This file contains the prototypes for functions that interface with
38 * Serdes Diag APIs. They are common among all tests/examples.
39 */
40
41#include <ti/csl/csl_serdes.h>
42
43#define TEST_SERDES_USB 0
44#define TEST_SERDES_PCIe 1
45#define TEST_SERDES_SGMII 2
46
47/* Set your serdes_diag_test_phy_type here */
48//#define serdes_diag_test_phy_type TEST_SERDES_USB /* Enables PCIe serdes tests */
49#define serdes_diag_test_phy_type TEST_SERDES_PCIe /* Enables SGMII serdes tests */
50//#define serdes_diag_test_phy_type TEST_SERDES_SGMII /* Enables USB serdes tests */
51
52#if defined(SOC_AM65XX)
53 #if (serdes_diag_test_phy_type == TEST_SERDES_USB)
54 #define SERDES_DIAG_TEST_BASE_ADDR CSL_SERDES0_BASE /* Serdes base address */
55 #define SERDES_DIAG_TEST_REF_CLOCK CSL_SERDES_REF_CLOCK_100M /* Ref clock of serdes */
56 #define SERDES_DIAG_TEST_LINK_RATE CSL_SERDES_LINK_RATE_5G /* Link rate of serdes */
57 #define SERDES_DIAG_TEST_NUM_LANES 1 /* Number of lanes to be tested */
58 #define SERDES_DIAG_TEST_LANE_MASK 0x1 /* All lanes are set */
59 #define SERDES_DIAG_TEST_PHY_TYPE CSL_SERDES_PHY_TYPE_USB /* For running USB tests */
60 #define SERDES_DIAG_TEST_PCIE_GEN_TYPE SERDES_DIAG_PCIE_GEN3 /* For running PCIe tests */
61 #define SERDES_DIAG_TEST_PRBS_PATTERN SERDES_PRBS_7 /* prbs7 pattern */
62 #define SERDES_DIAG_TEST_LANE_RATE CSL_SERDES_LANE_FULL_RATE /* Set to run at full rate of the link rate */
63 #define SERDES_DIAG_TEST_LOOPBACK_MODE CSL_SERDES_LOOPBACK_NES /* For internal near end serial loopback tests */
64 #define SERDES_DIAG_TEST_OPERATING_MODE CSL_SERDES_DIAGNOSTIC_MODE /* Should always be set to Diagnostic Mode for BER, EYE and PRBS tests */
65 #define SERDES_DIAG_TEST_FORCEATTBOOST CSL_SERDES_FORCE_ATT_BOOST_DISABLED
66 #define SERDES_DIAG_TEST_SWEEPTXRX SERDES_DIAG_SWEEP_RX
67#elif (serdes_diag_test_phy_type == TEST_SERDES_PCIe)
68 #define SERDES_DIAG_TEST_BASE_ADDR CSL_SERDES0_BASE /* Serdes base address */
69 #define SERDES_DIAG_TEST_REF_CLOCK CSL_SERDES_REF_CLOCK_100M /* Ref clock of serdes */
70 #define SERDES_DIAG_TEST_LINK_RATE CSL_SERDES_LINK_RATE_8G /* Link rate of serdes */
71 #define SERDES_DIAG_TEST_NUM_LANES 1 /* Number of lanes to be tested */
72 #define SERDES_DIAG_TEST_LANE_MASK 0x1 /* All lanes are set */
73 #define SERDES_DIAG_TEST_PHY_TYPE CSL_SERDES_PHY_TYPE_PCIe /* For running PCIe tests */
74 #define SERDES_DIAG_TEST_PCIE_GEN_TYPE SERDES_DIAG_PCIE_GEN3 /* For running PCIe tests */
75 #define SERDES_DIAG_TEST_PRBS_PATTERN SERDES_PRBS_7 /* prbs7 pattern */
76 #define SERDES_DIAG_TEST_LANE_RATE CSL_SERDES_LANE_FULL_RATE /* Set to run at full rate of the link rate */
77 #define SERDES_DIAG_TEST_LOOPBACK_MODE CSL_SERDES_LOOPBACK_NES /* For internal near end serial loopback tests */
78 #define SERDES_DIAG_TEST_OPERATING_MODE CSL_SERDES_DIAGNOSTIC_MODE /* Should always be set to Diagnostic Mode for BER, EYE and PRBS tests */
79 #define SERDES_DIAG_TEST_FORCEATTBOOST CSL_SERDES_FORCE_ATT_BOOST_DISABLED
80 #define SERDES_DIAG_TEST_SWEEPTXRX SERDES_DIAG_SWEEP_TX
81#elif (serdes_diag_test_phy_type == TEST_SERDES_SGMII)
82 #define SERDES_DIAG_TEST_BASE_ADDR CSL_SERDES0_BASE /* Serdes base address */
83 #define SERDES_DIAG_TEST_REF_CLOCK CSL_SERDES_REF_CLOCK_156p25M /* Ref clock of serdes */
84 #define SERDES_DIAG_TEST_LINK_RATE CSL_SERDES_LINK_RATE_5G /* Set 5G for 1.25G, set 6p25G for 3.125G */
85 #define SERDES_DIAG_TEST_NUM_LANES 1 /* Number of lanes to be tested */
86 #define SERDES_DIAG_TEST_LANE_MASK 0x1 /* All lanes are set */
87 #define SERDES_DIAG_TEST_PHY_TYPE CSL_SERDES_PHY_TYPE_SGMII /* For running SGMII tests */
88 #define SERDES_DIAG_TEST_PRBS_PATTERN SERDES_PRBS_7 /* prbs7 pattern */
89 #define SERDES_DIAG_TEST_LANE_RATE CSL_SERDES_LANE_QUARTER_RATE /* Set to run at quarter rate for 1.25G and half rate for 3.125G */
90 #define SERDES_DIAG_TEST_LOOPBACK_MODE CSL_SERDES_LOOPBACK_NES /* For internal near end serial loopback tests */
91 #define SERDES_DIAG_TEST_OPERATING_MODE CSL_SERDES_DIAGNOSTIC_MODE /* Should always be set to Diagnostic Mode for BER, EYE and PRBS tests */
92 #define SERDES_DIAG_TEST_FORCEATTBOOST CSL_SERDES_FORCE_ATT_BOOST_DISABLED
93#endif
94#endif
diff --git a/test/am65xx/serdes_diag_test.c b/test/am65xx/serdes_diag_test.c
new file mode 100644
index 0000000..2f21cb9
--- /dev/null
+++ b/test/am65xx/serdes_diag_test.c
@@ -0,0 +1,316 @@
1/*
2 *
3 * Copyright (C) 2015 Texas Instruments Incorporated - http://www.ti.com/
4 *
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:
9 *
10 * Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 *
13 * Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the
16 * distribution.
17 *
18 * Neither the name of Texas Instruments Incorporated nor the names of
19 * its contributors may be used to endorse or promote products derived
20 * from this software without specific prior written permission.
21 *
22 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
23 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
24 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
25 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
26 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
27 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
28 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
29 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
30 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
32 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 *
34*/
35
36
37#include <ti/diag/serdes_diag/src/am65xx/serdes_diag_k3.h>
38#include <ti/csl/csl_serdes.h>
39#include "serdes_diag_test.h"
40#include "serdes_diag_platform.h"
41#include "string.h"
42
43
44uint32_t diag_serdes_device_num = 0;
45char filename_ber_scan[30];
46char filename_eye_scan[30];
47char filename_prbs_scan[30];
48FILE *file_ber_scan;
49FILE *file_eye_scan;
50FILE *file_prbs_scan;
51SERDES_DIAG_SWEEP_T sweepber;
52
53
54
55SERDES_DIAG_STAT Serdes_Example_BERTest()
56{
57
58 uint32_t count =0, laneNum, sweep1, sweep2;
59 CSL_SerdesTapOffsets pTapOffsets;
60 SERDES_DIAG_TX_COEFF_T diagTxCoeff;
61 SERDES_DIAG_RX_COEFF_T diagRxCoeff;
62 SERDES_DIAG_BER_INIT_T berParamsInit;
63
64 memset(&sweepber, 0, sizeof(sweepber));
65 memset (&berParamsInit, 0, sizeof(berParamsInit));
66 memset(&diagTxCoeff, 0, sizeof(diagTxCoeff));
67 memset (&pTapOffsets, 0, sizeof(pTapOffsets));
68
69 berParamsInit.laneCtrlRate = SERDES_DIAG_TEST_LANE_RATE;
70 berParamsInit.phyType = SERDES_DIAG_TEST_PHY_TYPE;
71 berParamsInit.baseAddr = SERDES_DIAG_TEST_BASE_ADDR;
72 berParamsInit.numLanes = SERDES_DIAG_TEST_NUM_LANES;
73 berParamsInit.laneMask = SERDES_DIAG_TEST_LANE_MASK;
74 berParamsInit.bertesttime = 2000000;
75 berParamsInit.timeoutLoops = 1000000;
76 berParamsInit.prbsPattern = SERDES_DIAG_TEST_PRBS_PATTERN;
77 berParamsInit.forceAttBoost = SERDES_DIAG_TEST_FORCEATTBOOST;
78 berParamsInit.sweepTxRx = SERDES_DIAG_TEST_SWEEPTXRX;
79 berParamsInit.loopbackType = SERDES_DIAG_TEST_LOOPBACK_MODE;
80 berParamsInit.bistTxMode = SERDES_DIAG_TX_MODE_CONTINUOUS;
81 berParamsInit.pcieGenType = SERDES_DIAG_TEST_PCIE_GEN_TYPE;
82
83 diagRxCoeff.rxAttStart = 0;
84 diagRxCoeff.rxAttEnd = 8;
85 diagRxCoeff.rxBoostStart = 0;
86 diagRxCoeff.rxBoostEnd = 16;
87
88 if(berParamsInit.phyType == CSL_SERDES_PHY_TYPE_PCIe && berParamsInit.pcieGenType == SERDES_DIAG_PCIE_GEN3)
89 {
90 diagTxCoeff.presetStart = 0;
91 diagTxCoeff.presetEnd = 9;
92 }
93 else if (berParamsInit.phyType == CSL_SERDES_PHY_TYPE_SGMII)
94 {
95 diagTxCoeff.presetStart = 0;
96 diagTxCoeff.presetEnd = 9;
97 }
98 else
99 {
100 diagTxCoeff.presetStart = 0;
101 diagTxCoeff.presetEnd = 1;
102 }
103
104 if(berParamsInit.sweepTxRx == SERDES_DIAG_SWEEP_TX)
105 {
106 berParamsInit.sweepStart1 = diagTxCoeff.presetStart;
107 berParamsInit.sweepEnd1 = diagTxCoeff.presetEnd;
108 berParamsInit.sweepStart2 = 0; //Dummy sweep to be compatible with rx 2d sweep
109 berParamsInit.sweepEnd2 = 0; //Dummy sweep to be compatible with rx 2d sweep
110 }
111 else if(berParamsInit.sweepTxRx == SERDES_DIAG_SWEEP_RX)
112 {
113 berParamsInit.sweepStart1 = diagRxCoeff.rxAttStart;
114 berParamsInit.sweepEnd1 = diagRxCoeff.rxAttEnd;
115 berParamsInit.sweepStart2 = diagRxCoeff.rxBoostStart;
116 berParamsInit.sweepEnd2 = diagRxCoeff.rxBoostEnd;
117 }
118
119 if(berParamsInit.forceAttBoost)
120 {
121 berParamsInit.forceAttVal = 3;
122 berParamsInit.forceBoostVal = 12;
123 }
124
125 berParamsInit.bistTxClkEn = SERDES_DIAG_BIST_TX_CLK_ENABLED;
126 berParamsInit.bistRxClkEn = SERDES_DIAG_BIST_RX_CLK_ENABLED;
127
128#if (serdes_diag_test_phyType == TEST_SERDES_PCIe)
129 berParamsInit.pcieGenType = SERDES_DIAG_TEST_PCIE_GEN_TYPE;
130#endif
131
132 printf("Setting Lane Ctrl Overrides \n");
133 for(laneNum = 0; laneNum < berParamsInit.numLanes; laneNum++)
134 {
135 if ((berParamsInit.laneMask & (1<<laneNum))!=0)
136 {
137 if(berParamsInit.phyType == CSL_SERDES_PHY_TYPE_PCIe)
138 {
139 Serdes_Diag_PCIeCtrlOverride(&berParamsInit);
140 }
141 else if(berParamsInit.phyType == CSL_SERDES_PHY_TYPE_USB)
142 {
143 Serdes_Diag_USBCtrlOverride(&berParamsInit);
144 }
145 else if(berParamsInit.phyType == CSL_SERDES_PHY_TYPE_SGMII)
146 {
147 Serdes_Diag_SGMIICtrlOverride(&berParamsInit);
148 }
149 }
150 }
151
152// for(laneNum = 0; laneNum < berParamsInit.numLanes; laneNum++)
153// {
154// CSL_SerdesInvertLanePolarity(berParamsInit.baseAddr,laneNum);
155// }
156
157 if(berParamsInit.loopbackType == CSL_SERDES_LOOPBACK_FEP)
158 {
159 for(laneNum = 0; laneNum < berParamsInit.numLanes; laneNum++)
160 {
161 if ((berParamsInit.laneMask & (1<<laneNum))!=0)
162 {
163 Serdes_Diag_SetFEPLoopback(berParamsInit.baseAddr, laneNum);
164 }
165 }
166 printf("FEP Loopback Setup Complete! Exiting setup\n");
167 return SERDES_DIAG_SETUP_OK;
168 }
169
170 if(berParamsInit.loopbackType == CSL_SERDES_LOOPBACK_FEP1p5)
171 {
172 for(laneNum = 0; laneNum < berParamsInit.numLanes; laneNum++)
173 {
174 if ((berParamsInit.laneMask & (1<<laneNum))!=0)
175 {
176 Serdes_Diag_SetFEP1p5Loopback(berParamsInit.baseAddr, laneNum);
177 }
178 }
179 printf("FEP1.5 Loopback Setup Complete! Exiting setup\n");
180 return SERDES_DIAG_SETUP_OK;
181 }
182
183 if(berParamsInit.loopbackType == CSL_SERDES_LOOPBACK_FES)
184 {
185 for(laneNum = 0; laneNum < berParamsInit.numLanes; laneNum++)
186 {
187 if ((berParamsInit.laneMask & (1<<laneNum))!=0)
188 {
189 Serdes_Diag_SetFESLoopback(berParamsInit.baseAddr, laneNum);
190 }
191 }
192 printf("FES Loopback Setup Complete! Exiting setup\n");
193 return SERDES_DIAG_SETUP_OK;
194 }
195
196 if(berParamsInit.loopbackType == CSL_SERDES_LOOPBACK_TX_TO_BERT)
197 {
198 Serdes_Diag_BERTestTX(&berParamsInit);
199 printf("TX to external Setup Complete! Exiting setup\n");
200 return SERDES_DIAG_SETUP_OK;
201 }
202
203 if(berParamsInit.loopbackType == CSL_SERDES_LOOPBACK_PIPE)
204 {
205 printf("PIPE Loopback Setup Complete! Exiting setup\n");
206 return SERDES_DIAG_SETUP_OK;
207 }
208
209 printf("Entering BER Sweep Setup \n");
210 Serdes_Diag_SweepBER(&berParamsInit, &sweepber, &pTapOffsets, &diagTxCoeff);
211
212 sprintf(filename_ber_scan, "soc_device%d_ber_scanout.txt",diag_serdes_device_num);
213 file_ber_scan = fopen(filename_ber_scan, "w");
214
215 sprintf(filename_ber_scan, "soc_device%d_ber_scanout.txt",diag_serdes_device_num);
216 printf("\n\nSaving results to file: %s\n\n", filename_ber_scan);
217
218
219 fprintf(file_ber_scan, "Sweep1, Sweep2, LnErs0, Bist_Valid0, Att0, Boost0, DFE Slicer, DFE Tap, DFE Comp, DLEV, Gain, DFE DLEVA, DFE DLEVB, DFE Tap, CDR0, PMA0, Testtime \n");
220 for (sweep1 = berParamsInit.sweepStart1; sweep1 <= berParamsInit.sweepEnd1; sweep1++)
221 {
222 for (sweep2 = berParamsInit.sweepStart2; sweep2 <= berParamsInit.sweepEnd2; sweep2++)
223 {
224 fprintf(file_ber_scan, "%u, %u, %u, %u, %u, %u, %d, %d, %d, %d, %d, %d, %d, %d, %u, %u, %lld\n",
225 sweepber.sweep1[count],
226 sweepber.sweep2[count],
227 sweepber.berlane0[count],
228 sweepber.bistValid0[count],
229 sweepber.att0[count],
230 sweepber.boost0[count],
231 sweepber.dfe1_0[count],
232 sweepber.dfe2_0[count],
233 sweepber.dfe3_0[count],
234 sweepber.dfe4_0[count],
235 sweepber.dfe5_0[count],
236 sweepber.cdfe1_0[count],
237 sweepber.cdfe2_0[count],
238 sweepber.cdfe3_0[count],
239 sweepber.cdr0[count],
240 sweepber.pma0[count],
241 sweepber.runTime[count]);
242
243 count++;
244 }
245 }
246
247 printf("BER Sweep Complete!\n");
248 return SERDES_DIAG_SETUP_OK;
249
250}
251
252SERDES_DIAG_STAT Serdes_Example_EYETest()
253{
254 uint32_t laneNum;
255 SERDES_DIAG_BER_INIT_T berParamsInit;
256 memset (&berParamsInit, 0, sizeof(berParamsInit));
257
258 berParamsInit.laneCtrlRate = SERDES_DIAG_TEST_LANE_RATE;
259 berParamsInit.phyType = SERDES_DIAG_TEST_PHY_TYPE;
260 berParamsInit.baseAddr = SERDES_DIAG_TEST_BASE_ADDR;
261 berParamsInit.numLanes = SERDES_DIAG_TEST_NUM_LANES;
262 berParamsInit.laneMask = SERDES_DIAG_TEST_LANE_MASK;
263 berParamsInit.bertesttime = 2000000; //Equivalent to 10ms
264 berParamsInit.timeoutLoops = 1000000;
265 berParamsInit.prbsPattern = SERDES_DIAG_TEST_PRBS_PATTERN;
266 berParamsInit.forceAttBoost = SERDES_DIAG_TEST_FORCEATTBOOST;
267 berParamsInit.sweepTxRx = SERDES_DIAG_TEST_SWEEPTXRX;
268 berParamsInit.loopbackType = SERDES_DIAG_TEST_LOOPBACK_MODE;
269 berParamsInit.bistTxMode = SERDES_DIAG_TX_MODE_CONTINUOUS;
270 berParamsInit.pcieGenType = SERDES_DIAG_TEST_PCIE_GEN_TYPE;
271
272 if(berParamsInit.forceAttBoost)
273 {
274 berParamsInit.forceAttVal = 4;
275 berParamsInit.forceBoostVal = 5;
276 }
277
278 berParamsInit.bistTxClkEn = SERDES_DIAG_BIST_TX_CLK_ENABLED;
279 berParamsInit.bistRxClkEn = SERDES_DIAG_BIST_RX_CLK_ENABLED;
280
281#if (serdes_diag_test_phyType == TEST_SERDES_PCIe)
282 berParamsInit.pcieGenType = SERDES_DIAG_TEST_PCIE_GEN_TYPE;
283#endif
284
285 printf("Setting Lane Ctrl Overrides \n");
286 for(laneNum = 0; laneNum < berParamsInit.numLanes; laneNum++)
287 {
288 if ((berParamsInit.laneMask & (1<<laneNum))!=0)
289 {
290 if(berParamsInit.phyType == CSL_SERDES_PHY_TYPE_PCIe)
291 {
292 Serdes_Diag_PCIeCtrlOverride(&berParamsInit);
293 }
294 else if(berParamsInit.phyType == CSL_SERDES_PHY_TYPE_USB)
295 {
296 Serdes_Diag_USBCtrlOverride(&berParamsInit);
297 }
298 else if(berParamsInit.phyType == CSL_SERDES_PHY_TYPE_SGMII)
299 {
300 Serdes_Diag_SGMIICtrlOverride(&berParamsInit);
301 }
302 }
303 }
304
305
306
307 Serdes_Diag_BERTestTX(&berParamsInit);
308
309 //Then setup RX and measure EYE
310 Serdes_Diag_EYETest(&berParamsInit,0,2,4);
311
312 printf("On Chip Eye Measurement Complete\n");
313 return SERDES_DIAG_SETUP_OK;
314
315}
316
diff --git a/test/am65xx/serdes_diag_test_init.c b/test/am65xx/serdes_diag_test_init.c
new file mode 100644
index 0000000..696e250
--- /dev/null
+++ b/test/am65xx/serdes_diag_test_init.c
@@ -0,0 +1,237 @@
1/*
2 *
3 * Copyright (C) 2015 Texas Instruments Incorporated - http://www.ti.com/
4 *
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:
9 *
10 * Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 *
13 * Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the
16 * distribution.
17 *
18 * Neither the name of Texas Instruments Incorporated nor the names of
19 * its contributors may be used to endorse or promote products derived
20 * from this software without specific prior written permission.
21 *
22 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
23 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
24 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
25 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
26 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
27 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
28 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
29 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
30 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
32 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 *
34*/
35
36/*
37 * This file contains the prototypes for functions that interface with
38 * Serdes Diag APIs. They are common among all tests/examples.
39 */
40
41#include <ti/csl/soc.h>
42#include <ti/csl/csl_serdes.h>
43#include <ti/csl/cslr_device.h>
44#include <ti/csl/csl_serdes_pcie.h>
45#include <ti/csl/csl_serdes_usb.h>
46#include <ti/csl/csl_serdes_ethernet.h>
47#include <ti/csl/cslr_pcie.h>
48#include "serdes_diag_test.h"
49#include "serdes_diag_platform.h"
50#include "stdlib.h"
51
52#define KICK0 0x68EF3490ull
53#define KICK1 0xD172BC5Aull
54
55void serdes_diag_test_init()
56{
57
58 CSL_SerdesResult status;
59 uint32_t i;
60 CSL_SerdesLaneEnableParams serdesLaneEnableParams;
61 CSL_SerdesLaneEnableStatus laneRetVal = CSL_SERDES_LANE_ENABLE_NO_ERR;
62
63 memset(&serdesLaneEnableParams, 0, sizeof(serdesLaneEnableParams));
64
65 CSL_serdesPorReset(SERDES_DIAG_TEST_BASE_ADDR);
66
67
68 /* Serdes Input Sel details found in Maxwell IP Integration Spec Serdes Signal Connections
69 *
70 SERDES0.sys_lane0_ip_sel[1:0]
71 Input that selects which IP input is muxed into serdes output lane
72 00 : USB
73 01 : PCIE0 L0
74 10 : ICSS2 L0
75 11 : Reserved
76 MAIN_CTRL_MMR.SERDES0_CTRL.LANE_FUNC_SEL
77
78 SERDES1.sys_lane0_ip_sel[1:0]
79 Input that selects which IP input is muxed into serdes
80 output lane
81 00 : PCIE1 L0
82 01 : PCIE0 L1
83 10 : ICSS2 L1
84 11 : Reserved
85 MAIN_CTRL_MMR.SERDES1_CTRL.LANE_FUNC_SEL
86
87 Before writing to ip_sel, the main ctrl mmr kick registers need to be unlocked. lock1_kick0 and lock1_kick1 need to be unlocked.
88 lock1_kick0 is at 0x100000 + 0x5008 = 0x68EF3490
89 lock1_kick1 is at 0x100000 + 0x500c = 0xD172BC5A
90 Reading bit 0 of these registers will give the lock status. if it is 1, then it is unlocked for the MMR to be writable
91 */
92
93 /* This application code assumes that PSC is enabled for the serdes */
94
95 /* Unlock Lock1 Kick Registers */
96 *(volatile uint64_t *)(CSL_CTRL_MMR0_CFG0_BASE + CSL_MAIN_CTRL_MMR_CFG0_LOCK1_KICK0) = KICK0;
97 *(volatile uint64_t *)(CSL_CTRL_MMR0_CFG0_BASE + CSL_MAIN_CTRL_MMR_CFG0_LOCK1_KICK1) = KICK1;
98
99 /* Unlock Lock2 Kick Registers */
100 *(volatile uint32_t *)(CSL_CTRL_MMR0_CFG0_BASE + CSL_MAIN_CTRL_MMR_CFG0_LOCK2_KICK0) = KICK0;
101 *(volatile uint32_t *)(CSL_CTRL_MMR0_CFG0_BASE + CSL_MAIN_CTRL_MMR_CFG0_LOCK2_KICK1) = KICK1;
102
103 /* Select lane_func_sel based on the serdes type */
104#if (serdes_diag_test_phy_type == TEST_SERDES_USB)
105 CSL_FINSR(*(volatile uint32_t *)(CSL_CTRL_MMR0_CFG0_BASE + CSL_MAIN_CTRL_MMR_CFG0_SERDES0_CTRL),1,0,0x0);
106#elif (serdes_diag_test_phy_type == TEST_SERDES_PCIe)
107 CSL_FINSR(*(volatile uint32_t *)(CSL_CTRL_MMR0_CFG0_BASE + CSL_MAIN_CTRL_MMR_CFG0_SERDES0_CTRL),1,0,0x1);
108#elif (serdes_diag_test_phy_type == TEST_SERDES_SGMII)
109 CSL_FINSR(*(volatile uint32_t *)(CSL_CTRL_MMR0_CFG0_BASE + CSL_MAIN_CTRL_MMR_CFG0_SERDES0_CTRL),1,0,0x2);
110#endif
111
112/* Select Left CML clock for serdes0 and Right CML clock for serdes1 */
113#if (SERDES_DIAG_TEST_BASE_ADDR == CSL_SERDES0_BASE)
114 CSL_FINSR(*(volatile uint32_t *)(CSL_CTRL_MMR0_CFG0_BASE + CSL_MAIN_CTRL_MMR_CFG0_SERDES0_CTRL),7,4,0x4);
115 CSL_FINSR(*(volatile uint32_t *)(CSL_CTRL_MMR0_CFG0_BASE + CSL_MAIN_CTRL_MMR_CFG0_SERDES0_REFCLK_SEL),1,0,0x2);
116#elif (SERDES_DIAG_TEST_BASE_ADDR == CSL_SERDES1_BASE)
117 CSL_FINSR(*(volatile uint32_t *)(CSL_CTRL_MMR0_CFG0_BASE + CSL_MAIN_CTRL_MMR_CFG0_SERDES1_CTRL),7,4,0x1);
118 CSL_FINSR(*(volatile uint32_t *)(CSL_CTRL_MMR0_CFG0_BASE + CSL_MAIN_CTRL_MMR_CFG0_SERDES1_REFCLK_SEL),1,0,0x2);
119#endif
120
121 /* Set the serdes0 refclk input select register to main_pll_clkout */
122 /* Make sure that main_pll_clkout is the right clk for PCIe/USB/SGMII */
123 CSL_FINSR(*(volatile uint32_t *)(CSL_CTRL_MMR0_CFG0_BASE + CSL_MAIN_CTRL_MMR_CFG0_SERDES0_REFCLK_SEL),1,0,0x2);
124
125 serdesLaneEnableParams.baseAddr = SERDES_DIAG_TEST_BASE_ADDR;
126 serdesLaneEnableParams.refClock = SERDES_DIAG_TEST_REF_CLOCK;
127 serdesLaneEnableParams.linkRate = SERDES_DIAG_TEST_LINK_RATE;
128 serdesLaneEnableParams.numLanes = SERDES_DIAG_TEST_NUM_LANES;
129 serdesLaneEnableParams.laneMask = SERDES_DIAG_TEST_LANE_MASK;
130 serdesLaneEnableParams.phyType = SERDES_DIAG_TEST_PHY_TYPE;
131 serdesLaneEnableParams.operatingMode = SERDES_DIAG_TEST_OPERATING_MODE;
132 for(i=0; i< serdesLaneEnableParams.numLanes; i++)
133 {
134 serdesLaneEnableParams.laneCtrlRate[i] = SERDES_DIAG_TEST_LANE_RATE;
135 serdesLaneEnableParams.loopbackMode[i] = SERDES_DIAG_TEST_LOOPBACK_MODE;
136 }
137
138 if(serdes_diag_test_phy_type == TEST_SERDES_PCIe)
139 {
140#ifdef QT
141 /* QT Patch for Gen3 */
142 CSL_FINSR(*(volatile uint32_t *)(SERDES_DIAG_TEST_BASE_ADDR + 0x248), 31, 0, 0x500);
143 CSL_FINSR(*(volatile uint32_t *)(SERDES_DIAG_TEST_BASE_ADDR + 0x1400), 31, 0, 0x8800003E);
144 CSL_FINSR(*(volatile uint32_t *)(SERDES_DIAG_TEST_BASE_ADDR + 0x1ffc), 31, 0, 0x05000014);
145#endif
146 }
147
148 /*Load the Serdes Config File */
149#if (serdes_diag_test_phy_type == TEST_SERDES_SGMII)
150 status = CSL_serdesEthernetInit(serdesLaneEnableParams.baseAddr,
151 serdesLaneEnableParams.numLanes,
152 serdesLaneEnableParams.refClock,
153 serdesLaneEnableParams.linkRate); //Use this for SGMII serdes config load
154#elif (serdes_diag_test_phy_type == TEST_SERDES_PCIe)
155 status = CSL_serdesPCIeInit(serdesLaneEnableParams.baseAddr,
156 serdesLaneEnableParams.numLanes,
157 serdesLaneEnableParams.refClock,
158 serdesLaneEnableParams.linkRate); //Use this for PCIe serdes config load
159#elif (serdes_diag_test_phy_type == TEST_SERDES_USB)
160 status = CSL_serdesUSBInit(serdesLaneEnableParams.baseAddr,
161 serdesLaneEnableParams.numLanes,
162 serdesLaneEnableParams.refClock,
163 serdesLaneEnableParams.linkRate); //Use this for PCIe serdes config load
164#endif
165
166 /* Return error if input params are invalid */
167 if (status != CSL_SERDES_NO_ERR)
168 {
169 if(serdes_diag_test_phy_type == TEST_SERDES_SGMII)
170 {
171 printf("\nInvalid SGMII SERDES Init Params \n");
172 }
173 if(serdes_diag_test_phy_type == TEST_SERDES_USB)
174 {
175 printf("\nInvalid USB SERDES Init Params \n");
176 }
177 if(serdes_diag_test_phy_type == TEST_SERDES_PCIe)
178 {
179 printf("\nInvalid PCIe SERDES Init Params \n");
180 }
181 }
182 else
183 {
184 if(serdes_diag_test_phy_type == TEST_SERDES_SGMII)
185 {
186 printf("\nSGMII SERDES Config Load Complete \n");
187 }
188 if(serdes_diag_test_phy_type == TEST_SERDES_USB)
189 {
190 printf("\nUSB SERDES Config Load Complete \n");
191 }
192 if(serdes_diag_test_phy_type == TEST_SERDES_PCIe)
193 {
194 printf("\nPCIe SERDES Config Load Complete \n");
195 }
196 }
197
198 /* Common Lane Enable API for lane enable, pll enable etc */
199 laneRetVal = CSL_serdesLaneEnable(&serdesLaneEnableParams);
200
201 if (laneRetVal != 0)
202 {
203 if(serdes_diag_test_phy_type == TEST_SERDES_SGMII)
204 {
205 printf("\nInvalid SGMII Lane Enable \n");
206 }
207 if(serdes_diag_test_phy_type == TEST_SERDES_USB)
208 {
209 printf("\nInvalid USB Lane Enable \n");
210 }
211 if(serdes_diag_test_phy_type == TEST_SERDES_PCIe)
212 {
213 printf("\nInvalid PCIe Lane Enable \n");
214 }
215 }
216 else
217 {
218 if(serdes_diag_test_phy_type == TEST_SERDES_SGMII)
219 {
220 printf("SGMII Lane Enable Complete \n");
221 }
222 if(serdes_diag_test_phy_type == TEST_SERDES_USB)
223 {
224 printf("USB Lane Enable Complete \n");
225 }
226 if(serdes_diag_test_phy_type == TEST_SERDES_PCIe)
227 {
228 printf("PCIe Lane Enable Complete \n");
229 }
230 }
231
232 /* Check CMU_OK */
233 CSL_serdesWaitForCMUOK(serdesLaneEnableParams.baseAddr);
234
235 /* Wait 20us for phystatus before switching to Diag Mode */
236 CSL_serdesCycleDelay(20000);
237}
diff --git a/test/src/serdes_diag_test.h b/test/src/serdes_diag_test.h
index 7d494b3..fe6149d 100644
--- a/test/src/serdes_diag_test.h
+++ b/test/src/serdes_diag_test.h
@@ -33,7 +33,13 @@
33 * 33 *
34*/ 34*/
35#include <ti/csl/csl_serdes.h> 35#include <ti/csl/csl_serdes.h>
36#if defined (SOC_AM65XX)
37#include <ti/diag/serdes_diag/src/am65xx/serdes_diag_k3.h>
38#elif defined (SOC_J721E)
39#include <ti/diag/serdes_diag/src/j721e/serdes_diag_k3.h>
40#else
36#include <ti/diag/serdes_diag/serdes_diag.h> 41#include <ti/diag/serdes_diag/serdes_diag.h>
42#endif
37 43
38SERDES_DIAG_STAT Serdes_Example_BERTest(); 44SERDES_DIAG_STAT Serdes_Example_BERTest();
39SERDES_DIAG_STAT Serdes_Example_EYETest(); 45SERDES_DIAG_STAT Serdes_Example_EYETest();
diff --git a/test/src/serdes_diag_test_main.c b/test/src/serdes_diag_test_main.c
index 6ef38a7..2d50a5c 100644
--- a/test/src/serdes_diag_test_main.c
+++ b/test/src/serdes_diag_test_main.c
@@ -38,10 +38,14 @@
38 * Serdes Debug APIs. They are common among all tests/examples. 38 * Serdes Debug APIs. They are common among all tests/examples.
39 */ 39 */
40 40
41#include <ti/diag/serdes_diag/serdes_diag.h>
42#include <ti/csl/csl_serdes.h> 41#include <ti/csl/csl_serdes.h>
42#if defined (SOC_AM65XX)
43#include <ti/diag/serdes_diag/src/am65xx/serdes_diag_k3.h>
44#else
45#include <ti/diag/serdes_diag/serdes_diag.h>
43#include <ti/csl/csl_tsc.h> 46#include <ti/csl/csl_tsc.h>
44#include <ti/csl/csl_cacheAux.h> 47#include <ti/csl/csl_cacheAux.h>
48#endif
45#include "serdes_diag_test.h" 49#include "serdes_diag_test.h"
46#include "string.h" 50#include "string.h"
47 51
@@ -49,6 +53,7 @@ void main()
49{ 53{
50 SERDES_DIAG_STAT diag_stat; 54 SERDES_DIAG_STAT diag_stat;
51 55
56#if !defined (SOC_AM65XX)
52 /* Enable the TSC */ 57 /* Enable the TSC */
53 CSL_tscEnable(); 58 CSL_tscEnable();
54 59
@@ -57,6 +62,7 @@ void main()
57 CACHE_setL1DSize(CACHE_L1_0KCACHE); 62 CACHE_setL1DSize(CACHE_L1_0KCACHE);
58 printf("Turning off L2 Cache.\n"); 63 printf("Turning off L2 Cache.\n");
59 CACHE_setL2Size(CACHE_0KCACHE); 64 CACHE_setL2Size(CACHE_0KCACHE);
65#endif
60 66
61 /* serdes_diag_test_phy_type should be set in serdes_diag_platform.h */ 67 /* serdes_diag_test_phy_type should be set in serdes_diag_platform.h */
62 /* Initializes the peripheral based on the Platform(K2E/K2H/K2K/K2L) and phy type */ 68 /* Initializes the peripheral based on the Platform(K2E/K2H/K2K/K2L) and phy type */
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