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author | M V Pratap Reddy | 2018-09-04 15:10:29 -0500 |
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committer | M V Pratap Reddy | 2018-09-04 15:10:29 -0500 |
commit | d41f7d75842cfc2d83d2e09a8cb2fc3ae2597786 (patch) | |
tree | 04ffc24ec7d331259c0f28bd8342b26642ed2604 | |
parent | 5d76108d7b3e8a6cd07f77bf57bce3e4e0d6ae29 (diff) | |
parent | 92418bbeba868790e837c462ac4e5e1b83eda7ea (diff) | |
download | starterware-d41f7d75842cfc2d83d2e09a8cb2fc3ae2597786.tar.gz starterware-d41f7d75842cfc2d83d2e09a8cb2fc3ae2597786.tar.xz starterware-d41f7d75842cfc2d83d2e09a8cb2fc3ae2597786.zip |
Merge pull request #46 in PROCESSOR-SDK/starterware-procsdk from PRSDK-4449 to master
* commit '92418bbeba868790e837c462ac4e5e1b83eda7ea':
PRSDK-4449: Fixed Processor SDK Starterware QSPI clock setup issue on AM437x
-rw-r--r-- | dal/qspi.c | 8 |
1 files changed, 8 insertions, 0 deletions
@@ -87,8 +87,16 @@ void QSPISetPreScaler(uint32_t baseAddr, uint32_t clkDividerVal) | |||
87 | /* wait for QSPI to be idle */ | 87 | /* wait for QSPI to be idle */ |
88 | while (TRUE == QSPIIsBusy(baseAddr)); | 88 | while (TRUE == QSPIIsBusy(baseAddr)); |
89 | 89 | ||
90 | /* turn off QSPI data clock */ | ||
91 | HW_SET_FIELD(regVal, QSPI_CLOCK_CNTRL_REG_CLKEN, | ||
92 | QSPI_CLOCK_CNTRL_REG_CLKEN_DCLOCK_OFF); | ||
93 | /* Set the value of QSPI clock control register */ | ||
94 | HW_WR_REG32(baseAddr + QSPI_CLOCK_CNTRL_REG, regVal); | ||
95 | |||
90 | /* Set the QSPI clock divider bit field value*/ | 96 | /* Set the QSPI clock divider bit field value*/ |
91 | HW_SET_FIELD(regVal, QSPI_CLOCK_CNTRL_REG_DCLK_DIV, clkDividerVal); | 97 | HW_SET_FIELD(regVal, QSPI_CLOCK_CNTRL_REG_DCLK_DIV, clkDividerVal); |
98 | /* Set the value of QSPI clock control register */ | ||
99 | HW_WR_REG32(baseAddr + QSPI_CLOCK_CNTRL_REG, regVal); | ||
92 | 100 | ||
93 | /* Enable the QSPI data clock */ | 101 | /* Enable the QSPI data clock */ |
94 | HW_SET_FIELD(regVal, QSPI_CLOCK_CNTRL_REG_CLKEN, | 102 | HW_SET_FIELD(regVal, QSPI_CLOCK_CNTRL_REG_CLKEN, |