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authorThanh Tran2019-07-09 19:40:58 -0500
committerThanh Tran2019-07-09 19:40:58 -0500
commit29645d482fffc3e8e0011d8290e4c160cd893cd9 (patch)
tree27f324dfcf24fec7170565225dc3f874a16ef89b
parent2a90c39be49f2732b3ca08b322c51d0a977ea510 (diff)
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Enable compliance state early during USB host init
Currently USB host doesn't get to compliance mode if USB probe is connected to USB port before the controller is starting up. Move the code that enable compliance mode to right after the controller is set to host mode and after we poll for the PR bit to go low
-rw-r--r--build/makefile.mk3
-rw-r--r--src/dwc/usb_xhci_hcd.c74
2 files changed, 69 insertions, 8 deletions
diff --git a/build/makefile.mk b/build/makefile.mk
index 0f4c4c0..20132a6 100644
--- a/build/makefile.mk
+++ b/build/makefile.mk
@@ -81,7 +81,8 @@ endif
81 81
82ifeq ($(BUILD_PROFILE),debug) 82ifeq ($(BUILD_PROFILE),debug)
83ifeq ($(SOC),$(filter $(SOC), am65xx)) 83ifeq ($(SOC),$(filter $(SOC), am65xx))
84#CFLAGS_LOCAL_COMMON += -DUSB3_DEBUG 84#CFLAGS_LOCAL_COMMON += -DUSB3_DEBUG #this flag enable USB3.0 debug
85#CFLAGS_LOCAL_COMMON += -DPRINT_COMPLIANCE_STATUS #this flag makes the code wait for USB port to get to compliance state
85endif 86endif
86endif 87endif
87 88
diff --git a/src/dwc/usb_xhci_hcd.c b/src/dwc/usb_xhci_hcd.c
index e210f35..c98c2f7 100644
--- a/src/dwc/usb_xhci_hcd.c
+++ b/src/dwc/usb_xhci_hcd.c
@@ -339,15 +339,42 @@ void enableComplianceMode(uint32_t instanceNumber)
339 uint32_t regVal = 0; 339 uint32_t regVal = 0;
340 const USB_Config* usbConfig = &USB_config[instanceNumber]; 340 const USB_Config* usbConfig = &USB_config[instanceNumber];
341 uint32_t baseAddr = 0; 341 uint32_t baseAddr = 0;
342 uint32_t PP = 0, CCS=0, PED=0, PR=0, PLS=0;
342 343
343 baseAddr = XhciRegBaseAddr(instanceNumber); 344 baseAddr = XhciRegBaseAddr(instanceNumber);
344 345
345 if ((instanceNumber == 0) && /* only port #0 supports SS */ 346 if ((instanceNumber == 0) && /* only port #0 supports SS */
346 (usbConfig->usb30Enabled == TRUE) /* SOC support */) 347 (usbConfig->usb30Enabled == TRUE) /* SOC support */)
347 { 348 {
349
350 while (1)
351 {
352 regVal = HW_RD_REG32(baseAddr + DWC_USB_PORTSC2);
353 PR = HW_GET_FIELD(regVal, DWC_USB_PORTSC2_PR);
354 if (PR == 0) break;
355 }
356
348 /* attempt to turn on compliance mode */ 357 /* attempt to turn on compliance mode */
349 debug_printf("Enable compliance mode\n"); 358 debug_printf("Enable compliance mode\n");
350 359
360 /* CTE can only be set to 1 if port is in disconnected state and with PLS = RX_detect*/
361 debug_printf("checking to see if we are in disconnected state\n");
362 regVal = HW_RD_REG32(baseAddr + DWC_USB_PORTSC2);
363
364 PP = HW_GET_FIELD(regVal, DWC_USB_PORTSC2_PP);
365 CCS = HW_GET_FIELD(regVal, DWC_USB_PORTSC2_CCS);
366 PED = HW_GET_FIELD(regVal, DWC_USB_PORTSC2_PED);
367 PR = HW_GET_FIELD(regVal, DWC_USB_PORTSC2_PR);
368 PLS = HW_GET_FIELD(regVal, DWC_USB_PORTSC2_PLS);
369
370 debug_printf("PORTSC2 = 0x%x. PP=%d. CCS=%d. PED=%d. PR=%d. PLS=%d\n",
371 regVal, PP,CCS, PED, PR, PLS);
372
373 if ((PP != 1)|| (CCS!=0) || (PED!=0) || (PR!=0) )
374 {
375 debug_printf("Port is not in disconnected state while trying to enable CTE\n");
376 }
377
351 regVal = 0; 378 regVal = 0;
352 HW_SET_FIELD(regVal, DWC_USB_PORTSC2_PP, 0x1); /* PP = 1 */ 379 HW_SET_FIELD(regVal, DWC_USB_PORTSC2_PP, 0x1); /* PP = 1 */
353 HW_WR_REG32(baseAddr + DWC_USB_PORTSC2, regVal); /* write PP to PORTSC */ 380 HW_WR_REG32(baseAddr + DWC_USB_PORTSC2, regVal); /* write PP to PORTSC */
@@ -363,6 +390,40 @@ void enableComplianceMode(uint32_t instanceNumber)
363 390
364 HW_SET_FIELD(regVal, DWC_USB_PORTSC2_LWS, 0x0); /* LWS = 0 */ 391 HW_SET_FIELD(regVal, DWC_USB_PORTSC2_LWS, 0x0); /* LWS = 0 */
365 HW_WR_REG32(baseAddr + DWC_USB_PORTSC2, regVal); /* write it again */ 392 HW_WR_REG32(baseAddr + DWC_USB_PORTSC2, regVal); /* write it again */
393
394#if defined(PRINT_COMPLIANCE_STATUS)
395 uint32_t timeOut = 0;
396
397 /* if required, print to console if we get to compliance state or not
398 * for operational confirmation. But we don't want this to interfere
399 * with normal usual operation since this operation delays the code
400 * execution a bit which might not be always desired. */
401 debug_printf("checking to see if we are in compliance state\n");
402
403 while(1)
404 {
405 regVal = HW_RD_REG32(baseAddr + DWC_USB_PORTSC2);
406
407 PLS = HW_GET_FIELD(regVal, DWC_USB_PORTSC2_PLS);
408
409 if (PLS == 10)
410 {
411 debug_printf("PORTSC2 = 0x%x. PLS=%d. Port is in compliance state\n", regVal, PLS);
412 break;
413 }
414
415 usb_osalDelayMs(100);
416 timeOut++;
417
418 if (timeOut > 10) /* wait for 1.1 second */
419 {
420 debug_printf("Time out while waiting for compliance state. PORTSC2 = 0x%x. PLS=%d\n",
421 regVal, PLS);
422
423 break;
424 }
425 }
426#endif
366 } 427 }
367} 428}
368 429
@@ -440,7 +501,6 @@ void USB_Host_Init(uint32_t instanceNumber)
440 /* wait for Controller Not Ready to go 0 */ 501 /* wait for Controller Not Ready to go 0 */
441 while(HW_RD_FIELD32(baseAddr + DWC_USB_USBSTS, DWC_USB_USBSTS_CNR)); 502 while(HW_RD_FIELD32(baseAddr + DWC_USB_USBSTS, DWC_USB_USBSTS_CNR));
442 503
443
444 /*Setting the DWC3 controller for Host mode operation */ 504 /*Setting the DWC3 controller for Host mode operation */
445 regVal = HW_RD_REG32(baseAddr + DWC_USB_GCTL); 505 regVal = HW_RD_REG32(baseAddr + DWC_USB_GCTL);
446 regVal &= ~(3 << DWC_USB_GCTL_PRTCAPDIR_SHIFT); /* prtcapdir clr - tt - This line seems crucial **** */ 506 regVal &= ~(3 << DWC_USB_GCTL_PRTCAPDIR_SHIFT); /* prtcapdir clr - tt - This line seems crucial **** */
@@ -448,6 +508,11 @@ void USB_Host_Init(uint32_t instanceNumber)
448 regVal |= (DWC_USB_GCTL_PRTCAPDIR_HST << DWC_USB_GCTL_PRTCAPDIR_SHIFT); 508 regVal |= (DWC_USB_GCTL_PRTCAPDIR_HST << DWC_USB_GCTL_PRTCAPDIR_SHIFT);
449 HW_WR_REG32(baseAddr + DWC_USB_GCTL, regVal ); 509 HW_WR_REG32(baseAddr + DWC_USB_GCTL, regVal );
450 510
511#ifdef SOC_AM65XX
512 /* xHCI v1.1 disable Compliance mode by default */
513 enableComplianceMode(instanceNumber);
514#endif
515
451 /* USB3.0 */ 516 /* USB3.0 */
452 /*regVal = HW_RD_REG32(baseAddr + DWC_USB_GUSB3PIPECTL); */ 517 /*regVal = HW_RD_REG32(baseAddr + DWC_USB_GUSB3PIPECTL); */
453 /*HW_WR_FIELD32(baseAddr + DWC_USB_GUSB3PIPECTL, DWC_USB_GUSB3PIPECTL_LFPSFILT, 1); */ 518 /*HW_WR_FIELD32(baseAddr + DWC_USB_GUSB3PIPECTL, DWC_USB_GUSB3PIPECTL_LFPSFILT, 1); */
@@ -517,7 +582,7 @@ void USB_Host_Init(uint32_t instanceNumber)
517 HW_WR_FIELD32(baseAddr + DWC_USB_IMAN(1), DWC_USB_IMAN_IE, DWC_USB_IMAN_IE_EN); 582 HW_WR_FIELD32(baseAddr + DWC_USB_IMAN(1), DWC_USB_IMAN_IE, DWC_USB_IMAN_IE_EN);
518 583
519 HW_WR_FIELD32(baseAddr + DWC_USB_USBCMD, DWC_USB_USBCMD_INTE, 0x01); 584 HW_WR_FIELD32(baseAddr + DWC_USB_USBCMD, DWC_USB_USBCMD_INTE, 0x01);
520 585
521 HW_WR_FIELD32(baseAddr + DWC_USB_USBCMD, DWC_USB_USBCMD_R_S, 0x01); 586 HW_WR_FIELD32(baseAddr + DWC_USB_USBCMD, DWC_USB_USBCMD_R_S, 0x01);
522 587
523#if DOING_SERDES_AFTER_CORE_INIT 588#if DOING_SERDES_AFTER_CORE_INIT
@@ -535,11 +600,6 @@ void USB_Host_Init(uint32_t instanceNumber)
535#endif 600#endif
536#endif 601#endif
537 602
538#ifdef SOC_AM65XX
539 /* xHCI v1.1 disable Compliance mode by default */
540 enableComplianceMode(instanceNumber);
541#endif
542
543#ifdef USB3_DEBUG 603#ifdef USB3_DEBUG
544 usb30Debug(); 604 usb30Debug();
545#endif 605#endif