diff options
author | Mahesh Radhakrishnan | 2019-06-25 17:23:22 -0500 |
---|---|---|
committer | Mahesh Radhakrishnan | 2019-06-25 17:23:22 -0500 |
commit | 48cc692ddf0f9cdae03698bacc1c3c995c24ee33 (patch) | |
tree | dffcd3bf6ba18fbef19735919367d486f0588c89 | |
parent | f13c4a1729a901e88b87b6eef4cda26c28d874f7 (diff) | |
parent | 458bc4ba27ae61bbf5debb5a297bdeaa26ce23ce (diff) | |
download | usb-48cc692ddf0f9cdae03698bacc1c3c995c24ee33.tar.gz usb-48cc692ddf0f9cdae03698bacc1c3c995c24ee33.tar.xz usb-48cc692ddf0f9cdae03698bacc1c3c995c24ee33.zip |
Merge pull request #116 in PROCESSOR-SDK/usb from PRSDK-5873_PRSDK-5867_move_DMSC_reserve to master
* commit '458bc4ba27ae61bbf5debb5a297bdeaa26ce23ce':
Move linker files with no-cache sections to USB example
Update USB examples with new linker files
-rw-r--r-- | example/bios/am65xx/r5_mpu.xs | 4 | ||||
-rw-r--r-- | example/bios/am65xx/usb_am65xx_evm.cfg | 6 | ||||
-rw-r--r-- | example/bios/biosMmu.c | 163 | ||||
-rwxr-xr-x | example/build/am65xx/linker_a53.lds | 196 | ||||
-rw-r--r-- | example/build/am65xx/linker_r5.lds | 137 | ||||
-rw-r--r-- | example/build/am65xx/linker_r5_sysbios.lds | 99 | ||||
-rw-r--r-- | example/build/usb_dev_bulk/makefile | 9 | ||||
-rw-r--r-- | example/build/usb_dev_msc/makefile | 21 | ||||
-rw-r--r-- | example/build/usb_host_msc/makefile | 20 | ||||
-rw-r--r-- | example/common/usb_arm_r5.asm | 4 |
10 files changed, 498 insertions, 161 deletions
diff --git a/example/bios/am65xx/r5_mpu.xs b/example/bios/am65xx/r5_mpu.xs index c7de406..e73fa80 100644 --- a/example/bios/am65xx/r5_mpu.xs +++ b/example/bios/am65xx/r5_mpu.xs | |||
@@ -123,7 +123,7 @@ attrs.tex = 1; | |||
123 | attrs.subregionDisableMask = 0; | 123 | attrs.subregionDisableMask = 0; |
124 | MPU.setRegionMeta(5, 0x70000000, MPU.RegionSize_2M, attrs); | 124 | MPU.setRegionMeta(5, 0x70000000, MPU.RegionSize_2M, attrs); |
125 | 125 | ||
126 | /* make 0x701F2000 non-cache */ | 126 | /* make 0x701E2000 non-cache - Please check with linker file in ti/build */ |
127 | attrs.enable = true; | 127 | attrs.enable = true; |
128 | attrs.bufferable = false; | 128 | attrs.bufferable = false; |
129 | attrs.cacheable = false; | 129 | attrs.cacheable = false; |
@@ -132,5 +132,5 @@ attrs.noExecute = false; | |||
132 | attrs.accPerm = 1; /* RW at PL1 */ | 132 | attrs.accPerm = 1; /* RW at PL1 */ |
133 | attrs.tex = 1; | 133 | attrs.tex = 1; |
134 | attrs.subregionDisableMask = 0x80; /* mask first 0x2000 */ | 134 | attrs.subregionDisableMask = 0x80; /* mask first 0x2000 */ |
135 | MPU.setRegionMeta(6, 0x701F0000, MPU.RegionSize_64K, attrs); /* last 56k of MSMC effectively */ | 135 | MPU.setRegionMeta(6, 0x701E0000, MPU.RegionSize_64K, attrs); /* 56k of MSMC effectively */ |
136 | 136 | ||
diff --git a/example/bios/am65xx/usb_am65xx_evm.cfg b/example/bios/am65xx/usb_am65xx_evm.cfg index 2ebc0b0..d14f568 100644 --- a/example/bios/am65xx/usb_am65xx_evm.cfg +++ b/example/bios/am65xx/usb_am65xx_evm.cfg | |||
@@ -160,12 +160,9 @@ if (java.lang.String(Program.build.target.suffix).contains('a53')) | |||
160 | 160 | ||
161 | 161 | ||
162 | /* ================ Memory sections configuration ================ */ | 162 | /* ================ Memory sections configuration ================ */ |
163 | //Program.sectMap[".bss:extMemNonCache:usbXhci"] = "APP_UNCACHED_DATA_BLK3_MEM"; | ||
164 | Program.sectMap[".bss:extMemNonCache:usbXhci"] = "MSMC_SRAM_H_NOCACHE"; | 163 | Program.sectMap[".bss:extMemNonCache:usbXhci"] = "MSMC_SRAM_H_NOCACHE"; |
165 | Program.sectMap[".bss:extMemCache:ramdisk"] = new Program.SectionSpec(); | 164 | Program.sectMap[".bss:extMemCache:ramdisk"] = new Program.SectionSpec(); |
166 | //Program.sectMap[".bss:extMemCache:ramdisk"].loadSegment = "APP_CACHED_DATA_BLK2_MEM"; | ||
167 | Program.sectMap[".bss:extMemCache:ramdisk"].loadSegment = "DDR_0"; | 165 | Program.sectMap[".bss:extMemCache:ramdisk"].loadSegment = "DDR_0"; |
168 | //Program.sectMap[".bss:extMemCache:ramdisk"].loadSegment = "MSMC_SRAM"; | ||
169 | Program.sectMap[".bss:extMemCache:ramdisk"].type = "NOLOAD"; | 166 | Program.sectMap[".bss:extMemCache:ramdisk"].type = "NOLOAD"; |
170 | } | 167 | } |
171 | else if (java.lang.String(Program.build.target.suffix).contains('r5')) | 168 | else if (java.lang.String(Program.build.target.suffix).contains('r5')) |
@@ -175,13 +172,10 @@ else if (java.lang.String(Program.build.target.suffix).contains('r5')) | |||
175 | 172 | ||
176 | xdc.loadCapsule("r5_mpu.xs"); | 173 | xdc.loadCapsule("r5_mpu.xs"); |
177 | 174 | ||
178 | |||
179 | /* ================ Memory sections configuration ================ */ | 175 | /* ================ Memory sections configuration ================ */ |
180 | //Program.sectMap[".bss:extMemNonCache:usbXhci"] = "APP_UNCACHED_DATA_BLK3_MEM"; | ||
181 | Program.sectMap[".bss:extMemNonCache:usbXhci"] = "MSMC3_NOCACHE"; | 176 | Program.sectMap[".bss:extMemNonCache:usbXhci"] = "MSMC3_NOCACHE"; |
182 | Program.sectMap[".bss:extMemCache:ramdisk"] = new Program.SectionSpec(); | 177 | Program.sectMap[".bss:extMemCache:ramdisk"] = new Program.SectionSpec(); |
183 | Program.sectMap[".bss:extMemCache:ramdisk"].loadSegment = "DDR0"; /* "APP_CACHED_DATA_BLK2_MEM" */ | 178 | Program.sectMap[".bss:extMemCache:ramdisk"].loadSegment = "DDR0"; /* "APP_CACHED_DATA_BLK2_MEM" */ |
184 | //Program.sectMap[".bss:extMemCache:ramdisk"].loadSegment = "MSMC3"; | ||
185 | Program.sectMap[".bss:extMemCache:ramdisk"].type = "NOLOAD"; | 179 | Program.sectMap[".bss:extMemCache:ramdisk"].type = "NOLOAD"; |
186 | 180 | ||
187 | } | 181 | } |
diff --git a/example/bios/biosMmu.c b/example/bios/biosMmu.c index 346cea4..8081d10 100644 --- a/example/bios/biosMmu.c +++ b/example/bios/biosMmu.c | |||
@@ -49,7 +49,6 @@ | |||
49 | #define MSMC_NON_CACHE_START_ADDR 0x701F2000 | 49 | #define MSMC_NON_CACHE_START_ADDR 0x701F2000 |
50 | #define MSMC_NON_CACHE_SIZE 0xe000 | 50 | #define MSMC_NON_CACHE_SIZE 0xe000 |
51 | 51 | ||
52 | |||
53 | void InitMmu(void) | 52 | void InitMmu(void) |
54 | { | 53 | { |
55 | Bool retVal; | 54 | Bool retVal; |
@@ -202,11 +201,12 @@ void InitMmu(void) | |||
202 | mapIdx++; | 201 | mapIdx++; |
203 | retVal = Mmu_map(0x04000000ul, 0x04000000ul, 0x00200000ul, &attrs); | 202 | retVal = Mmu_map(0x04000000ul, 0x04000000ul, 0x00200000ul, &attrs); |
204 | if (retVal == FALSE) | 203 | if (retVal == FALSE) |
205 | { | 204 | { |
206 | goto mmu_exit; | 205 | goto mmu_exit; |
207 | } | 206 | } |
208 | 207 | ||
209 | attrs.attrIndx = 4; | 208 | /* MSMC */ |
209 | attrs.attrIndx = 7; | ||
210 | mapIdx++; | 210 | mapIdx++; |
211 | retVal = Mmu_map(0x70000000, 0x70000000, 0x04000000, &attrs); /* msmc */ | 211 | retVal = Mmu_map(0x70000000, 0x70000000, 0x04000000, &attrs); /* msmc */ |
212 | if (retVal == FALSE) | 212 | if (retVal == FALSE) |
@@ -214,6 +214,16 @@ void InitMmu(void) | |||
214 | goto mmu_exit; | 214 | goto mmu_exit; |
215 | } | 215 | } |
216 | 216 | ||
217 | mapIdx++; | ||
218 | |||
219 | /* 56K msmc no cache. Check with linker file in ti/build/am65xx */ | ||
220 | attrs.attrIndx = 4; | ||
221 | retVal = Mmu_map(0x701E2000, 0x701E2000, 0xE000, &attrs); | ||
222 | if (retVal == FALSE) | ||
223 | { | ||
224 | goto mmu_exit; | ||
225 | } | ||
226 | |||
217 | /* DDR */ | 227 | /* DDR */ |
218 | attrs.attrIndx = 7; | 228 | attrs.attrIndx = 7; |
219 | mapIdx++; | 229 | mapIdx++; |
@@ -235,151 +245,6 @@ mmu_exit: | |||
235 | } | 245 | } |
236 | 246 | ||
237 | 247 | ||
238 | #if 0 | ||
239 | Void InitMmu() | ||
240 | { | ||
241 | Mmu_MapAttrs attrs; | ||
242 | Bool retVal; | ||
243 | uint32_t mapIdx = 0; | ||
244 | |||
245 | Mmu_initMapAttrs(&attrs); | ||
246 | |||
247 | attrs.attrIndx = 0; | ||
248 | retVal = Mmu_map(0x00100000, 0x00100000, 0x00900000, &attrs); /* Main MMR0 cfg */ | ||
249 | if(retVal == FALSE) | ||
250 | { | ||
251 | goto mmu_exit; | ||
252 | } | ||
253 | |||
254 | mapIdx++; | ||
255 | retVal = Mmu_map(0x00400000, 0x00400000, 0x00001000, &attrs); /* PSC0 */ | ||
256 | if(retVal == FALSE) | ||
257 | { | ||
258 | goto mmu_exit; | ||
259 | } | ||
260 | |||
261 | mapIdx++; | ||
262 | retVal = Mmu_map(0x01800000, 0x01800000, 0x00100000, &attrs); /* gicv3 */ | ||
263 | if(retVal == FALSE) | ||
264 | { | ||
265 | goto mmu_exit; | ||
266 | } | ||
267 | |||
268 | mapIdx++; | ||
269 | retVal = Mmu_map(0x02400000, 0x02400000, 0x000c0000, &attrs); /* dmtimer */ | ||
270 | if(retVal == FALSE) | ||
271 | { | ||
272 | goto mmu_exit; | ||
273 | } | ||
274 | |||
275 | mapIdx++; | ||
276 | retVal = Mmu_map(0x02800000, 0x02800000, 0x00040000, &attrs); /* uart */ | ||
277 | if(retVal == FALSE) | ||
278 | { | ||
279 | goto mmu_exit; | ||
280 | } | ||
281 | |||
282 | mapIdx++; | ||
283 | retVal = Mmu_map(0x02000000, 0x02000000, 0x00100000, &attrs); /* I2C */ | ||
284 | if(retVal == FALSE) | ||
285 | { | ||
286 | goto mmu_exit; | ||
287 | } | ||
288 | |||
289 | mapIdx++; | ||
290 | retVal = Mmu_map(0x02100000, 0x02100000, 0x00080000, &attrs); /* McSPI */ | ||
291 | if(retVal == FALSE) | ||
292 | { | ||
293 | goto mmu_exit; | ||
294 | } | ||
295 | |||
296 | mapIdx++; | ||
297 | retVal = Mmu_map(0x40f00000, 0x40f00000, 0x00020000, &attrs); /* MCU MMR0 CFG */ | ||
298 | if(retVal == FALSE) | ||
299 | { | ||
300 | goto mmu_exit; | ||
301 | } | ||
302 | |||
303 | mapIdx++; | ||
304 | retVal = Mmu_map(0x40d00000, 0x40d00000, 0x00002000, &attrs); /* PLL0 CFG */ | ||
305 | if(retVal == FALSE) | ||
306 | { | ||
307 | goto mmu_exit; | ||
308 | } | ||
309 | |||
310 | mapIdx++; | ||
311 | retVal = Mmu_map(0x43000000, 0x43000000, 0x00020000, &attrs); /* WKUP MMR0 cfg */ | ||
312 | if(retVal == FALSE) | ||
313 | { | ||
314 | goto mmu_exit; | ||
315 | } | ||
316 | |||
317 | mapIdx++; | ||
318 | retVal = Mmu_map(0x02C40000, 0x02C40000, 0x00100000, &attrs); /* pinmux ctrl */ | ||
319 | if(retVal == FALSE) | ||
320 | { | ||
321 | goto mmu_exit; | ||
322 | } | ||
323 | |||
324 | mapIdx++; | ||
325 | retVal = Mmu_map(0x2A430000, 0x2A430000, 0x00001000, &attrs); /* ctrcontrol0 */ | ||
326 | if(retVal == FALSE) | ||
327 | { | ||
328 | goto mmu_exit; | ||
329 | } | ||
330 | |||
331 | mapIdx++; | ||
332 | retVal = Mmu_map(0x30800000, 0x30800000, 0x0C000000, &attrs); /* navss */ | ||
333 | if(retVal == FALSE) | ||
334 | { | ||
335 | goto mmu_exit; | ||
336 | } | ||
337 | |||
338 | attrs.attrIndx = 7; | ||
339 | mapIdx++; | ||
340 | retVal = Mmu_map(0x80000000, 0x80000000, 0x03000000, &attrs); /* ddr */ | ||
341 | if(retVal == FALSE) | ||
342 | { | ||
343 | goto mmu_exit; | ||
344 | } | ||
345 | |||
346 | mapIdx++; | ||
347 | retVal = Mmu_map(0x42000000, 0x42000000, 0x00001000, &attrs); /* PSC WKUP*/ | ||
348 | if (retVal == FALSE) | ||
349 | { | ||
350 | |||
351 | goto mmu_exit; | ||
352 | } | ||
353 | |||
354 | mapIdx++; | ||
355 | //retVal = Mmu_map(0x70000000, 0x70000000, 0x04000000, &attrs); /* msmc */ | ||
356 | retVal = Mmu_map(0x70000000, 0x70000000, (0x00200000-MSMC_NON_CACHE_SIZE), &attrs); /* msmc */ | ||
357 | if(retVal == FALSE) | ||
358 | { | ||
359 | goto mmu_exit; | ||
360 | } | ||
361 | |||
362 | #if 0 | ||
363 | mapIdx++; | ||
364 | attrs.attrIndx = 4; /* MAIR4 : inner and outter are non-cachable memory | ||
365 | ti/bios_6_73_00_00_eng/docs/cdoc/ti/sysbios/family/arm/v8a/Mmu.html#.M.A.I.R0 */ | ||
366 | retVal = Mmu_map(MSMC_NON_CACHE_START_ADDR, MSMC_NON_CACHE_START_ADDR, | ||
367 | MSMC_NON_CACHE_SIZE, &attrs); /* msmc non-cache */ | ||
368 | if(retVal == FALSE) | ||
369 | { | ||
370 | goto mmu_exit; | ||
371 | } | ||
372 | #endif | ||
373 | mmu_exit: | ||
374 | if(retVal == FALSE) | ||
375 | { | ||
376 | System_printf("Mmu_map idx %d returned error %d", mapIdx, retVal); | ||
377 | while(1); | ||
378 | } | ||
379 | |||
380 | return; | ||
381 | } | ||
382 | #endif | ||
383 | #endif | 248 | #endif |
384 | 249 | ||
385 | 250 | ||
diff --git a/example/build/am65xx/linker_a53.lds b/example/build/am65xx/linker_a53.lds new file mode 100755 index 0000000..890d781 --- /dev/null +++ b/example/build/am65xx/linker_a53.lds | |||
@@ -0,0 +1,196 @@ | |||
1 | /* File: linker_a53.lds | ||
2 | * Semihosting supported gcc Linker script for AM65XX A53 for QT | ||
3 | * Purpose: single core A53 C app | ||
4 | */ | ||
5 | __STACK_SIZE = 0x10000; | ||
6 | __TI_STACK_SIZE = __STACK_SIZE; | ||
7 | |||
8 | MEMORY | ||
9 | { | ||
10 | MCU_RESVD : ORIGIN = 0x000041C00000, LENGTH = 0x00060000 /* MCUSS-OCMC RAM RESERVED FOR MCUSS & SOC Boot - 384KB */ | ||
11 | OCMCRAM : ORIGIN = 0x000041C60000, LENGTH = 0x00020000 /* MCUSS-OCMC RAM - 128KB */ | ||
12 | BOOTVECTOR : ORIGIN = 0x000070000100, LENGTH = 0x00001000 - 0x100 /* MSMC RAM INIT CODE (4 KB) */ | ||
13 | MSMC_SRAM : ORIGIN = 0x000070001000, LENGTH = 0xEF000 /* MSMC RAM GENERAL USE */ | ||
14 | MSMC_SRAM_H : ORIGIN = 0x000070100000, LENGTH = 0xE2000 /* MSMC RAM GENERAL USE - High memory */ | ||
15 | MSMC_SRAM_H_NOCACHE : ORIGIN = 0x0000701E2000, LENGTH = 0x0E000 /* MSMC RAM no cache */ | ||
16 | MSMC_DMSC : ORIGIN = 0x0000701F0000, LENGTH = 0x10000 /* Reserved for DMSC */ | ||
17 | |||
18 | DDR_0 (RWX) : ORIGIN = 0x80000000, LENGTH = 0x10000000 | ||
19 | DDR_1 (RWX) : ORIGIN = 0x90000000, LENGTH = 0x10000000 | ||
20 | DDR_2 (RWX) : ORIGIN = 0xA0000000, LENGTH = 0x60000000 | ||
21 | } | ||
22 | |||
23 | REGION_ALIAS("REGION_TEXT", MSMC_SRAM); | ||
24 | REGION_ALIAS("REGION_BSS", MSMC_SRAM); | ||
25 | REGION_ALIAS("REGION_DATA", MSMC_SRAM); | ||
26 | REGION_ALIAS("REGION_STACK", MSMC_SRAM); | ||
27 | REGION_ALIAS("REGION_HEAP", MSMC_SRAM); | ||
28 | REGION_ALIAS("REGION_ARM_EXIDX", MSMC_SRAM); | ||
29 | REGION_ALIAS("REGION_ARM_EXTAB", MSMC_SRAM); | ||
30 | REGION_ALIAS("REGION_TEXT_STARTUP", MSMC_SRAM); | ||
31 | REGION_ALIAS("REGION_DATA_BUFFER", DDR_0); | ||
32 | REGION_ALIAS("REGION_FAR", DDR_0); | ||
33 | |||
34 | SECTIONS { | ||
35 | |||
36 | .vecs : { | ||
37 | *(.vecs) | ||
38 | } > BOOTVECTOR AT> BOOTVECTOR | ||
39 | |||
40 | .text.csl_a53_startup : { | ||
41 | *(.text.csl_a53_startup) | ||
42 | *(.Entry) | ||
43 | } > REGION_TEXT_STARTUP AT> REGION_TEXT_STARTUP | ||
44 | |||
45 | .text : { | ||
46 | CREATE_OBJECT_SYMBOLS | ||
47 | *(.text) | ||
48 | *(.text.*) | ||
49 | . = ALIGN(0x8); | ||
50 | KEEP (*(.ctors)) | ||
51 | . = ALIGN(0x4); | ||
52 | KEEP (*(.dtors)) | ||
53 | . = ALIGN(0x8); | ||
54 | __init_array_start = .; | ||
55 | KEEP (*(.init_array*)) | ||
56 | __init_array_end = .; | ||
57 | *(.init) | ||
58 | *(.fini*) | ||
59 | } > REGION_TEXT AT> REGION_TEXT | ||
60 | |||
61 | PROVIDE (__etext = .); | ||
62 | PROVIDE (_etext = .); | ||
63 | PROVIDE (etext = .); | ||
64 | |||
65 | .rodata : { | ||
66 | *(.rodata) | ||
67 | *(.rodata*) | ||
68 | } > REGION_TEXT AT> REGION_TEXT | ||
69 | |||
70 | .data_buffer : ALIGN (8) { | ||
71 | __data_buffer_load__ = LOADADDR (.data_buffer); | ||
72 | __data_buffer_start__ = .; | ||
73 | *(.data_buffer) | ||
74 | *(.data_buffer*) | ||
75 | . = ALIGN (8); | ||
76 | __data_buffer_end__ = .; | ||
77 | } > REGION_DATA_BUFFER AT> REGION_DATA_BUFFER | ||
78 | |||
79 | .data : ALIGN (8) { | ||
80 | __data_load__ = LOADADDR (.data); | ||
81 | __data_start__ = .; | ||
82 | *(.data) | ||
83 | *(.data*) | ||
84 | . = ALIGN (8); | ||
85 | __data_end__ = .; | ||
86 | } > REGION_DATA AT> REGION_TEXT | ||
87 | |||
88 | .ARM.exidx : { | ||
89 | __exidx_start = .; | ||
90 | *(.ARM.exidx* .gnu.linkonce.armexidx.*) | ||
91 | __exidx_end = .; | ||
92 | } > REGION_ARM_EXIDX AT> REGION_ARM_EXIDX | ||
93 | |||
94 | .ARM.extab : { | ||
95 | *(.ARM.extab* .gnu.linkonce.armextab.*) | ||
96 | } > REGION_ARM_EXTAB AT> REGION_ARM_EXTAB | ||
97 | |||
98 | /* usb application ramdisk buffer */ | ||
99 | .bss:extMemCache:ramdisk (NOLOAD) : ALIGN (32) { | ||
100 | } > DDR_0 | ||
101 | |||
102 | /* For NDK packet memory, we need to map this sections before .bss*/ | ||
103 | .bss:NDK_PACKETMEM (NOLOAD) : ALIGN (128) {} > DDR_0 | ||
104 | .bss:NDK_MMBUFFER (NOLOAD) : ALIGN (128) {} > DDR_0 | ||
105 | |||
106 | /* USB or any other LLD buffer for benchmarking */ | ||
107 | .benchmark_buffer (NOLOAD) : ALIGN (32) { | ||
108 | } > DDR_0 | ||
109 | |||
110 | /* cal's application buffer */ | ||
111 | .bss:frameBuffer (NOLOAD) : ALIGN (32) { | ||
112 | } > DDR_0 | ||
113 | |||
114 | |||
115 | .bss : { | ||
116 | __bss_start__ = .; | ||
117 | *(.shbss) | ||
118 | *(.bss) | ||
119 | *(.bss.*) | ||
120 | . = ALIGN (8); | ||
121 | __bss_end__ = .; | ||
122 | . = ALIGN (8); | ||
123 | *(COMMON) | ||
124 | } > REGION_BSS AT> REGION_BSS | ||
125 | |||
126 | .far : { | ||
127 | __far_start__ = .; | ||
128 | *(.far) | ||
129 | *(.far:*) | ||
130 | *(.far.*) | ||
131 | . = ALIGN (8); | ||
132 | __far_end__ = .; | ||
133 | . = ALIGN (8); | ||
134 | } > REGION_FAR AT> REGION_FAR | ||
135 | |||
136 | .heap : { | ||
137 | __heap_start__ = .; | ||
138 | end = __heap_start__; | ||
139 | _end = end; | ||
140 | __end = end; | ||
141 | KEEP(*(.heap)) | ||
142 | __heap_end__ = .; | ||
143 | __HeapLimit = __heap_end__; | ||
144 | } > REGION_HEAP AT> REGION_HEAP | ||
145 | |||
146 | .stack (NOLOAD) : ALIGN(16) { | ||
147 | _stack = .; | ||
148 | __stack = .; | ||
149 | KEEP(*(.stack)) | ||
150 | } > REGION_STACK AT> REGION_STACK | ||
151 | |||
152 | __TI_STACK_BASE = __stack; | ||
153 | |||
154 | /* Stabs debugging sections. */ | ||
155 | .stab 0 : { *(.stab) } | ||
156 | .stabstr 0 : { *(.stabstr) } | ||
157 | .stab.excl 0 : { *(.stab.excl) } | ||
158 | .stab.exclstr 0 : { *(.stab.exclstr) } | ||
159 | .stab.index 0 : { *(.stab.index) } | ||
160 | .stab.indexstr 0 : { *(.stab.indexstr) } | ||
161 | .comment 0 : { *(.comment) } | ||
162 | /* | ||
163 | * DWARF debug sections. | ||
164 | * Symbols in the DWARF debugging sections are relative to the beginning | ||
165 | * of the section so we begin them at 0. | ||
166 | */ | ||
167 | /* DWARF 1 */ | ||
168 | .debug 0 : { *(.debug) } | ||
169 | .line 0 : { *(.line) } | ||
170 | /* GNU DWARF 1 extensions */ | ||
171 | .debug_srcinfo 0 : { *(.debug_srcinfo) } | ||
172 | .debug_sfnames 0 : { *(.debug_sfnames) } | ||
173 | /* DWARF 1.1 and DWARF 2 */ | ||
174 | .debug_aranges 0 : { *(.debug_aranges) } | ||
175 | .debug_pubnames 0 : { *(.debug_pubnames) } | ||
176 | /* DWARF 2 */ | ||
177 | .debug_info 0 : { *(.debug_info .gnu.linkonce.wi.*) } | ||
178 | .debug_abbrev 0 : { *(.debug_abbrev) } | ||
179 | .debug_line 0 : { *(.debug_line .debug_line.* .debug_line_end ) } | ||
180 | .debug_frame 0 : { *(.debug_frame) } | ||
181 | .debug_str 0 : { *(.debug_str) } | ||
182 | .debug_loc 0 : { *(.debug_loc) } | ||
183 | .debug_macinfo 0 : { *(.debug_macinfo) } | ||
184 | /* SGI/MIPS DWARF 2 extensions */ | ||
185 | .debug_weaknames 0 : { *(.debug_weaknames) } | ||
186 | .debug_funcnames 0 : { *(.debug_funcnames) } | ||
187 | .debug_typenames 0 : { *(.debug_typenames) } | ||
188 | .debug_varnames 0 : { *(.debug_varnames) } | ||
189 | /* DWARF 3 */ | ||
190 | .debug_pubtypes 0 : { *(.debug_pubtypes) } | ||
191 | .debug_ranges 0 : { *(.debug_ranges) } | ||
192 | /* DWARF Extension. */ | ||
193 | .debug_macro 0 : { *(.debug_macro) } | ||
194 | .note.gnu.arm.ident 0 : { KEEP (*(.note.gnu.arm.ident)) } | ||
195 | /DISCARD/ : { *(.note.GNU-stack) *(.gnu_debuglink) *(.gnu.lto_*) } | ||
196 | } | ||
diff --git a/example/build/am65xx/linker_r5.lds b/example/build/am65xx/linker_r5.lds new file mode 100644 index 0000000..57a3df5 --- /dev/null +++ b/example/build/am65xx/linker_r5.lds | |||
@@ -0,0 +1,137 @@ | |||
1 | /*----------------------------------------------------------------------------*/ | ||
2 | /* File: k3m4_r5f_linker.cmd */ | ||
3 | /* Description: */ | ||
4 | /* Link command file for AM65XX M4 MCU 0 view */ | ||
5 | /* TI ARM Compiler version 15.12.3 LTS or later */ | ||
6 | /* */ | ||
7 | /* Platform: QT */ | ||
8 | /* (c) Texas Instruments 2017, All rights reserved. */ | ||
9 | /*----------------------------------------------------------------------------*/ | ||
10 | /* History: *' | ||
11 | /* Aug 26th, 2016 Original version .......................... Loc Truong */ | ||
12 | /* Aug 01th, 2017 new TCM mem map .......................... Loc Truong */ | ||
13 | /* Nov 07th, 2017 Changes for R5F Init Code.................. Vivek Dhande */ | ||
14 | /*----------------------------------------------------------------------------*/ | ||
15 | /* Linker Settings */ | ||
16 | /* Standard linker options */ | ||
17 | --retain="*(.intvecs)" | ||
18 | --retain="*(.intc_text)" | ||
19 | --retain="*(.rstvectors)" | ||
20 | --retain="*(.irqStack)" | ||
21 | --retain="*(.fiqStack)" | ||
22 | --retain="*(.abortStack)" | ||
23 | --retain="*(.undStack)" | ||
24 | --retain="*(.svcStack)" | ||
25 | --fill_value=0 | ||
26 | --stack_size=0x2000 | ||
27 | --heap_size=0x1000 | ||
28 | --entry_point=_resetvectors /* Default C RTS boot.asm */ | ||
29 | |||
30 | -stack 0x2000 /* SOFTWARE STACK SIZE */ | ||
31 | -heap 0x2000 /* HEAP AREA SIZE */ | ||
32 | |||
33 | /* Stack Sizes for various modes */ | ||
34 | __IRQ_STACK_SIZE = 0x1000; | ||
35 | __FIQ_STACK_SIZE = 0x1000; | ||
36 | __ABORT_STACK_SIZE = 0x1000; | ||
37 | __UND_STACK_SIZE = 0x1000; | ||
38 | __SVC_STACK_SIZE = 0x1000; | ||
39 | |||
40 | /*----------------------------------------------------------------------------*/ | ||
41 | /* Memory Map */ | ||
42 | MEMORY | ||
43 | { | ||
44 | VECTORS (X) : origin=0x41C7F000 length=0x1000 | ||
45 | /* Reset Vectors base address(RESET_VECTORS) should be 64 bytes aligned */ | ||
46 | RESET_VECTORS (X) : origin=0x41C00000 length=0x100 | ||
47 | /* MCU0_R5F_0 local view */ | ||
48 | MCU0_R5F_TCMA_SBL_RSVD (X) : origin=0x0 length=0x100 | ||
49 | MCU0_R5F_TCMA (X) : origin=0x100 length=0x8000 - 0x100 | ||
50 | MCU0_R5F_TCMB0 (RWIX) : origin=0x41010000 length=0x8000 | ||
51 | |||
52 | /* MCU0_R5F_1 SoC view */ | ||
53 | MCU0_R5F1_ATCM (RWIX) : origin=0x41400000 length=0x8000 | ||
54 | MCU0_R5F1_BTCM (RWIX) : origin=0x41410000 length=0x8000 | ||
55 | |||
56 | /* Fully avaialble for apps. Used by SBL to load SYSFW */ | ||
57 | OCMRAM_LOW (RWIX) : origin=0x41C00100 length=0x40600 - 0x100 /* ~257KB */ | ||
58 | |||
59 | /* MCU0 memory used for SBL. Avaiable after boot for app starts for dynamic use */ | ||
60 | SBL_RESERVED (RWIX) : origin=0x41C40600 length=0x60000 - 0x40600 /* ~126KB */ | ||
61 | |||
62 | /* MCU0 share locations */ | ||
63 | OCMRAM (RWIX) : origin=0x41C60000 length=0x20000 - 0x1000 /* ~124KB */ | ||
64 | |||
65 | |||
66 | /* AM65XX M4 locations */ | ||
67 | MSMC3 (RWIX) : origin=0x70000000 length=0xF0000 /* 1MB - 64K */ | ||
68 | MSMC3_H (RWIX) : origin=0x70100000 length=0xE2000 /* 1MB -56K */ | ||
69 | MSMC3_NOCACHE (RWIX) : origin=0x701E2000 length=0xE000 /* 56K */ | ||
70 | |||
71 | /* Reserved for DMSC */ | ||
72 | MSMC3_DMSC (RWIX) : origin=0x701F0000 length=0x10000 /* 64K */ | ||
73 | |||
74 | DDR0 (RWIX) : origin=0x80000000 length=0x80000000 /* 2GB */ | ||
75 | |||
76 | /* Additional memory settings */ | ||
77 | |||
78 | } /* end of MEMORY */ | ||
79 | |||
80 | /*----------------------------------------------------------------------------*/ | ||
81 | /* Section Configuration */ | ||
82 | |||
83 | SECTIONS | ||
84 | { | ||
85 | /* 'intvecs' and 'intc_text' sections shall be placed within */ | ||
86 | /* a range of +\- 16 MB */ | ||
87 | .intvecs : {} palign(8) > VECTORS | ||
88 | .intc_text : {} palign(8) > VECTORS | ||
89 | .rstvectors : {} palign(8) > RESET_VECTORS | ||
90 | .bootCode : {} palign(8) > MSMC3 | ||
91 | .startupCode : {} palign(8) > MSMC3 | ||
92 | .startupData : {} palign(8) > MSMC3, type = NOINIT | ||
93 | .text : {} palign(8) > MSMC3 | ||
94 | .const : {} palign(8) > MSMC3 | ||
95 | .cinit : {} palign(8) > MSMC3 | ||
96 | .pinit : {} palign(8) > MSMC3 | ||
97 | .bss : {} align(4) > MSMC3 | ||
98 | .far : {} align(4) > DDR0 | ||
99 | .data : {} palign(128) > MSMC3 | ||
100 | .boardcfg_data : {} palign(128) > MSMC3 | ||
101 | .sysmem : {} > MSMC3 | ||
102 | |||
103 | /* USB ram disk dev-msc example */ | ||
104 | .bss:extMemCache:ramdisk : {} align (32) > DDR0 | ||
105 | |||
106 | /* UXB host xhci */ | ||
107 | .bss:extMemNonCache:usbXhci : {} align (32) > MSMC3_NOCACHE | ||
108 | |||
109 | /* USB or any other LLD buffer for benchmarking */ | ||
110 | .benchmark_buffer (NOLOAD) {} ALIGN (8) > DDR0 | ||
111 | |||
112 | .stack : {} align(4) > MSMC3 (HIGH) | ||
113 | .irqStack : {. = . + __IRQ_STACK_SIZE;} align(4) > MSMC3 (HIGH) | ||
114 | RUN_START(__IRQ_STACK_START) | ||
115 | RUN_END(__IRQ_STACK_END) | ||
116 | .fiqStack : {. = . + __FIQ_STACK_SIZE;} align(4) > MSMC3 (HIGH) | ||
117 | RUN_START(__FIQ_STACK_START) | ||
118 | RUN_END(__FIQ_STACK_END) | ||
119 | .abortStack : {. = . + __ABORT_STACK_SIZE;} align(4) > MSMC3 (HIGH) | ||
120 | RUN_START(__ABORT_STACK_START) | ||
121 | RUN_END(__ABORT_STACK_END) | ||
122 | .undStack : {. = . + __UND_STACK_SIZE;} align(4) > MSMC3 (HIGH) | ||
123 | RUN_START(__UND_STACK_START) | ||
124 | RUN_END(__UND_STACK_END) | ||
125 | .svcStack : {. = . + __SVC_STACK_SIZE;} align(4) > MSMC3 (HIGH) | ||
126 | RUN_START(__SVC_STACK_START) | ||
127 | RUN_END(__SVC_STACK_END) | ||
128 | |||
129 | /* Additional sections settings */ | ||
130 | |||
131 | } /* end of SECTIONS */ | ||
132 | |||
133 | /*----------------------------------------------------------------------------*/ | ||
134 | /* Misc linker settings */ | ||
135 | |||
136 | |||
137 | /*-------------------------------- END ---------------------------------------*/ | ||
diff --git a/example/build/am65xx/linker_r5_sysbios.lds b/example/build/am65xx/linker_r5_sysbios.lds new file mode 100644 index 0000000..c57a5c6 --- /dev/null +++ b/example/build/am65xx/linker_r5_sysbios.lds | |||
@@ -0,0 +1,99 @@ | |||
1 | /*----------------------------------------------------------------------------*/ | ||
2 | /* File: k3m4_r5f_linker.cmd */ | ||
3 | /* Description: */ | ||
4 | /* Link command file for AM65XX M4 MCU 0 view */ | ||
5 | /* TI ARM Compiler version 15.12.3 LTS or later */ | ||
6 | /* */ | ||
7 | /* Platform: QT */ | ||
8 | /* (c) Texas Instruments 2017, All rights reserved. */ | ||
9 | /*----------------------------------------------------------------------------*/ | ||
10 | /* History: *' | ||
11 | /* Aug 26th, 2016 Original version .......................... Loc Truong */ | ||
12 | /* Aug 01th, 2017 new TCM mem map .......................... Loc Truong */ | ||
13 | /* Nov 07th, 2017 Changes for R5F Init Code.................. Vivek Dhande */ | ||
14 | /*----------------------------------------------------------------------------*/ | ||
15 | /* Linker Settings */ | ||
16 | /* Standard linker options */ | ||
17 | --retain="*(.intvecs)" | ||
18 | --retain="*(.intc_text)" | ||
19 | --retain="*(.rstvectors)" | ||
20 | --fill_value=0 | ||
21 | --entry_point=ti_sysbios_family_arm_v7r_keystone3_Hwi_vectors /* Default BIOS */ | ||
22 | |||
23 | /*----------------------------------------------------------------------------*/ | ||
24 | /* Memory Map */ | ||
25 | MEMORY | ||
26 | { | ||
27 | VECTORS (X) : origin=0x41C7F000 length=0x1000 | ||
28 | /* Reset Vectors base address(RESET_VECTORS) should be 64 bytes aligned */ | ||
29 | RESET_VECTORS (X) : origin=0x41C00000 length=0x100 | ||
30 | /* MCU0_R5F_0 local view */ | ||
31 | MCU0_R5F_TCMA_SBL_RSVD (X) : origin=0x0 length=0x100 | ||
32 | MCU0_R5F_TCMA (X) : origin=0x100 length=0x8000 - 0x100 | ||
33 | MCU0_R5F_TCMB0 (RWIX) : origin=0x41010000 length=0x8000 | ||
34 | |||
35 | /* MCU0_R5F_1 SoC view */ | ||
36 | MCU0_R5F1_ATCM (RWIX) : origin=0x41400000 length=0x8000 | ||
37 | MCU0_R5F1_BTCM (RWIX) : origin=0x41410000 length=0x8000 | ||
38 | |||
39 | /* Fully avaialble for apps. Used by SBL to load SYSFW */ | ||
40 | OCMRAM_LOW (RWIX) : origin=0x41C00100 length=0x40600 - 0x100 /* ~257KB */ | ||
41 | |||
42 | /* MCU0 memory used for SBL. Avaiable after boot for app starts for dynamic use */ | ||
43 | SBL_RESERVED (RWIX) : origin=0x41C40600 length=0x60000 - 0x40600 /* ~126KB */ | ||
44 | |||
45 | /* MCU0 share locations */ | ||
46 | OCMRAM (RWIX) : origin=0x41C60000 length=0x20000 - 0x1000 /* ~124KB */ | ||
47 | |||
48 | /* AM65XX M4 locations */ | ||
49 | MSMC3 (RWIX) : origin=0x70000000 length=0xF0000 /* 1MB - 64K */ | ||
50 | MSMC3_H (RWIX) : origin=0x70100000 length=0xE2000 /* 1MB -56K */ | ||
51 | MSMC3_NOCACHE (RWIX) : origin=0x701E2000 length=0xE000 /* 56K */ | ||
52 | |||
53 | /* Reserved for DMSC */ | ||
54 | MSMC3_DMSC (RWIX) : origin=0x701F0000 length=0x10000 /* 64K */ | ||
55 | |||
56 | DDR0 (RWIX) : origin=0x80000000 length=0x80000000 /* 2GB */ | ||
57 | |||
58 | /* Additional memory settings */ | ||
59 | |||
60 | } /* end of MEMORY */ | ||
61 | |||
62 | /*----------------------------------------------------------------------------*/ | ||
63 | /* Section Configuration */ | ||
64 | |||
65 | SECTIONS | ||
66 | { | ||
67 | /* 'intvecs' and 'intc_text' sections shall be placed within */ | ||
68 | /* a range of +\- 16 MB */ | ||
69 | .intvecs : {} palign(8) > VECTORS | ||
70 | .intc_text : {} palign(8) > VECTORS | ||
71 | .rstvectors : {} palign(8) > RESET_VECTORS | ||
72 | .text : {} palign(8) > MSMC3 | ||
73 | .const : {} palign(8) > MSMC3 | ||
74 | .cinit : {} palign(8) > MSMC3 | ||
75 | .pinit : {} palign(8) > MSMC3 | ||
76 | |||
77 | /* For NDK packet memory, we need to map this sections before .bss*/ | ||
78 | .bss:NDK_MMBUFFER (NOLOAD) {} ALIGN (128) > DDR0 | ||
79 | .bss:NDK_PACKETMEM (NOLOAD) {} ALIGN (128) > DDR0 | ||
80 | |||
81 | .bss : {} align(4) > MSMC3 | ||
82 | .far : {} align(4) > DDR0 | ||
83 | .data : {} palign(128) > MSMC3 | ||
84 | .boardcfg_data : {} palign(128) > MSMC3 | ||
85 | .sysmem : {} > MSMC3 | ||
86 | .stack : {} align(4) > MSMC3 (HIGH) | ||
87 | |||
88 | /* USB or any other LLD buffer for benchmarking */ | ||
89 | .benchmark_buffer (NOLOAD) {} ALIGN (8) > DDR0 | ||
90 | |||
91 | /* Additional sections settings */ | ||
92 | |||
93 | } /* end of SECTIONS */ | ||
94 | |||
95 | /*----------------------------------------------------------------------------*/ | ||
96 | /* Misc linker settings */ | ||
97 | |||
98 | |||
99 | /*-------------------------------- END ---------------------------------------*/ | ||
diff --git a/example/build/usb_dev_bulk/makefile b/example/build/usb_dev_bulk/makefile index 0eae885..f43ecc4 100644 --- a/example/build/usb_dev_bulk/makefile +++ b/example/build/usb_dev_bulk/makefile | |||
@@ -13,6 +13,15 @@ INCLUDE_EXTERNAL_INTERFACES = bios xdc pdk | |||
13 | 13 | ||
14 | #TIRTOS components are indicated in the rtsc cfg file | 14 | #TIRTOS components are indicated in the rtsc cfg file |
15 | 15 | ||
16 | #using USB local linker file instead of ti/build for customization | ||
17 | ifeq ($(CORE),$(filter $(CORE), mcu1_0)) | ||
18 | EXTERNAL_LNKCMD_FILE_LOCAL = $(pdk_PATH)/ti/drv/usb/example/build/$(SOC)/linker_r5_sysbios.lds | ||
19 | endif | ||
20 | |||
21 | ifeq ($(CORE),$(filter $(CORE), mpu1_0)) | ||
22 | EXTERNAL_LNKCMD_FILE_LOCAL = $(pdk_PATH)/ti/drv/usb/example/build/$(SOC)/linker_a53.lds | ||
23 | endif | ||
24 | |||
16 | ifeq ($(USB30),yes) | 25 | ifeq ($(USB30),yes) |
17 | USB3OPT=usb3_ | 26 | USB3OPT=usb3_ |
18 | USB3FLG=-DUSB3SS_EN | 27 | USB3FLG=-DUSB3SS_EN |
diff --git a/example/build/usb_dev_msc/makefile b/example/build/usb_dev_msc/makefile index c37e4e5..20b6e25 100644 --- a/example/build/usb_dev_msc/makefile +++ b/example/build/usb_dev_msc/makefile | |||
@@ -1,4 +1,4 @@ | |||
1 | # Makefile for UART sample app | 1 | # Makefile for USB sample app |
2 | include $(PDK_INSTALL_PATH)/ti/build/Rules.make | 2 | include $(PDK_INSTALL_PATH)/ti/build/Rules.make |
3 | 3 | ||
4 | ifeq ($(BAREMETAL),yes) | 4 | ifeq ($(BAREMETAL),yes) |
@@ -14,6 +14,15 @@ COMP_LIST_COMMON = osal_nonos csl csl_init board uart usb sciclient | |||
14 | # need to be included for this component | 14 | # need to be included for this component |
15 | INCLUDE_EXTERNAL_INTERFACES = pdk | 15 | INCLUDE_EXTERNAL_INTERFACES = pdk |
16 | 16 | ||
17 | #using USB local linker file instead of ti/build for customization | ||
18 | ifeq ($(CORE),$(filter $(CORE), mcu1_0)) | ||
19 | EXTERNAL_LNKCMD_FILE_LOCAL = $(pdk_PATH)/ti/drv/usb/example/build/$(SOC)/linker_r5.lds | ||
20 | endif | ||
21 | |||
22 | ifeq ($(CORE),$(filter $(CORE), mpu1_0)) | ||
23 | EXTERNAL_LNKCMD_FILE_LOCAL = $(pdk_PATH)/ti/drv/usb/example/build/$(SOC)/linker_a53.lds | ||
24 | endif | ||
25 | |||
17 | else | 26 | else |
18 | BUILD_OS_TYPE=tirtos | 27 | BUILD_OS_TYPE=tirtos |
19 | OS_FLAGS=-DTIRTOS | 28 | OS_FLAGS=-DTIRTOS |
@@ -26,6 +35,16 @@ COMP_LIST_COMMON = osal_tirtos csl board uart usb sciclient | |||
26 | INCLUDE_EXTERNAL_INTERFACES = bios xdc pdk | 35 | INCLUDE_EXTERNAL_INTERFACES = bios xdc pdk |
27 | 36 | ||
28 | #TIRTOS components are indicated in the rtsc cfg file | 37 | #TIRTOS components are indicated in the rtsc cfg file |
38 | |||
39 | #using USB local linker file instead of ti/build for customization | ||
40 | ifeq ($(CORE),$(filter $(CORE), mcu1_0)) | ||
41 | EXTERNAL_LNKCMD_FILE_LOCAL = $(pdk_PATH)/ti/drv/usb/example/build/$(SOC)/linker_r5_sysbios.lds | ||
42 | endif | ||
43 | |||
44 | ifeq ($(CORE),$(filter $(CORE), mpu1_0)) | ||
45 | EXTERNAL_LNKCMD_FILE_LOCAL = $(pdk_PATH)/ti/drv/usb/example/build/$(SOC)/linker_a53.lds | ||
46 | endif | ||
47 | |||
29 | endif | 48 | endif |
30 | 49 | ||
31 | ifeq ($(USB30),yes) | 50 | ifeq ($(USB30),yes) |
diff --git a/example/build/usb_host_msc/makefile b/example/build/usb_host_msc/makefile index 8fe2228..ab77782 100644 --- a/example/build/usb_host_msc/makefile +++ b/example/build/usb_host_msc/makefile | |||
@@ -1,4 +1,4 @@ | |||
1 | # Makefile for UART sample app | 1 | # Makefile for USB sample app |
2 | include $(PDK_INSTALL_PATH)/ti/build/Rules.make | 2 | include $(PDK_INSTALL_PATH)/ti/build/Rules.make |
3 | 3 | ||
4 | ifeq ($(BAREMETAL),yes) | 4 | ifeq ($(BAREMETAL),yes) |
@@ -16,6 +16,15 @@ COMP_LIST_COMMON = osal_nonos csl csl_init board uart fatfs_indp usb sciclient | |||
16 | # Enable XDC build for application by providing XDC CFG File per core | 16 | # Enable XDC build for application by providing XDC CFG File per core |
17 | XDC_CFG_FILE_$(CORE) = | 17 | XDC_CFG_FILE_$(CORE) = |
18 | 18 | ||
19 | #using USB local linker file instead of ti/build for customization | ||
20 | ifeq ($(CORE),$(filter $(CORE), mcu1_0)) | ||
21 | EXTERNAL_LNKCMD_FILE_LOCAL = $(pdk_PATH)/ti/drv/usb/example/build/$(SOC)/linker_r5.lds | ||
22 | endif | ||
23 | |||
24 | ifeq ($(CORE),$(filter $(CORE), mpu1_0)) | ||
25 | EXTERNAL_LNKCMD_FILE_LOCAL = $(pdk_PATH)/ti/drv/usb/example/build/$(SOC)/linker_a53.lds | ||
26 | endif | ||
27 | |||
19 | else | 28 | else |
20 | BUILD_OS_TYPE=tirtos | 29 | BUILD_OS_TYPE=tirtos |
21 | OS_FLAGS=-DTIRTOS | 30 | OS_FLAGS=-DTIRTOS |
@@ -30,6 +39,15 @@ COMP_LIST_COMMON = osal_tirtos csl board uart fatfs_indp usb sciclient | |||
30 | # Enable XDC build for application by providing XDC CFG File per core | 39 | # Enable XDC build for application by providing XDC CFG File per core |
31 | XDC_CFG_FILE_$(CORE) = $(PDK_INSTALL_PATH)/ti/drv/usb/example/bios/$(SOC)/usb_$(SOC)_evm.cfg | 40 | XDC_CFG_FILE_$(CORE) = $(PDK_INSTALL_PATH)/ti/drv/usb/example/bios/$(SOC)/usb_$(SOC)_evm.cfg |
32 | 41 | ||
42 | #using USB local linker file instead of ti/build for customization | ||
43 | ifeq ($(CORE),$(filter $(CORE), mcu1_0)) | ||
44 | EXTERNAL_LNKCMD_FILE_LOCAL = $(pdk_PATH)/ti/drv/usb/example/build/$(SOC)/linker_r5_sysbios.lds | ||
45 | endif | ||
46 | |||
47 | ifeq ($(CORE),$(filter $(CORE), mpu1_0)) | ||
48 | EXTERNAL_LNKCMD_FILE_LOCAL = $(pdk_PATH)/ti/drv/usb/example/build/$(SOC)/linker_a53.lds | ||
49 | endif | ||
50 | |||
33 | endif | 51 | endif |
34 | 52 | ||
35 | USB3OPT= | 53 | USB3OPT= |
diff --git a/example/common/usb_arm_r5.asm b/example/common/usb_arm_r5.asm index c6910d4..75ab58f 100644 --- a/example/common/usb_arm_r5.asm +++ b/example/common/usb_arm_r5.asm | |||
@@ -77,8 +77,8 @@ mpu_region_5_base .word 0x41010000 ;The MPU Region Base Address Regi | |||
77 | mpu_region_5_size .word (0x0<<8) | (0xE<<1) | 0x1 ;Region Size and Enable bits (and Subre region enable ) | 77 | mpu_region_5_size .word (0x0<<8) | (0xE<<1) | 0x1 ;Region Size and Enable bits (and Subre region enable ) |
78 | mpu_region_5_permissions .word (0 << 12) | (3 << 8) | (4 << 3) | (0 << 2) | (0 << 0);The MPU Region Access Control | 78 | mpu_region_5_permissions .word (0 << 12) | (3 << 8) | (4 << 3) | (0 << 2) | (0 << 0);The MPU Region Access Control |
79 | 79 | ||
80 | ; make 0x701F2000 to end of MSMC 56KB uncached memory | 80 | ; make a 56K@0x701E2000 MSMC uncached memory |
81 | mpu_region_6_base .word 0x701F0000 ;The MPU Region Base Address Register | 81 | mpu_region_6_base .word 0x701E0000 ;The MPU Region Base Address Register |
82 | mpu_region_6_size .word (0x80<<8) | (0x0F<<1) | 0x1 ; disable subregion 7 (masking out 0x2000 bytes) | 82 | mpu_region_6_size .word (0x80<<8) | (0x0F<<1) | 0x1 ; disable subregion 7 (masking out 0x2000 bytes) |
83 | ; 64KB region size (0x0F). | 83 | ; 64KB region size (0x0F). |
84 | ; Enable bits | 84 | ; Enable bits |