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author | Thanh Tran | 2019-09-16 19:44:57 -0500 |
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committer | Thanh Tran | 2019-09-16 19:44:57 -0500 |
commit | 50c0f7cc336b0a38e3a8f2d12e8d0cea9c77499e (patch) | |
tree | 32fa61574f8b9dc64b7ddc85a5b82e61ce9a1a74 | |
parent | b024af9a03a150aaec6c620b0070b9b4c713f1ea (diff) | |
download | usb-50c0f7cc336b0a38e3a8f2d12e8d0cea9c77499e.tar.gz usb-50c0f7cc336b0a38e3a8f2d12e8d0cea9c77499e.tar.xz usb-50c0f7cc336b0a38e3a8f2d12e8d0cea9c77499e.zip |
Move noncache MSMC setting to USB
Move non-cache section setting from OSAL to USB so that
other non-cache section settings are in one place inside USB.
Update the GPIO interrupt number with latest CSL
-rw-r--r-- | example/bios/biosMmu.c | 42 | ||||
-rw-r--r-- | example/common/usb_c_handler.c | 4 | ||||
-rw-r--r-- | example/common/usb_osal.c | 7 |
3 files changed, 43 insertions, 10 deletions
diff --git a/example/bios/biosMmu.c b/example/bios/biosMmu.c index 8081d10..def62b8 100644 --- a/example/bios/biosMmu.c +++ b/example/bios/biosMmu.c | |||
@@ -1,5 +1,5 @@ | |||
1 | /** | 1 | /** |
2 | * \copyright Copyright (C) 2018 Texas Instruments Incorporated - | 2 | * \copyright Copyright (C) 2018-2019 Texas Instruments Incorporated - |
3 | * http://www.ti.com/ | 3 | * http://www.ti.com/ |
4 | */ | 4 | */ |
5 | 5 | ||
@@ -244,9 +244,49 @@ mmu_exit: | |||
244 | 244 | ||
245 | } | 245 | } |
246 | 246 | ||
247 | #endif | ||
248 | |||
249 | #ifdef SOC_J721E | ||
250 | |||
251 | /* copy of ti/osal/j721e/bios_mmu.c, but add the non-cache MSMC section for USB */ | ||
252 | void InitMmu(void) | ||
253 | { | ||
254 | Mmu_MapAttrs attrs; | ||
255 | |||
256 | Mmu_initMapAttrs(&attrs); | ||
257 | attrs.attrIndx = Mmu_AttrIndx_MAIR0; /* device memory */ | ||
247 | 258 | ||
259 | /* Register region */ | ||
260 | Mmu_map(0x00000000U, 0x00000000U, 0x20000000U, &attrs); | ||
261 | Mmu_map(0x20000000U, 0x20000000U, 0x20000000U, &attrs); | ||
262 | Mmu_map(0x40000000U, 0x40000000U, 0x20000000U, &attrs); | ||
263 | Mmu_map(0x60000000U, 0x60000000U, 0x10000000U, &attrs); | ||
264 | Mmu_map(0x78000000U, 0x78000000U, 0x08000000U, &attrs); /* CLEC */ | ||
265 | |||
266 | #if defined(BUILD_MPU) | ||
267 | Mmu_map(0x400000000U, 0x400000000U, 0x400000000U, &attrs); /* FSS0 data */ | ||
248 | #endif | 268 | #endif |
249 | 269 | ||
270 | attrs.attrIndx = Mmu_AttrIndx_MAIR7; | ||
271 | Mmu_map(0x80000000U, 0x80000000U, 0x20000000U, &attrs); /* DDR */ | ||
272 | Mmu_map(0xA0000000U, 0xA0000000U, 0x20000000U, &attrs); /* DDR */ | ||
273 | Mmu_map(0x70000000U, 0x70000000U, 0x00800000U, &attrs); /* MSMC - 8MB */ | ||
274 | |||
275 | Mmu_map(0x41C00000U, 0x41C00000U, 0x00080000U, &attrs); /* OCMC - 512KB */ | ||
276 | |||
277 | /* | ||
278 | * DDR range 0xA0000000 - 0xAA000000 : Used as RAM by multiple | ||
279 | * remote cores, no need to mmp_map this range. | ||
280 | * IPC VRing Buffer - uncached | ||
281 | */ | ||
282 | attrs.attrIndx = Mmu_AttrIndx_MAIR4; | ||
283 | Mmu_map(0xAA000000, 0xAA000000, 0x02000000, &attrs); | ||
284 | |||
285 | Mmu_map(0x707D0000U, 0x707D0000U, 0x20000U, &attrs); /* MSMC no cache- 128KB */ | ||
286 | |||
287 | return; | ||
288 | } | ||
289 | #endif | ||
250 | 290 | ||
251 | 291 | ||
252 | /* end of file */ | 292 | /* end of file */ |
diff --git a/example/common/usb_c_handler.c b/example/common/usb_c_handler.c index 95371e0..5ccc652 100644 --- a/example/common/usb_c_handler.c +++ b/example/common/usb_c_handler.c | |||
@@ -147,9 +147,9 @@ int32_t GPIO_configIntRouter(uint32_t portNum, uint32_t pinNum, uint32_t gpioInt | |||
147 | 147 | ||
148 | /* WKUP GPIO int router input interrupt is the GPIO bank interrupt */ | 148 | /* WKUP GPIO int router input interrupt is the GPIO bank interrupt */ |
149 | #if (BUILD_MPU) | 149 | #if (BUILD_MPU) |
150 | intCfg[pinNum].intNum = CSLR_COMPUTE_CLUSTER0_GIC_SPI_GPIOMUX_INTRTR0_OUTP_8 + bankNum; | 150 | intCfg[pinNum].intNum = CSLR_COMPUTE_CLUSTER0_GIC500SS_SPI_GPIOMUX_INTRTR0_OUTP_8 + bankNum; |
151 | #else | 151 | #else |
152 | intCfg[pinNum].intNum = CSLR_ARMSS0_CPU0_INTR_GPIOMUX_INTRTR0_OUTP_16 + bankNum; | 152 | intCfg[pinNum].intNum = CSLR_MCU_R5FSS0_CORE0_INTR_MAIN2MCU_LVL_INTRTR0_OUTL_0 + bankNum; |
153 | #endif | 153 | #endif |
154 | intCfg[pinNum].eventId = 0; | 154 | intCfg[pinNum].eventId = 0; |
155 | intCfg[pinNum].intcMuxNum = INVALID_INTC_MUX_NUM; | 155 | intCfg[pinNum].intcMuxNum = INVALID_INTC_MUX_NUM; |
diff --git a/example/common/usb_osal.c b/example/common/usb_osal.c index 74f6321..51db443 100644 --- a/example/common/usb_osal.c +++ b/example/common/usb_osal.c | |||
@@ -281,13 +281,6 @@ uint64_t usb_osalGetPerfCounter(void) | |||
281 | return timeVal; | 281 | return timeVal; |
282 | } | 282 | } |
283 | 283 | ||
284 | #ifdef SOC_J721E | ||
285 | extern void Osal_initMmuDefault(void); | ||
286 | void InitMmu(void) | ||
287 | { | ||
288 | Osal_initMmuDefault(); | ||
289 | } | ||
290 | #endif | ||
291 | 284 | ||
292 | 285 | ||
293 | /* end of OSAL implementation */ | 286 | /* end of OSAL implementation */ |