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author | Kishon Vijay Abraham I | 2018-12-19 04:10:50 -0600 |
---|---|---|
committer | Kishon Vijay Abraham I | 2019-03-20 06:00:54 -0500 |
commit | 623b1a9662c34fa59c6f5332e8ba3435df291b78 (patch) | |
tree | fcf264d810ca1b69000aa9d97cc1f3d147c8e4ac | |
parent | 98e4c16b492f2ae194086a8b766f93065eab0561 (diff) | |
download | kishons-ti-linux-kernel-623b1a9662c34fa59c6f5332e8ba3435df291b78.tar.gz kishons-ti-linux-kernel-623b1a9662c34fa59c6f5332e8ba3435df291b78.tar.xz kishons-ti-linux-kernel-623b1a9662c34fa59c6f5332e8ba3435df291b78.zip |
PCI: dwc: Remove Keystone specific dw_pcie_host_ops
Now that Keystone started using its own msi_irq_chip, remove
Keystone specific callback functions defined in dw_pcie_host_ops.
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
-rw-r--r-- | drivers/pci/controller/dwc/pcie-designware-host.c | 50 | ||||
-rw-r--r-- | drivers/pci/controller/dwc/pcie-designware.h | 5 |
2 files changed, 14 insertions, 41 deletions
diff --git a/drivers/pci/controller/dwc/pcie-designware-host.c b/drivers/pci/controller/dwc/pcie-designware-host.c index 9e47bad82bbc..498422397609 100644 --- a/drivers/pci/controller/dwc/pcie-designware-host.c +++ b/drivers/pci/controller/dwc/pcie-designware-host.c | |||
@@ -126,18 +126,12 @@ static void dw_pci_setup_msi_msg(struct irq_data *d, struct msi_msg *msg) | |||
126 | struct dw_pcie *pci = to_dw_pcie_from_pp(pp); | 126 | struct dw_pcie *pci = to_dw_pcie_from_pp(pp); |
127 | u64 msi_target; | 127 | u64 msi_target; |
128 | 128 | ||
129 | if (pp->ops->get_msi_addr) | 129 | msi_target = (u64)pp->msi_data; |
130 | msi_target = pp->ops->get_msi_addr(pp); | ||
131 | else | ||
132 | msi_target = (u64)pp->msi_data; | ||
133 | 130 | ||
134 | msg->address_lo = lower_32_bits(msi_target); | 131 | msg->address_lo = lower_32_bits(msi_target); |
135 | msg->address_hi = upper_32_bits(msi_target); | 132 | msg->address_hi = upper_32_bits(msi_target); |
136 | 133 | ||
137 | if (pp->ops->get_msi_data) | 134 | msg->data = d->hwirq; |
138 | msg->data = pp->ops->get_msi_data(pp, d->hwirq); | ||
139 | else | ||
140 | msg->data = d->hwirq; | ||
141 | 135 | ||
142 | dev_dbg(pci->dev, "msi#%d address_hi %#x address_lo %#x\n", | 136 | dev_dbg(pci->dev, "msi#%d address_hi %#x address_lo %#x\n", |
143 | (int)d->hwirq, msg->address_hi, msg->address_lo); | 137 | (int)d->hwirq, msg->address_hi, msg->address_lo); |
@@ -157,17 +151,13 @@ static void dw_pci_bottom_mask(struct irq_data *d) | |||
157 | 151 | ||
158 | raw_spin_lock_irqsave(&pp->lock, flags); | 152 | raw_spin_lock_irqsave(&pp->lock, flags); |
159 | 153 | ||
160 | if (pp->ops->msi_clear_irq) { | 154 | ctrl = d->hwirq / MAX_MSI_IRQS_PER_CTRL; |
161 | pp->ops->msi_clear_irq(pp, d->hwirq); | 155 | res = ctrl * MSI_REG_CTRL_BLOCK_SIZE; |
162 | } else { | 156 | bit = d->hwirq % MAX_MSI_IRQS_PER_CTRL; |
163 | ctrl = d->hwirq / MAX_MSI_IRQS_PER_CTRL; | ||
164 | res = ctrl * MSI_REG_CTRL_BLOCK_SIZE; | ||
165 | bit = d->hwirq % MAX_MSI_IRQS_PER_CTRL; | ||
166 | 157 | ||
167 | pp->irq_mask[ctrl] |= BIT(bit); | 158 | pp->irq_mask[ctrl] |= BIT(bit); |
168 | dw_pcie_wr_own_conf(pp, PCIE_MSI_INTR0_MASK + res, 4, | 159 | dw_pcie_wr_own_conf(pp, PCIE_MSI_INTR0_MASK + res, 4, |
169 | pp->irq_mask[ctrl]); | 160 | pp->irq_mask[ctrl]); |
170 | } | ||
171 | 161 | ||
172 | raw_spin_unlock_irqrestore(&pp->lock, flags); | 162 | raw_spin_unlock_irqrestore(&pp->lock, flags); |
173 | } | 163 | } |
@@ -180,17 +170,13 @@ static void dw_pci_bottom_unmask(struct irq_data *d) | |||
180 | 170 | ||
181 | raw_spin_lock_irqsave(&pp->lock, flags); | 171 | raw_spin_lock_irqsave(&pp->lock, flags); |
182 | 172 | ||
183 | if (pp->ops->msi_set_irq) { | 173 | ctrl = d->hwirq / MAX_MSI_IRQS_PER_CTRL; |
184 | pp->ops->msi_set_irq(pp, d->hwirq); | 174 | res = ctrl * MSI_REG_CTRL_BLOCK_SIZE; |
185 | } else { | 175 | bit = d->hwirq % MAX_MSI_IRQS_PER_CTRL; |
186 | ctrl = d->hwirq / MAX_MSI_IRQS_PER_CTRL; | ||
187 | res = ctrl * MSI_REG_CTRL_BLOCK_SIZE; | ||
188 | bit = d->hwirq % MAX_MSI_IRQS_PER_CTRL; | ||
189 | 176 | ||
190 | pp->irq_mask[ctrl] &= ~BIT(bit); | 177 | pp->irq_mask[ctrl] &= ~BIT(bit); |
191 | dw_pcie_wr_own_conf(pp, PCIE_MSI_INTR0_MASK + res, 4, | 178 | dw_pcie_wr_own_conf(pp, PCIE_MSI_INTR0_MASK + res, 4, |
192 | pp->irq_mask[ctrl]); | 179 | pp->irq_mask[ctrl]); |
193 | } | ||
194 | 180 | ||
195 | raw_spin_unlock_irqrestore(&pp->lock, flags); | 181 | raw_spin_unlock_irqrestore(&pp->lock, flags); |
196 | } | 182 | } |
@@ -199,20 +185,12 @@ static void dw_pci_bottom_ack(struct irq_data *d) | |||
199 | { | 185 | { |
200 | struct pcie_port *pp = irq_data_get_irq_chip_data(d); | 186 | struct pcie_port *pp = irq_data_get_irq_chip_data(d); |
201 | unsigned int res, bit, ctrl; | 187 | unsigned int res, bit, ctrl; |
202 | unsigned long flags; | ||
203 | 188 | ||
204 | ctrl = d->hwirq / MAX_MSI_IRQS_PER_CTRL; | 189 | ctrl = d->hwirq / MAX_MSI_IRQS_PER_CTRL; |
205 | res = ctrl * MSI_REG_CTRL_BLOCK_SIZE; | 190 | res = ctrl * MSI_REG_CTRL_BLOCK_SIZE; |
206 | bit = d->hwirq % MAX_MSI_IRQS_PER_CTRL; | 191 | bit = d->hwirq % MAX_MSI_IRQS_PER_CTRL; |
207 | 192 | ||
208 | raw_spin_lock_irqsave(&pp->lock, flags); | ||
209 | |||
210 | dw_pcie_wr_own_conf(pp, PCIE_MSI_INTR0_STATUS + res, 4, BIT(bit)); | 193 | dw_pcie_wr_own_conf(pp, PCIE_MSI_INTR0_STATUS + res, 4, BIT(bit)); |
211 | |||
212 | if (pp->ops->msi_irq_ack) | ||
213 | pp->ops->msi_irq_ack(d->hwirq, pp); | ||
214 | |||
215 | raw_spin_unlock_irqrestore(&pp->lock, flags); | ||
216 | } | 194 | } |
217 | 195 | ||
218 | static struct irq_chip dw_pci_msi_bottom_irq_chip = { | 196 | static struct irq_chip dw_pci_msi_bottom_irq_chip = { |
diff --git a/drivers/pci/controller/dwc/pcie-designware.h b/drivers/pci/controller/dwc/pcie-designware.h index 6b0cea473ee7..ca3a3190a6f5 100644 --- a/drivers/pci/controller/dwc/pcie-designware.h +++ b/drivers/pci/controller/dwc/pcie-designware.h | |||
@@ -145,14 +145,9 @@ struct dw_pcie_host_ops { | |||
145 | int (*wr_other_conf)(struct pcie_port *pp, struct pci_bus *bus, | 145 | int (*wr_other_conf)(struct pcie_port *pp, struct pci_bus *bus, |
146 | unsigned int devfn, int where, int size, u32 val); | 146 | unsigned int devfn, int where, int size, u32 val); |
147 | int (*host_init)(struct pcie_port *pp); | 147 | int (*host_init)(struct pcie_port *pp); |
148 | void (*msi_set_irq)(struct pcie_port *pp, int irq); | ||
149 | void (*msi_clear_irq)(struct pcie_port *pp, int irq); | ||
150 | phys_addr_t (*get_msi_addr)(struct pcie_port *pp); | ||
151 | u32 (*get_msi_data)(struct pcie_port *pp, int pos); | ||
152 | void (*scan_bus)(struct pcie_port *pp); | 148 | void (*scan_bus)(struct pcie_port *pp); |
153 | void (*set_num_vectors)(struct pcie_port *pp); | 149 | void (*set_num_vectors)(struct pcie_port *pp); |
154 | int (*msi_host_init)(struct pcie_port *pp); | 150 | int (*msi_host_init)(struct pcie_port *pp); |
155 | void (*msi_irq_ack)(int irq, struct pcie_port *pp); | ||
156 | }; | 151 | }; |
157 | 152 | ||
158 | struct pcie_port { | 153 | struct pcie_port { |