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authorKishon Vijay Abraham I2014-05-28 08:41:02 -0500
committerKishon Vijay Abraham I2014-05-29 01:23:19 -0500
commita0f2993874f8e81c53a6b0bb9ac04cd4f3cc4cb7 (patch)
treee41cbe4fa1805cc5cf651e6cb871fbbd13e2c05c
parentf389360b8cd4432a68b706659521b0f4a2b78546 (diff)
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ARM: dts: dra7xx-clocks: rename pcie clocks to accommodate second PHY instance
There are two instances of PCIe PHY in DRA7xx. So renamed optfclk_pciephy_32khz, optfclk_pciephy_clk and optfclk_pciephy_div_clk to optfclk_pciephy1_32khz, optfclk_pciephy1_clk and optfclk_pciephy1_div_clk respectively. This is needed for adding the clocks for second PCIe PHY instance.
-rw-r--r--arch/arm/boot/dts/dra7xx-clocks.dtsi6
1 files changed, 3 insertions, 3 deletions
diff --git a/arch/arm/boot/dts/dra7xx-clocks.dtsi b/arch/arm/boot/dts/dra7xx-clocks.dtsi
index e1bd05288b47..3d8c9c2c5cf5 100644
--- a/arch/arm/boot/dts/dra7xx-clocks.dtsi
+++ b/arch/arm/boot/dts/dra7xx-clocks.dtsi
@@ -1165,7 +1165,7 @@
1165 reg = <0x021c>, <0x0220>; 1165 reg = <0x021c>, <0x0220>;
1166 }; 1166 };
1167 1167
1168 optfclk_pciephy_32khz: optfclk_pciephy_32khz@4a0093b0 { 1168 optfclk_pciephy1_32khz: optfclk_pciephy_32khz@4a0093b0 {
1169 compatible = "ti,gate-clock"; 1169 compatible = "ti,gate-clock";
1170 clocks = <&sys_32k_ck>; 1170 clocks = <&sys_32k_ck>;
1171 #clock-cells = <0>; 1171 #clock-cells = <0>;
@@ -1183,7 +1183,7 @@
1183 ti,max-div = <2>; 1183 ti,max-div = <2>;
1184 }; 1184 };
1185 1185
1186 optfclk_pciephy_clk: optfclk_pciephy_clk@4a0093b0 { 1186 optfclk_pciephy1_clk: optfclk_pciephy_clk@4a0093b0 {
1187 compatible = "ti,gate-clock"; 1187 compatible = "ti,gate-clock";
1188 clocks = <&apll_pcie_ck>; 1188 clocks = <&apll_pcie_ck>;
1189 #clock-cells = <0>; 1189 #clock-cells = <0>;
@@ -1191,7 +1191,7 @@
1191 ti,bit-shift = <9>; 1191 ti,bit-shift = <9>;
1192 }; 1192 };
1193 1193
1194 optfclk_pciephy_div_clk: optfclk_pciephy_div_clk@4a0093b0 { 1194 optfclk_pciephy1_div_clk: optfclk_pciephy_div_clk@4a0093b0 {
1195 compatible = "ti,gate-clock"; 1195 compatible = "ti,gate-clock";
1196 clocks = <&optfclk_pciephy_div>; 1196 clocks = <&optfclk_pciephy_div>;
1197 #clock-cells = <0>; 1197 #clock-cells = <0>;