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authorKishon Vijay Abraham I2014-03-18 06:43:19 -0500
committerKishon Vijay Abraham I2014-05-29 01:23:18 -0500
commitb4d3b7f38a9bc286795670362a63bafd35efeedd (patch)
treeefc3aaf38bbc88ccb5798433ab4c441157b39002
parentec3fb2f39bb99ce82665bf7954a9db666aa8e598 (diff)
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arm: dra7xx: Add hwmod data for pcie1 and pcie2 subsystems
Added hwmod data for pcie1 and pcie2 subsystem present in DRA7xx SOC. Cc: Tony Lindgren <tony@atomide.com> Cc: Russell King <linux@arm.linux.org.uk> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
-rw-r--r--arch/arm/mach-omap2/omap_hwmod_7xx_data.c55
1 files changed, 55 insertions, 0 deletions
diff --git a/arch/arm/mach-omap2/omap_hwmod_7xx_data.c b/arch/arm/mach-omap2/omap_hwmod_7xx_data.c
index 1282a428dcf2..a51fa7f17c90 100644
--- a/arch/arm/mach-omap2/omap_hwmod_7xx_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_7xx_data.c
@@ -1231,6 +1231,43 @@ static struct omap_hwmod dra7xx_ocp2scp3_hwmod = {
1231}; 1231};
1232 1232
1233/* 1233/*
1234 * 'PCIE' class
1235 *
1236 */
1237
1238static struct omap_hwmod_class dra7xx_pcie_hwmod_class = {
1239 .name = "pcie",
1240};
1241
1242/* pcie1 */
1243static struct omap_hwmod dra7xx_pcie1_hwmod = {
1244 .name = "pcie1",
1245 .class = &dra7xx_pcie_hwmod_class,
1246 .clkdm_name = "l3init_clkdm",
1247 .main_clk = "l4_root_clk_div",
1248 .prcm = {
1249 .omap4 = {
1250 .clkctrl_offs = DRA7XX_CM_PCIE_CLKSTCTRL_OFFSET,
1251 .modulemode = MODULEMODE_SWCTRL,
1252 },
1253 },
1254};
1255
1256/* pcie2 */
1257static struct omap_hwmod dra7xx_pcie2_hwmod = {
1258 .name = "pcie2",
1259 .class = &dra7xx_pcie_hwmod_class,
1260 .clkdm_name = "l3init_clkdm",
1261 .main_clk = "l4_root_clk_div",
1262 .prcm = {
1263 .omap4 = {
1264 .clkctrl_offs = DRA7XX_CM_PCIE_CLKSTCTRL_OFFSET,
1265 .modulemode = MODULEMODE_SWCTRL,
1266 },
1267 },
1268};
1269
1270/*
1234 * 'PCIE PHY' class 1271 * 'PCIE PHY' class
1235 * 1272 *
1236 */ 1273 */
@@ -2388,6 +2425,22 @@ static struct omap_hwmod_ocp_if dra7xx_l4_cfg__ocp2scp1 = {
2388 .user = OCP_USER_MPU | OCP_USER_SDMA, 2425 .user = OCP_USER_MPU | OCP_USER_SDMA,
2389}; 2426};
2390 2427
2428/* l4_cfg -> pcie1 */
2429static struct omap_hwmod_ocp_if dra7xx_l4_cfg__pcie1 = {
2430 .master = &dra7xx_l4_cfg_hwmod,
2431 .slave = &dra7xx_pcie1_hwmod,
2432 .clk = "l4_root_clk_div",
2433 .user = OCP_USER_MPU | OCP_USER_SDMA,
2434};
2435
2436/* l4_cfg -> pcie2 */
2437static struct omap_hwmod_ocp_if dra7xx_l4_cfg__pcie2 = {
2438 .master = &dra7xx_l4_cfg_hwmod,
2439 .slave = &dra7xx_pcie2_hwmod,
2440 .clk = "l4_root_clk_div",
2441 .user = OCP_USER_MPU | OCP_USER_SDMA,
2442};
2443
2391/* l4_cfg -> pcie1 phy */ 2444/* l4_cfg -> pcie1 phy */
2392static struct omap_hwmod_ocp_if dra7xx_l4_cfg__pcie1_phy = { 2445static struct omap_hwmod_ocp_if dra7xx_l4_cfg__pcie1_phy = {
2393 .master = &dra7xx_l4_cfg_hwmod, 2446 .master = &dra7xx_l4_cfg_hwmod,
@@ -2751,6 +2804,8 @@ static struct omap_hwmod_ocp_if *dra7xx_hwmod_ocp_ifs[] __initdata = {
2751 &dra7xx_l4_cfg__mpu, 2804 &dra7xx_l4_cfg__mpu,
2752 &dra7xx_l4_cfg__ocp2scp1, 2805 &dra7xx_l4_cfg__ocp2scp1,
2753 &dra7xx_l4_cfg__ocp2scp3, 2806 &dra7xx_l4_cfg__ocp2scp3,
2807 &dra7xx_l4_cfg__pcie1,
2808 &dra7xx_l4_cfg__pcie2,
2754 &dra7xx_l4_cfg__pcie1_phy, 2809 &dra7xx_l4_cfg__pcie1_phy,
2755 &dra7xx_l4_cfg__pcie2_phy, 2810 &dra7xx_l4_cfg__pcie2_phy,
2756 &dra7xx_l3_main_1__qspi, 2811 &dra7xx_l3_main_1__qspi,