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authorKishon Vijay Abraham I2014-03-18 06:43:48 -0500
committerKishon Vijay Abraham I2014-05-29 01:23:18 -0500
commitd02be1b3cd796861e06d8a0f82149d27755cb6dc (patch)
treee9d9a3be33def3f547f896da451aa3a5bd5a5ea9
parentb4d3b7f38a9bc286795670362a63bafd35efeedd (diff)
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ARM: dts: dra7xx-clocks: Add missing 32khz clocks used for PHY
Added missing 32khz clock used by PCIe PHY. The documention for this node can be found @ ../bindings/clock/ti/gate.txt. Cc: Tony Lindgren <tony@atomide.com> Cc: Rajendra Nayak <rnayak@ti.com> Cc: Tero Kristo <t-kristo@ti.com> Cc: Paul Walmsley <paul@pwsan.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
-rw-r--r--arch/arm/boot/dts/dra7xx-clocks.dtsi8
1 files changed, 8 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/dra7xx-clocks.dtsi b/arch/arm/boot/dts/dra7xx-clocks.dtsi
index 44993ecf0036..e1bd05288b47 100644
--- a/arch/arm/boot/dts/dra7xx-clocks.dtsi
+++ b/arch/arm/boot/dts/dra7xx-clocks.dtsi
@@ -1165,6 +1165,14 @@
1165 reg = <0x021c>, <0x0220>; 1165 reg = <0x021c>, <0x0220>;
1166 }; 1166 };
1167 1167
1168 optfclk_pciephy_32khz: optfclk_pciephy_32khz@4a0093b0 {
1169 compatible = "ti,gate-clock";
1170 clocks = <&sys_32k_ck>;
1171 #clock-cells = <0>;
1172 reg = <0x13b0>;
1173 ti,bit-shift = <8>;
1174 };
1175
1168 optfclk_pciephy_div: optfclk_pciephy_div@4a00821c { 1176 optfclk_pciephy_div: optfclk_pciephy_div@4a00821c {
1169 compatible = "ti,divider-clock"; 1177 compatible = "ti,divider-clock";
1170 clocks = <&apll_pcie_ck>; 1178 clocks = <&apll_pcie_ck>;