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authorKishon Vijay Abraham I2014-05-28 08:48:06 -0500
committerKishon Vijay Abraham I2014-05-29 01:23:20 -0500
commitf0ba76ad3fac734010b6d82e39ec1e4fc4474dd2 (patch)
tree0fbc65bae95d366c9ce5bbd1100bf925cb86a906
parenta0f2993874f8e81c53a6b0bb9ac04cd4f3cc4cb7 (diff)
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ARM: dts: dra7xx-clocks: Add missing clocks for second PCIe PHY instance
Added missing clocks used by second instance of PCIe PHY. The documention for this nodes can be found @ ../bindings/clock/ti/gate.txt.
-rw-r--r--arch/arm/boot/dts/dra7xx-clocks.dtsi24
1 files changed, 24 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/dra7xx-clocks.dtsi b/arch/arm/boot/dts/dra7xx-clocks.dtsi
index 3d8c9c2c5cf5..a9ff0dc8b9c7 100644
--- a/arch/arm/boot/dts/dra7xx-clocks.dtsi
+++ b/arch/arm/boot/dts/dra7xx-clocks.dtsi
@@ -1173,6 +1173,14 @@
1173 ti,bit-shift = <8>; 1173 ti,bit-shift = <8>;
1174 }; 1174 };
1175 1175
1176 optfclk_pciephy2_32khz: optfclk_pciephy_32khz@4a0093b4 {
1177 compatible = "ti,gate-clock";
1178 clocks = <&sys_32k_ck>;
1179 #clock-cells = <0>;
1180 reg = <0x13b4>;
1181 ti,bit-shift = <8>;
1182 };
1183
1176 optfclk_pciephy_div: optfclk_pciephy_div@4a00821c { 1184 optfclk_pciephy_div: optfclk_pciephy_div@4a00821c {
1177 compatible = "ti,divider-clock"; 1185 compatible = "ti,divider-clock";
1178 clocks = <&apll_pcie_ck>; 1186 clocks = <&apll_pcie_ck>;
@@ -1191,6 +1199,14 @@
1191 ti,bit-shift = <9>; 1199 ti,bit-shift = <9>;
1192 }; 1200 };
1193 1201
1202 optfclk_pciephy2_clk: optfclk_pciephy_clk@4a0093b4 {
1203 compatible = "ti,gate-clock";
1204 clocks = <&apll_pcie_ck>;
1205 #clock-cells = <0>;
1206 reg = <0x13b4>;
1207 ti,bit-shift = <9>;
1208 };
1209
1194 optfclk_pciephy1_div_clk: optfclk_pciephy_div_clk@4a0093b0 { 1210 optfclk_pciephy1_div_clk: optfclk_pciephy_div_clk@4a0093b0 {
1195 compatible = "ti,gate-clock"; 1211 compatible = "ti,gate-clock";
1196 clocks = <&optfclk_pciephy_div>; 1212 clocks = <&optfclk_pciephy_div>;
@@ -1199,6 +1215,14 @@
1199 ti,bit-shift = <10>; 1215 ti,bit-shift = <10>;
1200 }; 1216 };
1201 1217
1218 optfclk_pciephy2_div_clk: optfclk_pciephy_div_clk@4a0093b4 {
1219 compatible = "ti,gate-clock";
1220 clocks = <&optfclk_pciephy_div>;
1221 #clock-cells = <0>;
1222 reg = <0x13b4>;
1223 ti,bit-shift = <10>;
1224 };
1225
1202 apll_pcie_clkvcoldo: apll_pcie_clkvcoldo { 1226 apll_pcie_clkvcoldo: apll_pcie_clkvcoldo {
1203 #clock-cells = <0>; 1227 #clock-cells = <0>;
1204 compatible = "fixed-factor-clock"; 1228 compatible = "fixed-factor-clock";