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authorKishon Vijay Abraham I2017-03-07 00:40:13 -0600
committerKishon Vijay Abraham I2017-03-07 00:40:13 -0600
commit59e58d943e049480a157755adee94a0f11b452f7 (patch)
tree22361efb2ebaaf30b9ae029ceafeea3408b02dfa
parent0c490b3f54a8854e473768fc046216f8e31bac90 (diff)
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PCI: dwc: all: Modify dbi accessors to take dbi_base as argument
dwc has 2 dbi address space labeled dbics and dbics2. The existing helper to access dbi address space can access only dbics. However dbics2 has to be accessed for programming the BAR registers in the case of EP mode. This is in preparation for adding EP mode support to dwc driver. Cc: Jingoo Han <jingoohan1@gmail.com> Cc: Richard Zhu <hongxing.zhu@nxp.com> Cc: Lucas Stach <l.stach@pengutronix.de> Cc: Murali Karicheri <m-karicheri2@ti.com> Cc: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Cc: Niklas Cassel <niklas.cassel@axis.com> Cc: Jesper Nilsson <jesper.nilsson@axis.com> Cc: Joao Pinto <Joao.Pinto@synopsys.com> Cc: Zhou Wang <wangzhou1@hisilicon.com> Cc: Gabriele Paoloni <gabriele.paoloni@huawei.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
-rw-r--r--drivers/pci/dwc/pci-dra7xx.c10
-rw-r--r--drivers/pci/dwc/pci-exynos.c10
-rw-r--r--drivers/pci/dwc/pci-imx6.c62
-rw-r--r--drivers/pci/dwc/pci-keystone-dw.c15
-rw-r--r--drivers/pci/dwc/pcie-armada8k.c39
-rw-r--r--drivers/pci/dwc/pcie-artpec6.c7
-rw-r--r--drivers/pci/dwc/pcie-designware-host.c20
-rw-r--r--drivers/pci/dwc/pcie-designware.c76
-rw-r--r--drivers/pci/dwc/pcie-designware.h10
-rw-r--r--drivers/pci/dwc/pcie-hisi.c17
10 files changed, 152 insertions, 114 deletions
diff --git a/drivers/pci/dwc/pci-dra7xx.c b/drivers/pci/dwc/pci-dra7xx.c
index 07c45ec07662..3708bd6367c2 100644
--- a/drivers/pci/dwc/pci-dra7xx.c
+++ b/drivers/pci/dwc/pci-dra7xx.c
@@ -495,12 +495,13 @@ static int dra7xx_pcie_suspend(struct device *dev)
495{ 495{
496 struct dra7xx_pcie *dra7xx = dev_get_drvdata(dev); 496 struct dra7xx_pcie *dra7xx = dev_get_drvdata(dev);
497 struct dw_pcie *pci = dra7xx->pci; 497 struct dw_pcie *pci = dra7xx->pci;
498 void __iomem *base = pci->dbi_base;
498 u32 val; 499 u32 val;
499 500
500 /* clear MSE */ 501 /* clear MSE */
501 val = dw_pcie_readl_dbi(pci, PCI_COMMAND); 502 val = dw_pcie_readl_dbi(pci, base, PCI_COMMAND);
502 val &= ~PCI_COMMAND_MEMORY; 503 val &= ~PCI_COMMAND_MEMORY;
503 dw_pcie_writel_dbi(pci, PCI_COMMAND, val); 504 dw_pcie_writel_dbi(pci, base, PCI_COMMAND, val);
504 505
505 return 0; 506 return 0;
506} 507}
@@ -509,12 +510,13 @@ static int dra7xx_pcie_resume(struct device *dev)
509{ 510{
510 struct dra7xx_pcie *dra7xx = dev_get_drvdata(dev); 511 struct dra7xx_pcie *dra7xx = dev_get_drvdata(dev);
511 struct dw_pcie *pci = dra7xx->pci; 512 struct dw_pcie *pci = dra7xx->pci;
513 void __iomem *base = pci->dbi_base;
512 u32 val; 514 u32 val;
513 515
514 /* set MSE */ 516 /* set MSE */
515 val = dw_pcie_readl_dbi(pci, PCI_COMMAND); 517 val = dw_pcie_readl_dbi(pci, base, PCI_COMMAND);
516 val |= PCI_COMMAND_MEMORY; 518 val |= PCI_COMMAND_MEMORY;
517 dw_pcie_writel_dbi(pci, PCI_COMMAND, val); 519 dw_pcie_writel_dbi(pci, base, PCI_COMMAND, val);
518 520
519 return 0; 521 return 0;
520} 522}
diff --git a/drivers/pci/dwc/pci-exynos.c b/drivers/pci/dwc/pci-exynos.c
index 993b650ef275..a0d40f74b88d 100644
--- a/drivers/pci/dwc/pci-exynos.c
+++ b/drivers/pci/dwc/pci-exynos.c
@@ -521,23 +521,25 @@ static void exynos_pcie_enable_interrupts(struct exynos_pcie *ep)
521 exynos_pcie_msi_init(ep); 521 exynos_pcie_msi_init(ep);
522} 522}
523 523
524static u32 exynos_pcie_readl_dbi(struct dw_pcie *pci, u32 reg) 524static u32 exynos_pcie_readl_dbi(struct dw_pcie *pci, void __iomem *base,
525 u32 reg)
525{ 526{
526 struct exynos_pcie *ep = to_exynos_pcie(pci); 527 struct exynos_pcie *ep = to_exynos_pcie(pci);
527 u32 val; 528 u32 val;
528 529
529 exynos_pcie_sideband_dbi_r_mode(ep, true); 530 exynos_pcie_sideband_dbi_r_mode(ep, true);
530 val = readl(pci->dbi_base + reg); 531 val = readl(base + reg);
531 exynos_pcie_sideband_dbi_r_mode(ep, false); 532 exynos_pcie_sideband_dbi_r_mode(ep, false);
532 return val; 533 return val;
533} 534}
534 535
535static void exynos_pcie_writel_dbi(struct dw_pcie *pci, u32 reg, u32 val) 536static void exynos_pcie_writel_dbi(struct dw_pcie *pci, void __iomem *base,
537 u32 reg, u32 val)
536{ 538{
537 struct exynos_pcie *ep = to_exynos_pcie(pci); 539 struct exynos_pcie *ep = to_exynos_pcie(pci);
538 540
539 exynos_pcie_sideband_dbi_w_mode(ep, true); 541 exynos_pcie_sideband_dbi_w_mode(ep, true);
540 writel(val, pci->dbi_base + reg); 542 writel(val, base + reg);
541 exynos_pcie_sideband_dbi_w_mode(ep, false); 543 exynos_pcie_sideband_dbi_w_mode(ep, false);
542} 544}
543 545
diff --git a/drivers/pci/dwc/pci-imx6.c b/drivers/pci/dwc/pci-imx6.c
index 801e46cd266d..85dd9018e29e 100644
--- a/drivers/pci/dwc/pci-imx6.c
+++ b/drivers/pci/dwc/pci-imx6.c
@@ -98,12 +98,13 @@ struct imx6_pcie {
98static int pcie_phy_poll_ack(struct imx6_pcie *imx6_pcie, int exp_val) 98static int pcie_phy_poll_ack(struct imx6_pcie *imx6_pcie, int exp_val)
99{ 99{
100 struct dw_pcie *pci = imx6_pcie->pci; 100 struct dw_pcie *pci = imx6_pcie->pci;
101 void __iomem *base = pci->dbi_base;
101 u32 val; 102 u32 val;
102 u32 max_iterations = 10; 103 u32 max_iterations = 10;
103 u32 wait_counter = 0; 104 u32 wait_counter = 0;
104 105
105 do { 106 do {
106 val = dw_pcie_readl_dbi(pci, PCIE_PHY_STAT); 107 val = dw_pcie_readl_dbi(pci, base, PCIE_PHY_STAT);
107 val = (val >> PCIE_PHY_STAT_ACK_LOC) & 0x1; 108 val = (val >> PCIE_PHY_STAT_ACK_LOC) & 0x1;
108 wait_counter++; 109 wait_counter++;
109 110
@@ -119,21 +120,22 @@ static int pcie_phy_poll_ack(struct imx6_pcie *imx6_pcie, int exp_val)
119static int pcie_phy_wait_ack(struct imx6_pcie *imx6_pcie, int addr) 120static int pcie_phy_wait_ack(struct imx6_pcie *imx6_pcie, int addr)
120{ 121{
121 struct dw_pcie *pci = imx6_pcie->pci; 122 struct dw_pcie *pci = imx6_pcie->pci;
123 void __iomem *base = pci->dbi_base;
122 u32 val; 124 u32 val;
123 int ret; 125 int ret;
124 126
125 val = addr << PCIE_PHY_CTRL_DATA_LOC; 127 val = addr << PCIE_PHY_CTRL_DATA_LOC;
126 dw_pcie_writel_dbi(pci, PCIE_PHY_CTRL, val); 128 dw_pcie_writel_dbi(pci, base, PCIE_PHY_CTRL, val);
127 129
128 val |= (0x1 << PCIE_PHY_CTRL_CAP_ADR_LOC); 130 val |= (0x1 << PCIE_PHY_CTRL_CAP_ADR_LOC);
129 dw_pcie_writel_dbi(pci, PCIE_PHY_CTRL, val); 131 dw_pcie_writel_dbi(pci, base, PCIE_PHY_CTRL, val);
130 132
131 ret = pcie_phy_poll_ack(imx6_pcie, 1); 133 ret = pcie_phy_poll_ack(imx6_pcie, 1);
132 if (ret) 134 if (ret)
133 return ret; 135 return ret;
134 136
135 val = addr << PCIE_PHY_CTRL_DATA_LOC; 137 val = addr << PCIE_PHY_CTRL_DATA_LOC;
136 dw_pcie_writel_dbi(pci, PCIE_PHY_CTRL, val); 138 dw_pcie_writel_dbi(pci, base, PCIE_PHY_CTRL, val);
137 139
138 return pcie_phy_poll_ack(imx6_pcie, 0); 140 return pcie_phy_poll_ack(imx6_pcie, 0);
139} 141}
@@ -142,6 +144,7 @@ static int pcie_phy_wait_ack(struct imx6_pcie *imx6_pcie, int addr)
142static int pcie_phy_read(struct imx6_pcie *imx6_pcie, int addr, int *data) 144static int pcie_phy_read(struct imx6_pcie *imx6_pcie, int addr, int *data)
143{ 145{
144 struct dw_pcie *pci = imx6_pcie->pci; 146 struct dw_pcie *pci = imx6_pcie->pci;
147 void __iomem *base = pci->dbi_base;
145 u32 val, phy_ctl; 148 u32 val, phy_ctl;
146 int ret; 149 int ret;
147 150
@@ -151,17 +154,17 @@ static int pcie_phy_read(struct imx6_pcie *imx6_pcie, int addr, int *data)
151 154
152 /* assert Read signal */ 155 /* assert Read signal */
153 phy_ctl = 0x1 << PCIE_PHY_CTRL_RD_LOC; 156 phy_ctl = 0x1 << PCIE_PHY_CTRL_RD_LOC;
154 dw_pcie_writel_dbi(pci, PCIE_PHY_CTRL, phy_ctl); 157 dw_pcie_writel_dbi(pci, base, PCIE_PHY_CTRL, phy_ctl);
155 158
156 ret = pcie_phy_poll_ack(imx6_pcie, 1); 159 ret = pcie_phy_poll_ack(imx6_pcie, 1);
157 if (ret) 160 if (ret)
158 return ret; 161 return ret;
159 162
160 val = dw_pcie_readl_dbi(pci, PCIE_PHY_STAT); 163 val = dw_pcie_readl_dbi(pci, base, PCIE_PHY_STAT);
161 *data = val & 0xffff; 164 *data = val & 0xffff;
162 165
163 /* deassert Read signal */ 166 /* deassert Read signal */
164 dw_pcie_writel_dbi(pci, PCIE_PHY_CTRL, 0x00); 167 dw_pcie_writel_dbi(pci, base, PCIE_PHY_CTRL, 0x00);
165 168
166 return pcie_phy_poll_ack(imx6_pcie, 0); 169 return pcie_phy_poll_ack(imx6_pcie, 0);
167} 170}
@@ -169,6 +172,7 @@ static int pcie_phy_read(struct imx6_pcie *imx6_pcie, int addr, int *data)
169static int pcie_phy_write(struct imx6_pcie *imx6_pcie, int addr, int data) 172static int pcie_phy_write(struct imx6_pcie *imx6_pcie, int addr, int data)
170{ 173{
171 struct dw_pcie *pci = imx6_pcie->pci; 174 struct dw_pcie *pci = imx6_pcie->pci;
175 void __iomem *base = pci->dbi_base;
172 u32 var; 176 u32 var;
173 int ret; 177 int ret;
174 178
@@ -179,11 +183,11 @@ static int pcie_phy_write(struct imx6_pcie *imx6_pcie, int addr, int data)
179 return ret; 183 return ret;
180 184
181 var = data << PCIE_PHY_CTRL_DATA_LOC; 185 var = data << PCIE_PHY_CTRL_DATA_LOC;
182 dw_pcie_writel_dbi(pci, PCIE_PHY_CTRL, var); 186 dw_pcie_writel_dbi(pci, base, PCIE_PHY_CTRL, var);
183 187
184 /* capture data */ 188 /* capture data */
185 var |= (0x1 << PCIE_PHY_CTRL_CAP_DAT_LOC); 189 var |= (0x1 << PCIE_PHY_CTRL_CAP_DAT_LOC);
186 dw_pcie_writel_dbi(pci, PCIE_PHY_CTRL, var); 190 dw_pcie_writel_dbi(pci, base, PCIE_PHY_CTRL, var);
187 191
188 ret = pcie_phy_poll_ack(imx6_pcie, 1); 192 ret = pcie_phy_poll_ack(imx6_pcie, 1);
189 if (ret) 193 if (ret)
@@ -191,7 +195,7 @@ static int pcie_phy_write(struct imx6_pcie *imx6_pcie, int addr, int data)
191 195
192 /* deassert cap data */ 196 /* deassert cap data */
193 var = data << PCIE_PHY_CTRL_DATA_LOC; 197 var = data << PCIE_PHY_CTRL_DATA_LOC;
194 dw_pcie_writel_dbi(pci, PCIE_PHY_CTRL, var); 198 dw_pcie_writel_dbi(pci, base, PCIE_PHY_CTRL, var);
195 199
196 /* wait for ack de-assertion */ 200 /* wait for ack de-assertion */
197 ret = pcie_phy_poll_ack(imx6_pcie, 0); 201 ret = pcie_phy_poll_ack(imx6_pcie, 0);
@@ -200,7 +204,7 @@ static int pcie_phy_write(struct imx6_pcie *imx6_pcie, int addr, int data)
200 204
201 /* assert wr signal */ 205 /* assert wr signal */
202 var = 0x1 << PCIE_PHY_CTRL_WR_LOC; 206 var = 0x1 << PCIE_PHY_CTRL_WR_LOC;
203 dw_pcie_writel_dbi(pci, PCIE_PHY_CTRL, var); 207 dw_pcie_writel_dbi(pci, base, PCIE_PHY_CTRL, var);
204 208
205 /* wait for ack */ 209 /* wait for ack */
206 ret = pcie_phy_poll_ack(imx6_pcie, 1); 210 ret = pcie_phy_poll_ack(imx6_pcie, 1);
@@ -209,14 +213,14 @@ static int pcie_phy_write(struct imx6_pcie *imx6_pcie, int addr, int data)
209 213
210 /* deassert wr signal */ 214 /* deassert wr signal */
211 var = data << PCIE_PHY_CTRL_DATA_LOC; 215 var = data << PCIE_PHY_CTRL_DATA_LOC;
212 dw_pcie_writel_dbi(pci, PCIE_PHY_CTRL, var); 216 dw_pcie_writel_dbi(pci, base, PCIE_PHY_CTRL, var);
213 217
214 /* wait for ack de-assertion */ 218 /* wait for ack de-assertion */
215 ret = pcie_phy_poll_ack(imx6_pcie, 0); 219 ret = pcie_phy_poll_ack(imx6_pcie, 0);
216 if (ret) 220 if (ret)
217 return ret; 221 return ret;
218 222
219 dw_pcie_writel_dbi(pci, PCIE_PHY_CTRL, 0x0); 223 dw_pcie_writel_dbi(pci, base, PCIE_PHY_CTRL, 0x0);
220 224
221 return 0; 225 return 0;
222} 226}
@@ -411,6 +415,7 @@ static void imx6_pcie_init_phy(struct imx6_pcie *imx6_pcie)
411static int imx6_pcie_wait_for_link(struct imx6_pcie *imx6_pcie) 415static int imx6_pcie_wait_for_link(struct imx6_pcie *imx6_pcie)
412{ 416{
413 struct dw_pcie *pci = imx6_pcie->pci; 417 struct dw_pcie *pci = imx6_pcie->pci;
418 void __iomem *base = pci->dbi_base;
414 struct device *dev = pci->dev; 419 struct device *dev = pci->dev;
415 420
416 /* check if the link is up or not */ 421 /* check if the link is up or not */
@@ -418,20 +423,22 @@ static int imx6_pcie_wait_for_link(struct imx6_pcie *imx6_pcie)
418 return 0; 423 return 0;
419 424
420 dev_dbg(dev, "DEBUG_R0: 0x%08x, DEBUG_R1: 0x%08x\n", 425 dev_dbg(dev, "DEBUG_R0: 0x%08x, DEBUG_R1: 0x%08x\n",
421 dw_pcie_readl_dbi(pci, PCIE_PHY_DEBUG_R0), 426 dw_pcie_readl_dbi(pci, base, PCIE_PHY_DEBUG_R0),
422 dw_pcie_readl_dbi(pci, PCIE_PHY_DEBUG_R1)); 427 dw_pcie_readl_dbi(pci, base, PCIE_PHY_DEBUG_R1));
423 return -ETIMEDOUT; 428 return -ETIMEDOUT;
424} 429}
425 430
426static int imx6_pcie_wait_for_speed_change(struct imx6_pcie *imx6_pcie) 431static int imx6_pcie_wait_for_speed_change(struct imx6_pcie *imx6_pcie)
427{ 432{
428 struct dw_pcie *pci = imx6_pcie->pci; 433 struct dw_pcie *pci = imx6_pcie->pci;
434 void __iomem *base = pci->dbi_base;
429 struct device *dev = pci->dev; 435 struct device *dev = pci->dev;
430 u32 tmp; 436 u32 tmp;
431 unsigned int retries; 437 unsigned int retries;
432 438
433 for (retries = 0; retries < 200; retries++) { 439 for (retries = 0; retries < 200; retries++) {
434 tmp = dw_pcie_readl_dbi(pci, PCIE_LINK_WIDTH_SPEED_CONTROL); 440 tmp = dw_pcie_readl_dbi(pci, base,
441 PCIE_LINK_WIDTH_SPEED_CONTROL);
435 /* Test if the speed change finished. */ 442 /* Test if the speed change finished. */
436 if (!(tmp & PORT_LOGIC_SPEED_CHANGE)) 443 if (!(tmp & PORT_LOGIC_SPEED_CHANGE))
437 return 0; 444 return 0;
@@ -454,6 +461,7 @@ static irqreturn_t imx6_pcie_msi_handler(int irq, void *arg)
454static int imx6_pcie_establish_link(struct imx6_pcie *imx6_pcie) 461static int imx6_pcie_establish_link(struct imx6_pcie *imx6_pcie)
455{ 462{
456 struct dw_pcie *pci = imx6_pcie->pci; 463 struct dw_pcie *pci = imx6_pcie->pci;
464 void __iomem *base = pci->dbi_base;
457 struct device *dev = pci->dev; 465 struct device *dev = pci->dev;
458 u32 tmp; 466 u32 tmp;
459 int ret; 467 int ret;
@@ -463,10 +471,10 @@ static int imx6_pcie_establish_link(struct imx6_pcie *imx6_pcie)
463 * started in Gen2 mode, there is a possibility the devices on the 471 * started in Gen2 mode, there is a possibility the devices on the
464 * bus will not be detected at all. This happens with PCIe switches. 472 * bus will not be detected at all. This happens with PCIe switches.
465 */ 473 */
466 tmp = dw_pcie_readl_dbi(pci, PCIE_RC_LCR); 474 tmp = dw_pcie_readl_dbi(pci, base, PCIE_RC_LCR);
467 tmp &= ~PCIE_RC_LCR_MAX_LINK_SPEEDS_MASK; 475 tmp &= ~PCIE_RC_LCR_MAX_LINK_SPEEDS_MASK;
468 tmp |= PCIE_RC_LCR_MAX_LINK_SPEEDS_GEN1; 476 tmp |= PCIE_RC_LCR_MAX_LINK_SPEEDS_GEN1;
469 dw_pcie_writel_dbi(pci, PCIE_RC_LCR, tmp); 477 dw_pcie_writel_dbi(pci, base, PCIE_RC_LCR, tmp);
470 478
471 /* Start LTSSM. */ 479 /* Start LTSSM. */
472 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12, 480 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12,
@@ -478,10 +486,10 @@ static int imx6_pcie_establish_link(struct imx6_pcie *imx6_pcie)
478 486
479 if (imx6_pcie->link_gen == 2) { 487 if (imx6_pcie->link_gen == 2) {
480 /* Allow Gen2 mode after the link is up. */ 488 /* Allow Gen2 mode after the link is up. */
481 tmp = dw_pcie_readl_dbi(pci, PCIE_RC_LCR); 489 tmp = dw_pcie_readl_dbi(pci, base, PCIE_RC_LCR);
482 tmp &= ~PCIE_RC_LCR_MAX_LINK_SPEEDS_MASK; 490 tmp &= ~PCIE_RC_LCR_MAX_LINK_SPEEDS_MASK;
483 tmp |= PCIE_RC_LCR_MAX_LINK_SPEEDS_GEN2; 491 tmp |= PCIE_RC_LCR_MAX_LINK_SPEEDS_GEN2;
484 dw_pcie_writel_dbi(pci, PCIE_RC_LCR, tmp); 492 dw_pcie_writel_dbi(pci, base, PCIE_RC_LCR, tmp);
485 } else { 493 } else {
486 dev_info(dev, "Link: Gen2 disabled\n"); 494 dev_info(dev, "Link: Gen2 disabled\n");
487 } 495 }
@@ -490,9 +498,9 @@ static int imx6_pcie_establish_link(struct imx6_pcie *imx6_pcie)
490 * Start Directed Speed Change so the best possible speed both link 498 * Start Directed Speed Change so the best possible speed both link
491 * partners support can be negotiated. 499 * partners support can be negotiated.
492 */ 500 */
493 tmp = dw_pcie_readl_dbi(pci, PCIE_LINK_WIDTH_SPEED_CONTROL); 501 tmp = dw_pcie_readl_dbi(pci, base, PCIE_LINK_WIDTH_SPEED_CONTROL);
494 tmp |= PORT_LOGIC_SPEED_CHANGE; 502 tmp |= PORT_LOGIC_SPEED_CHANGE;
495 dw_pcie_writel_dbi(pci, PCIE_LINK_WIDTH_SPEED_CONTROL, tmp); 503 dw_pcie_writel_dbi(pci, base, PCIE_LINK_WIDTH_SPEED_CONTROL, tmp);
496 504
497 ret = imx6_pcie_wait_for_speed_change(imx6_pcie); 505 ret = imx6_pcie_wait_for_speed_change(imx6_pcie);
498 if (ret) { 506 if (ret) {
@@ -507,14 +515,14 @@ static int imx6_pcie_establish_link(struct imx6_pcie *imx6_pcie)
507 goto err_reset_phy; 515 goto err_reset_phy;
508 } 516 }
509 517
510 tmp = dw_pcie_readl_dbi(pci, PCIE_RC_LCSR); 518 tmp = dw_pcie_readl_dbi(pci, base, PCIE_RC_LCSR);
511 dev_info(dev, "Link up, Gen%i\n", (tmp >> 16) & 0xf); 519 dev_info(dev, "Link up, Gen%i\n", (tmp >> 16) & 0xf);
512 return 0; 520 return 0;
513 521
514err_reset_phy: 522err_reset_phy:
515 dev_dbg(dev, "PHY DEBUG_R0=0x%08x DEBUG_R1=0x%08x\n", 523 dev_dbg(dev, "PHY DEBUG_R0=0x%08x DEBUG_R1=0x%08x\n",
516 dw_pcie_readl_dbi(pci, PCIE_PHY_DEBUG_R0), 524 dw_pcie_readl_dbi(pci, base, PCIE_PHY_DEBUG_R0),
517 dw_pcie_readl_dbi(pci, PCIE_PHY_DEBUG_R1)); 525 dw_pcie_readl_dbi(pci, base, PCIE_PHY_DEBUG_R1));
518 imx6_pcie_reset_phy(imx6_pcie); 526 imx6_pcie_reset_phy(imx6_pcie);
519 return ret; 527 return ret;
520} 528}
@@ -536,7 +544,9 @@ static void imx6_pcie_host_init(struct pcie_port *pp)
536 544
537static int imx6_pcie_link_up(struct dw_pcie *pci) 545static int imx6_pcie_link_up(struct dw_pcie *pci)
538{ 546{
539 return dw_pcie_readl_dbi(pci, PCIE_PHY_DEBUG_R1) & 547 void __iomem *base = pci->dbi_base;
548
549 return dw_pcie_readl_dbi(pci, base, PCIE_PHY_DEBUG_R1) &
540 PCIE_PHY_DEBUG_R1_XMLH_LINK_UP; 550 PCIE_PHY_DEBUG_R1_XMLH_LINK_UP;
541} 551}
542 552
diff --git a/drivers/pci/dwc/pci-keystone-dw.c b/drivers/pci/dwc/pci-keystone-dw.c
index 6b396f6b4615..7220c04f40ff 100644
--- a/drivers/pci/dwc/pci-keystone-dw.c
+++ b/drivers/pci/dwc/pci-keystone-dw.c
@@ -378,6 +378,7 @@ static void ks_dw_pcie_clear_dbi_mode(struct keystone_pcie *ks_pcie)
378void ks_dw_pcie_setup_rc_app_regs(struct keystone_pcie *ks_pcie) 378void ks_dw_pcie_setup_rc_app_regs(struct keystone_pcie *ks_pcie)
379{ 379{
380 struct dw_pcie *pci = ks_pcie->pci; 380 struct dw_pcie *pci = ks_pcie->pci;
381 void __iomem *base = pci->dbi_base;
381 struct pcie_port *pp = &pci->pp; 382 struct pcie_port *pp = &pci->pp;
382 u32 start = pp->mem->start, end = pp->mem->end; 383 u32 start = pp->mem->start, end = pp->mem->end;
383 int i, tr_size; 384 int i, tr_size;
@@ -385,8 +386,8 @@ void ks_dw_pcie_setup_rc_app_regs(struct keystone_pcie *ks_pcie)
385 386
386 /* Disable BARs for inbound access */ 387 /* Disable BARs for inbound access */
387 ks_dw_pcie_set_dbi_mode(ks_pcie); 388 ks_dw_pcie_set_dbi_mode(ks_pcie);
388 dw_pcie_writel_dbi(pci, PCI_BASE_ADDRESS_0, 0); 389 dw_pcie_writel_dbi(pci, base, PCI_BASE_ADDRESS_0, 0);
389 dw_pcie_writel_dbi(pci, PCI_BASE_ADDRESS_1, 0); 390 dw_pcie_writel_dbi(pci, base, PCI_BASE_ADDRESS_1, 0);
390 ks_dw_pcie_clear_dbi_mode(ks_pcie); 391 ks_dw_pcie_clear_dbi_mode(ks_pcie);
391 392
392 /* Set outbound translation size per window division */ 393 /* Set outbound translation size per window division */
@@ -482,14 +483,15 @@ int ks_dw_pcie_wr_other_conf(struct pcie_port *pp, struct pci_bus *bus,
482void ks_dw_pcie_v3_65_scan_bus(struct pcie_port *pp) 483void ks_dw_pcie_v3_65_scan_bus(struct pcie_port *pp)
483{ 484{
484 struct dw_pcie *pci = to_dw_pcie_from_pp(pp); 485 struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
486 void __iomem *base = pci->dbi_base;
485 struct keystone_pcie *ks_pcie = to_keystone_pcie(pci); 487 struct keystone_pcie *ks_pcie = to_keystone_pcie(pci);
486 488
487 /* Configure and set up BAR0 */ 489 /* Configure and set up BAR0 */
488 ks_dw_pcie_set_dbi_mode(ks_pcie); 490 ks_dw_pcie_set_dbi_mode(ks_pcie);
489 491
490 /* Enable BAR0 */ 492 /* Enable BAR0 */
491 dw_pcie_writel_dbi(pci, PCI_BASE_ADDRESS_0, 1); 493 dw_pcie_writel_dbi(pci, base, PCI_BASE_ADDRESS_0, 1);
492 dw_pcie_writel_dbi(pci, PCI_BASE_ADDRESS_0, SZ_4K - 1); 494 dw_pcie_writel_dbi(pci, base, PCI_BASE_ADDRESS_0, SZ_4K - 1);
493 495
494 ks_dw_pcie_clear_dbi_mode(ks_pcie); 496 ks_dw_pcie_clear_dbi_mode(ks_pcie);
495 497
@@ -497,7 +499,7 @@ void ks_dw_pcie_v3_65_scan_bus(struct pcie_port *pp)
497 * For BAR0, just setting bus address for inbound writes (MSI) should 499 * For BAR0, just setting bus address for inbound writes (MSI) should
498 * be sufficient. Use physical address to avoid any conflicts. 500 * be sufficient. Use physical address to avoid any conflicts.
499 */ 501 */
500 dw_pcie_writel_dbi(pci, PCI_BASE_ADDRESS_0, ks_pcie->app.start); 502 dw_pcie_writel_dbi(pci, base, PCI_BASE_ADDRESS_0, ks_pcie->app.start);
501} 503}
502 504
503/** 505/**
@@ -506,8 +508,9 @@ void ks_dw_pcie_v3_65_scan_bus(struct pcie_port *pp)
506int ks_dw_pcie_link_up(struct dw_pcie *pci) 508int ks_dw_pcie_link_up(struct dw_pcie *pci)
507{ 509{
508 u32 val; 510 u32 val;
511 void __iomem *base = pci->dbi_base;
509 512
510 val = dw_pcie_readl_dbi(pci, DEBUG0); 513 val = dw_pcie_readl_dbi(pci, base, DEBUG0);
511 return (val & LTSSM_STATE_MASK) == LTSSM_STATE_L0; 514 return (val & LTSSM_STATE_MASK) == LTSSM_STATE_L0;
512} 515}
513 516
diff --git a/drivers/pci/dwc/pcie-armada8k.c b/drivers/pci/dwc/pcie-armada8k.c
index f110e3b24a26..b2328dfb1c63 100644
--- a/drivers/pci/dwc/pcie-armada8k.c
+++ b/drivers/pci/dwc/pcie-armada8k.c
@@ -73,8 +73,9 @@ static int armada8k_pcie_link_up(struct dw_pcie *pci)
73{ 73{
74 u32 reg; 74 u32 reg;
75 u32 mask = PCIE_GLB_STS_RDLH_LINK_UP | PCIE_GLB_STS_PHY_LINK_UP; 75 u32 mask = PCIE_GLB_STS_RDLH_LINK_UP | PCIE_GLB_STS_PHY_LINK_UP;
76 void __iomem *base = pci->dbi_base;
76 77
77 reg = dw_pcie_readl_dbi(pci, PCIE_GLOBAL_STATUS_REG); 78 reg = dw_pcie_readl_dbi(pci, base, PCIE_GLOBAL_STATUS_REG);
78 79
79 if ((reg & mask) == mask) 80 if ((reg & mask) == mask)
80 return 1; 81 return 1;
@@ -86,47 +87,50 @@ static int armada8k_pcie_link_up(struct dw_pcie *pci)
86static void armada8k_pcie_establish_link(struct armada8k_pcie *pcie) 87static void armada8k_pcie_establish_link(struct armada8k_pcie *pcie)
87{ 88{
88 struct dw_pcie *pci = pcie->pci; 89 struct dw_pcie *pci = pcie->pci;
90 void __iomem *base = pci->dbi_base;
89 u32 reg; 91 u32 reg;
90 92
91 if (!dw_pcie_link_up(pci)) { 93 if (!dw_pcie_link_up(pci)) {
92 /* Disable LTSSM state machine to enable configuration */ 94 /* Disable LTSSM state machine to enable configuration */
93 reg = dw_pcie_readl_dbi(pci, PCIE_GLOBAL_CONTROL_REG); 95 reg = dw_pcie_readl_dbi(pci, base, PCIE_GLOBAL_CONTROL_REG);
94 reg &= ~(PCIE_APP_LTSSM_EN); 96 reg &= ~(PCIE_APP_LTSSM_EN);
95 dw_pcie_writel_dbi(pci, PCIE_GLOBAL_CONTROL_REG, reg); 97 dw_pcie_writel_dbi(pci, base, PCIE_GLOBAL_CONTROL_REG, reg);
96 } 98 }
97 99
98 /* Set the device to root complex mode */ 100 /* Set the device to root complex mode */
99 reg = dw_pcie_readl_dbi(pci, PCIE_GLOBAL_CONTROL_REG); 101 reg = dw_pcie_readl_dbi(pci, base, PCIE_GLOBAL_CONTROL_REG);
100 reg &= ~(PCIE_DEVICE_TYPE_MASK << PCIE_DEVICE_TYPE_SHIFT); 102 reg &= ~(PCIE_DEVICE_TYPE_MASK << PCIE_DEVICE_TYPE_SHIFT);
101 reg |= PCIE_DEVICE_TYPE_RC << PCIE_DEVICE_TYPE_SHIFT; 103 reg |= PCIE_DEVICE_TYPE_RC << PCIE_DEVICE_TYPE_SHIFT;
102 dw_pcie_writel_dbi(pci, PCIE_GLOBAL_CONTROL_REG, reg); 104 dw_pcie_writel_dbi(pci, base, PCIE_GLOBAL_CONTROL_REG, reg);
103 105
104 /* Set the PCIe master AxCache attributes */ 106 /* Set the PCIe master AxCache attributes */
105 dw_pcie_writel_dbi(pci, PCIE_ARCACHE_TRC_REG, ARCACHE_DEFAULT_VALUE); 107 dw_pcie_writel_dbi(pci, base, PCIE_ARCACHE_TRC_REG,
106 dw_pcie_writel_dbi(pci, PCIE_AWCACHE_TRC_REG, AWCACHE_DEFAULT_VALUE); 108 ARCACHE_DEFAULT_VALUE);
109 dw_pcie_writel_dbi(pci, base, PCIE_AWCACHE_TRC_REG,
110 AWCACHE_DEFAULT_VALUE);
107 111
108 /* Set the PCIe master AxDomain attributes */ 112 /* Set the PCIe master AxDomain attributes */
109 reg = dw_pcie_readl_dbi(pci, PCIE_ARUSER_REG); 113 reg = dw_pcie_readl_dbi(pci, base, PCIE_ARUSER_REG);
110 reg &= ~(AX_USER_DOMAIN_MASK << AX_USER_DOMAIN_SHIFT); 114 reg &= ~(AX_USER_DOMAIN_MASK << AX_USER_DOMAIN_SHIFT);
111 reg |= DOMAIN_OUTER_SHAREABLE << AX_USER_DOMAIN_SHIFT; 115 reg |= DOMAIN_OUTER_SHAREABLE << AX_USER_DOMAIN_SHIFT;
112 dw_pcie_writel_dbi(pci, PCIE_ARUSER_REG, reg); 116 dw_pcie_writel_dbi(pci, base, PCIE_ARUSER_REG, reg);
113 117
114 reg = dw_pcie_readl_dbi(pci, PCIE_AWUSER_REG); 118 reg = dw_pcie_readl_dbi(pci, base, PCIE_AWUSER_REG);
115 reg &= ~(AX_USER_DOMAIN_MASK << AX_USER_DOMAIN_SHIFT); 119 reg &= ~(AX_USER_DOMAIN_MASK << AX_USER_DOMAIN_SHIFT);
116 reg |= DOMAIN_OUTER_SHAREABLE << AX_USER_DOMAIN_SHIFT; 120 reg |= DOMAIN_OUTER_SHAREABLE << AX_USER_DOMAIN_SHIFT;
117 dw_pcie_writel_dbi(pci, PCIE_AWUSER_REG, reg); 121 dw_pcie_writel_dbi(pci, base, PCIE_AWUSER_REG, reg);
118 122
119 /* Enable INT A-D interrupts */ 123 /* Enable INT A-D interrupts */
120 reg = dw_pcie_readl_dbi(pci, PCIE_GLOBAL_INT_MASK1_REG); 124 reg = dw_pcie_readl_dbi(pci, base, PCIE_GLOBAL_INT_MASK1_REG);
121 reg |= PCIE_INT_A_ASSERT_MASK | PCIE_INT_B_ASSERT_MASK | 125 reg |= PCIE_INT_A_ASSERT_MASK | PCIE_INT_B_ASSERT_MASK |
122 PCIE_INT_C_ASSERT_MASK | PCIE_INT_D_ASSERT_MASK; 126 PCIE_INT_C_ASSERT_MASK | PCIE_INT_D_ASSERT_MASK;
123 dw_pcie_writel_dbi(pci, PCIE_GLOBAL_INT_MASK1_REG, reg); 127 dw_pcie_writel_dbi(pci, base, PCIE_GLOBAL_INT_MASK1_REG, reg);
124 128
125 if (!dw_pcie_link_up(pci)) { 129 if (!dw_pcie_link_up(pci)) {
126 /* Configuration done. Start LTSSM */ 130 /* Configuration done. Start LTSSM */
127 reg = dw_pcie_readl_dbi(pci, PCIE_GLOBAL_CONTROL_REG); 131 reg = dw_pcie_readl_dbi(pci, base, PCIE_GLOBAL_CONTROL_REG);
128 reg |= PCIE_APP_LTSSM_EN; 132 reg |= PCIE_APP_LTSSM_EN;
129 dw_pcie_writel_dbi(pci, PCIE_GLOBAL_CONTROL_REG, reg); 133 dw_pcie_writel_dbi(pci, base, PCIE_GLOBAL_CONTROL_REG, reg);
130 } 134 }
131 135
132 /* Wait until the link becomes active again */ 136 /* Wait until the link becomes active again */
@@ -147,6 +151,7 @@ static irqreturn_t armada8k_pcie_irq_handler(int irq, void *arg)
147{ 151{
148 struct armada8k_pcie *pcie = arg; 152 struct armada8k_pcie *pcie = arg;
149 struct dw_pcie *pci = pcie->pci; 153 struct dw_pcie *pci = pcie->pci;
154 void __iomem *base = pci->dbi_base;
150 u32 val; 155 u32 val;
151 156
152 /* 157 /*
@@ -154,8 +159,8 @@ static irqreturn_t armada8k_pcie_irq_handler(int irq, void *arg)
154 * PCI device. However, they are also latched into the PCIe 159 * PCI device. However, they are also latched into the PCIe
155 * controller, so we simply discard them. 160 * controller, so we simply discard them.
156 */ 161 */
157 val = dw_pcie_readl_dbi(pci, PCIE_GLOBAL_INT_CAUSE1_REG); 162 val = dw_pcie_readl_dbi(pci, base, PCIE_GLOBAL_INT_CAUSE1_REG);
158 dw_pcie_writel_dbi(pci, PCIE_GLOBAL_INT_CAUSE1_REG, val); 163 dw_pcie_writel_dbi(pci, base, PCIE_GLOBAL_INT_CAUSE1_REG, val);
159 164
160 return IRQ_HANDLED; 165 return IRQ_HANDLED;
161} 166}
diff --git a/drivers/pci/dwc/pcie-artpec6.c b/drivers/pci/dwc/pcie-artpec6.c
index 5b3b3afc0edb..e3ba11ce3cb4 100644
--- a/drivers/pci/dwc/pcie-artpec6.c
+++ b/drivers/pci/dwc/pcie-artpec6.c
@@ -86,6 +86,7 @@ static u64 artpec6_pcie_cpu_addr_fixup(u64 pci_addr)
86static int artpec6_pcie_establish_link(struct artpec6_pcie *artpec6_pcie) 86static int artpec6_pcie_establish_link(struct artpec6_pcie *artpec6_pcie)
87{ 87{
88 struct dw_pcie *pci = artpec6_pcie->pci; 88 struct dw_pcie *pci = artpec6_pcie->pci;
89 void __iomem *base = pci->dbi_base;
89 struct pcie_port *pp = &pci->pp; 90 struct pcie_port *pp = &pci->pp;
90 u32 val; 91 u32 val;
91 unsigned int retries; 92 unsigned int retries;
@@ -145,7 +146,7 @@ static int artpec6_pcie_establish_link(struct artpec6_pcie *artpec6_pcie)
145 * Enable writing to config regs. This is required as the Synopsys 146 * Enable writing to config regs. This is required as the Synopsys
146 * driver changes the class code. That register needs DBI write enable. 147 * driver changes the class code. That register needs DBI write enable.
147 */ 148 */
148 dw_pcie_writel_dbi(pci, MISC_CONTROL_1_OFF, DBI_RO_WR_EN); 149 dw_pcie_writel_dbi(pci, base, MISC_CONTROL_1_OFF, DBI_RO_WR_EN);
149 150
150 /* setup root complex */ 151 /* setup root complex */
151 dw_pcie_setup_rc(pp); 152 dw_pcie_setup_rc(pp);
@@ -160,8 +161,8 @@ static int artpec6_pcie_establish_link(struct artpec6_pcie *artpec6_pcie)
160 return 0; 161 return 0;
161 162
162 dev_dbg(pci->dev, "DEBUG_R0: 0x%08x, DEBUG_R1: 0x%08x\n", 163 dev_dbg(pci->dev, "DEBUG_R0: 0x%08x, DEBUG_R1: 0x%08x\n",
163 dw_pcie_readl_dbi(pci, PCIE_PHY_DEBUG_R0), 164 dw_pcie_readl_dbi(pci, base, PCIE_PHY_DEBUG_R0),
164 dw_pcie_readl_dbi(pci, PCIE_PHY_DEBUG_R1)); 165 dw_pcie_readl_dbi(pci, base, PCIE_PHY_DEBUG_R1));
165 166
166 return -ETIMEDOUT; 167 return -ETIMEDOUT;
167} 168}
diff --git a/drivers/pci/dwc/pcie-designware-host.c b/drivers/pci/dwc/pcie-designware-host.c
index 5ba334938b52..9df620de7793 100644
--- a/drivers/pci/dwc/pcie-designware-host.c
+++ b/drivers/pci/dwc/pcie-designware-host.c
@@ -566,8 +566,9 @@ static struct pci_ops dw_pcie_ops = {
566static u8 dw_pcie_iatu_unroll_enabled(struct dw_pcie *pci) 566static u8 dw_pcie_iatu_unroll_enabled(struct dw_pcie *pci)
567{ 567{
568 u32 val; 568 u32 val;
569 void __iomem *base = pci->dbi_base;
569 570
570 val = dw_pcie_readl_dbi(pci, PCIE_ATU_VIEWPORT); 571 val = dw_pcie_readl_dbi(pci, base, PCIE_ATU_VIEWPORT);
571 if (val == 0xffffffff) 572 if (val == 0xffffffff)
572 return 1; 573 return 1;
573 574
@@ -578,31 +579,32 @@ void dw_pcie_setup_rc(struct pcie_port *pp)
578{ 579{
579 u32 val; 580 u32 val;
580 struct dw_pcie *pci = to_dw_pcie_from_pp(pp); 581 struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
582 void __iomem *base = pci->dbi_base;
581 583
582 dw_pcie_setup(pci); 584 dw_pcie_setup(pci);
583 585
584 /* setup RC BARs */ 586 /* setup RC BARs */
585 dw_pcie_writel_dbi(pci, PCI_BASE_ADDRESS_0, 0x00000004); 587 dw_pcie_writel_dbi(pci, base, PCI_BASE_ADDRESS_0, 0x00000004);
586 dw_pcie_writel_dbi(pci, PCI_BASE_ADDRESS_1, 0x00000000); 588 dw_pcie_writel_dbi(pci, base, PCI_BASE_ADDRESS_1, 0x00000000);
587 589
588 /* setup interrupt pins */ 590 /* setup interrupt pins */
589 val = dw_pcie_readl_dbi(pci, PCI_INTERRUPT_LINE); 591 val = dw_pcie_readl_dbi(pci, base, PCI_INTERRUPT_LINE);
590 val &= 0xffff00ff; 592 val &= 0xffff00ff;
591 val |= 0x00000100; 593 val |= 0x00000100;
592 dw_pcie_writel_dbi(pci, PCI_INTERRUPT_LINE, val); 594 dw_pcie_writel_dbi(pci, base, PCI_INTERRUPT_LINE, val);
593 595
594 /* setup bus numbers */ 596 /* setup bus numbers */
595 val = dw_pcie_readl_dbi(pci, PCI_PRIMARY_BUS); 597 val = dw_pcie_readl_dbi(pci, base, PCI_PRIMARY_BUS);
596 val &= 0xff000000; 598 val &= 0xff000000;
597 val |= 0x00010100; 599 val |= 0x00010100;
598 dw_pcie_writel_dbi(pci, PCI_PRIMARY_BUS, val); 600 dw_pcie_writel_dbi(pci, base, PCI_PRIMARY_BUS, val);
599 601
600 /* setup command register */ 602 /* setup command register */
601 val = dw_pcie_readl_dbi(pci, PCI_COMMAND); 603 val = dw_pcie_readl_dbi(pci, base, PCI_COMMAND);
602 val &= 0xffff0000; 604 val &= 0xffff0000;
603 val |= PCI_COMMAND_IO | PCI_COMMAND_MEMORY | 605 val |= PCI_COMMAND_IO | PCI_COMMAND_MEMORY |
604 PCI_COMMAND_MASTER | PCI_COMMAND_SERR; 606 PCI_COMMAND_MASTER | PCI_COMMAND_SERR;
605 dw_pcie_writel_dbi(pci, PCI_COMMAND, val); 607 dw_pcie_writel_dbi(pci, base, PCI_COMMAND, val);
606 608
607 /* 609 /*
608 * If the platform provides ->rd_other_conf, it means the platform 610 * If the platform provides ->rd_other_conf, it means the platform
diff --git a/drivers/pci/dwc/pcie-designware.c b/drivers/pci/dwc/pcie-designware.c
index 14ee7a33a91d..f8eaeeace8ae 100644
--- a/drivers/pci/dwc/pcie-designware.c
+++ b/drivers/pci/dwc/pcie-designware.c
@@ -61,75 +61,82 @@ int dw_pcie_write(void __iomem *addr, int size, u32 val)
61 return PCIBIOS_SUCCESSFUL; 61 return PCIBIOS_SUCCESSFUL;
62} 62}
63 63
64u32 dw_pcie_readl_dbi(struct dw_pcie *pci, u32 reg) 64u32 dw_pcie_readl_dbi(struct dw_pcie *pci, void __iomem *base, u32 reg)
65{ 65{
66 if (pci->ops->readl_dbi) 66 if (pci->ops->readl_dbi)
67 return pci->ops->readl_dbi(pci, reg); 67 return pci->ops->readl_dbi(pci, base, reg);
68 68
69 return readl(pci->dbi_base + reg); 69 return readl(base + reg);
70} 70}
71 71
72void dw_pcie_writel_dbi(struct dw_pcie *pci, u32 reg, u32 val) 72void dw_pcie_writel_dbi(struct dw_pcie *pci, void __iomem *base, u32 reg,
73 u32 val)
73{ 74{
74 if (pci->ops->writel_dbi) 75 if (pci->ops->writel_dbi)
75 pci->ops->writel_dbi(pci, reg, val); 76 pci->ops->writel_dbi(pci, base, reg, val);
76 else 77 else
77 writel(val, pci->dbi_base + reg); 78 writel(val, base + reg);
78} 79}
79 80
80static u32 dw_pcie_readl_unroll(struct dw_pcie *pci, u32 index, u32 reg) 81static u32 dw_pcie_readl_unroll(struct dw_pcie *pci, void __iomem *base,
82 u32 index, u32 reg)
81{ 83{
82 u32 offset = PCIE_GET_ATU_OUTB_UNR_REG_OFFSET(index); 84 u32 offset = PCIE_GET_ATU_OUTB_UNR_REG_OFFSET(index);
83 85
84 return dw_pcie_readl_dbi(pci, offset + reg); 86 return dw_pcie_readl_dbi(pci, base, offset + reg);
85} 87}
86 88
87static void dw_pcie_writel_unroll(struct dw_pcie *pci, u32 index, u32 reg, 89static void dw_pcie_writel_unroll(struct dw_pcie *pci, void __iomem *base,
88 u32 val) 90 u32 index, u32 reg, u32 val)
89{ 91{
90 u32 offset = PCIE_GET_ATU_OUTB_UNR_REG_OFFSET(index); 92 u32 offset = PCIE_GET_ATU_OUTB_UNR_REG_OFFSET(index);
91 93
92 dw_pcie_writel_dbi(pci, offset + reg, val); 94 dw_pcie_writel_dbi(pci, base, offset + reg, val);
93} 95}
94 96
95void dw_pcie_prog_outbound_atu(struct dw_pcie *pci, int index, int type, 97void dw_pcie_prog_outbound_atu(struct dw_pcie *pci, int index, int type,
96 u64 cpu_addr, u64 pci_addr, u32 size) 98 u64 cpu_addr, u64 pci_addr, u32 size)
97{ 99{
98 u32 retries, val; 100 u32 retries, val;
101 void __iomem *base = pci->dbi_base;
99 102
100 if (pp->ops->cpu_addr_fixup) 103 if (pci->ops->cpu_addr_fixup)
101 cpu_addr = pp->ops->cpu_addr_fixup(cpu_addr); 104 cpu_addr = pci->ops->cpu_addr_fixup(cpu_addr);
102 105
103 if (pci->iatu_unroll_enabled) { 106 if (pci->iatu_unroll_enabled) {
104 dw_pcie_writel_unroll(pci, index, PCIE_ATU_UNR_LOWER_BASE, 107 dw_pcie_writel_unroll(pci, base, index, PCIE_ATU_UNR_LOWER_BASE,
105 lower_32_bits(cpu_addr)); 108 lower_32_bits(cpu_addr));
106 dw_pcie_writel_unroll(pci, index, PCIE_ATU_UNR_UPPER_BASE, 109 dw_pcie_writel_unroll(pci, base, index, PCIE_ATU_UNR_UPPER_BASE,
107 upper_32_bits(cpu_addr)); 110 upper_32_bits(cpu_addr));
108 dw_pcie_writel_unroll(pci, index, PCIE_ATU_UNR_LIMIT, 111 dw_pcie_writel_unroll(pci, base, index, PCIE_ATU_UNR_LIMIT,
109 lower_32_bits(cpu_addr + size - 1)); 112 lower_32_bits(cpu_addr + size - 1));
110 dw_pcie_writel_unroll(pci, index, PCIE_ATU_UNR_LOWER_TARGET, 113 dw_pcie_writel_unroll(pci, base, index,
114 PCIE_ATU_UNR_LOWER_TARGET,
111 lower_32_bits(pci_addr)); 115 lower_32_bits(pci_addr));
112 dw_pcie_writel_unroll(pci, index, PCIE_ATU_UNR_UPPER_TARGET, 116 dw_pcie_writel_unroll(pci, base, index,
117 PCIE_ATU_UNR_UPPER_TARGET,
113 upper_32_bits(pci_addr)); 118 upper_32_bits(pci_addr));
114 dw_pcie_writel_unroll(pci, index, PCIE_ATU_UNR_REGION_CTRL1, 119 dw_pcie_writel_unroll(pci, base, index,
120 PCIE_ATU_UNR_REGION_CTRL1,
115 type); 121 type);
116 dw_pcie_writel_unroll(pci, index, PCIE_ATU_UNR_REGION_CTRL2, 122 dw_pcie_writel_unroll(pci, base, index,
123 PCIE_ATU_UNR_REGION_CTRL2,
117 PCIE_ATU_ENABLE); 124 PCIE_ATU_ENABLE);
118 } else { 125 } else {
119 dw_pcie_writel_dbi(pci, PCIE_ATU_VIEWPORT, 126 dw_pcie_writel_dbi(pci, base, PCIE_ATU_VIEWPORT,
120 PCIE_ATU_REGION_OUTBOUND | index); 127 PCIE_ATU_REGION_OUTBOUND | index);
121 dw_pcie_writel_dbi(pci, PCIE_ATU_LOWER_BASE, 128 dw_pcie_writel_dbi(pci, base, PCIE_ATU_LOWER_BASE,
122 lower_32_bits(cpu_addr)); 129 lower_32_bits(cpu_addr));
123 dw_pcie_writel_dbi(pci, PCIE_ATU_UPPER_BASE, 130 dw_pcie_writel_dbi(pci, base, PCIE_ATU_UPPER_BASE,
124 upper_32_bits(cpu_addr)); 131 upper_32_bits(cpu_addr));
125 dw_pcie_writel_dbi(pci, PCIE_ATU_LIMIT, 132 dw_pcie_writel_dbi(pci, base, PCIE_ATU_LIMIT,
126 lower_32_bits(cpu_addr + size - 1)); 133 lower_32_bits(cpu_addr + size - 1));
127 dw_pcie_writel_dbi(pci, PCIE_ATU_LOWER_TARGET, 134 dw_pcie_writel_dbi(pci, base, PCIE_ATU_LOWER_TARGET,
128 lower_32_bits(pci_addr)); 135 lower_32_bits(pci_addr));
129 dw_pcie_writel_dbi(pci, PCIE_ATU_UPPER_TARGET, 136 dw_pcie_writel_dbi(pci, base, PCIE_ATU_UPPER_TARGET,
130 upper_32_bits(pci_addr)); 137 upper_32_bits(pci_addr));
131 dw_pcie_writel_dbi(pci, PCIE_ATU_CR1, type); 138 dw_pcie_writel_dbi(pci, base, PCIE_ATU_CR1, type);
132 dw_pcie_writel_dbi(pci, PCIE_ATU_CR2, PCIE_ATU_ENABLE); 139 dw_pcie_writel_dbi(pci, base, PCIE_ATU_CR2, PCIE_ATU_ENABLE);
133 } 140 }
134 141
135 /* 142 /*
@@ -138,10 +145,10 @@ void dw_pcie_prog_outbound_atu(struct dw_pcie *pci, int index, int type,
138 */ 145 */
139 for (retries = 0; retries < LINK_WAIT_MAX_IATU_RETRIES; retries++) { 146 for (retries = 0; retries < LINK_WAIT_MAX_IATU_RETRIES; retries++) {
140 if (pci->iatu_unroll_enabled) 147 if (pci->iatu_unroll_enabled)
141 val = dw_pcie_readl_unroll(pci, index, 148 val = dw_pcie_readl_unroll(pci, base, index,
142 PCIE_ATU_UNR_REGION_CTRL2); 149 PCIE_ATU_UNR_REGION_CTRL2);
143 else 150 else
144 val = dw_pcie_readl_dbi(pci, PCIE_ATU_CR2); 151 val = dw_pcie_readl_dbi(pci, base, PCIE_ATU_CR2);
145 152
146 if (val == PCIE_ATU_ENABLE) 153 if (val == PCIE_ATU_ENABLE)
147 return; 154 return;
@@ -188,13 +195,14 @@ void dw_pcie_setup(struct dw_pcie *pci)
188 u32 lanes; 195 u32 lanes;
189 struct device *dev = pci->dev; 196 struct device *dev = pci->dev;
190 struct device_node *np = dev->of_node; 197 struct device_node *np = dev->of_node;
198 void __iomem *base = pci->dbi_base;
191 199
192 ret = of_property_read_u32(np, "num-lanes", &lanes); 200 ret = of_property_read_u32(np, "num-lanes", &lanes);
193 if (ret) 201 if (ret)
194 lanes = 0; 202 lanes = 0;
195 203
196 /* set the number of lanes */ 204 /* set the number of lanes */
197 val = dw_pcie_readl_dbi(pci, PCIE_PORT_LINK_CONTROL); 205 val = dw_pcie_readl_dbi(pci, base, PCIE_PORT_LINK_CONTROL);
198 val &= ~PORT_LINK_MODE_MASK; 206 val &= ~PORT_LINK_MODE_MASK;
199 switch (lanes) { 207 switch (lanes) {
200 case 1: 208 case 1:
@@ -213,10 +221,10 @@ void dw_pcie_setup(struct dw_pcie *pci)
213 dev_err(pci->dev, "num-lanes %u: invalid value\n", lanes); 221 dev_err(pci->dev, "num-lanes %u: invalid value\n", lanes);
214 return; 222 return;
215 } 223 }
216 dw_pcie_writel_dbi(pci, PCIE_PORT_LINK_CONTROL, val); 224 dw_pcie_writel_dbi(pci, base, PCIE_PORT_LINK_CONTROL, val);
217 225
218 /* set link width speed control register */ 226 /* set link width speed control register */
219 val = dw_pcie_readl_dbi(pci, PCIE_LINK_WIDTH_SPEED_CONTROL); 227 val = dw_pcie_readl_dbi(pci, base, PCIE_LINK_WIDTH_SPEED_CONTROL);
220 val &= ~PORT_LOGIC_LINK_WIDTH_MASK; 228 val &= ~PORT_LOGIC_LINK_WIDTH_MASK;
221 switch (lanes) { 229 switch (lanes) {
222 case 1: 230 case 1:
@@ -232,5 +240,5 @@ void dw_pcie_setup(struct dw_pcie *pci)
232 val |= PORT_LOGIC_LINK_WIDTH_8_LANES; 240 val |= PORT_LOGIC_LINK_WIDTH_8_LANES;
233 break; 241 break;
234 } 242 }
235 dw_pcie_writel_dbi(pci, PCIE_LINK_WIDTH_SPEED_CONTROL, val); 243 dw_pcie_writel_dbi(pci, base, PCIE_LINK_WIDTH_SPEED_CONTROL, val);
236} 244}
diff --git a/drivers/pci/dwc/pcie-designware.h b/drivers/pci/dwc/pcie-designware.h
index 8f3dcb2b099b..fe93f7fbcd52 100644
--- a/drivers/pci/dwc/pcie-designware.h
+++ b/drivers/pci/dwc/pcie-designware.h
@@ -144,8 +144,9 @@ struct pcie_port {
144 144
145struct dw_pcie_ops { 145struct dw_pcie_ops {
146 u64 (*cpu_addr_fixup)(u64 cpu_addr); 146 u64 (*cpu_addr_fixup)(u64 cpu_addr);
147 u32 (*readl_dbi)(struct dw_pcie *pcie, u32 reg); 147 u32 (*readl_dbi)(struct dw_pcie *pcie, void __iomem *base, u32 reg);
148 void (*writel_dbi)(struct dw_pcie *pcie, u32 reg, u32 val); 148 void (*writel_dbi)(struct dw_pcie *pcie, void __iomem *base, u32 reg,
149 u32 val);
149 int (*link_up)(struct dw_pcie *pcie); 150 int (*link_up)(struct dw_pcie *pcie);
150}; 151};
151 152
@@ -163,8 +164,9 @@ struct dw_pcie {
163int dw_pcie_read(void __iomem *addr, int size, u32 *val); 164int dw_pcie_read(void __iomem *addr, int size, u32 *val);
164int dw_pcie_write(void __iomem *addr, int size, u32 val); 165int dw_pcie_write(void __iomem *addr, int size, u32 val);
165 166
166u32 dw_pcie_readl_dbi(struct dw_pcie *pci, u32 reg); 167u32 dw_pcie_readl_dbi(struct dw_pcie *pci, void __iomem *base, u32 reg);
167void dw_pcie_writel_dbi(struct dw_pcie *pci, u32 reg, u32 val); 168void dw_pcie_writel_dbi(struct dw_pcie *pci, void __iomem *base, u32 reg,
169 u32 val);
168int dw_pcie_link_up(struct dw_pcie *pci); 170int dw_pcie_link_up(struct dw_pcie *pci);
169int dw_pcie_wait_for_link(struct dw_pcie *pci); 171int dw_pcie_wait_for_link(struct dw_pcie *pci);
170void dw_pcie_prog_outbound_atu(struct dw_pcie *pci, int index, 172void dw_pcie_prog_outbound_atu(struct dw_pcie *pci, int index,
diff --git a/drivers/pci/dwc/pcie-hisi.c b/drivers/pci/dwc/pcie-hisi.c
index fd66a3199db7..409b54b95b5b 100644
--- a/drivers/pci/dwc/pcie-hisi.c
+++ b/drivers/pci/dwc/pcie-hisi.c
@@ -152,10 +152,11 @@ static int hisi_pcie_cfg_read(struct pcie_port *pp, int where, int size,
152 u32 reg_val; 152 u32 reg_val;
153 void *walker = &reg_val; 153 void *walker = &reg_val;
154 struct dw_pcie *pci = to_dw_pcie_from_pp(pp); 154 struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
155 void __iomem *base = pci->dbi_base;
155 156
156 walker += (where & 0x3); 157 walker += (where & 0x3);
157 reg = where & ~0x3; 158 reg = where & ~0x3;
158 reg_val = dw_pcie_readl_dbi(pci, reg); 159 reg_val = dw_pcie_readl_dbi(pci, base, reg);
159 160
160 if (size == 1) 161 if (size == 1)
161 *val = *(u8 __force *) walker; 162 *val = *(u8 __force *) walker;
@@ -177,19 +178,20 @@ static int hisi_pcie_cfg_write(struct pcie_port *pp, int where, int size,
177 u32 reg; 178 u32 reg;
178 void *walker = &reg_val; 179 void *walker = &reg_val;
179 struct dw_pcie *pci = to_dw_pcie_from_pp(pp); 180 struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
181 void __iomem *base = pci->dbi_base;
180 182
181 walker += (where & 0x3); 183 walker += (where & 0x3);
182 reg = where & ~0x3; 184 reg = where & ~0x3;
183 if (size == 4) 185 if (size == 4)
184 dw_pcie_writel_dbi(pci, reg, val); 186 dw_pcie_writel_dbi(pci, base, reg, val);
185 else if (size == 2) { 187 else if (size == 2) {
186 reg_val = dw_pcie_readl_dbi(pci, reg); 188 reg_val = dw_pcie_readl_dbi(pci, base, reg);
187 *(u16 __force *) walker = val; 189 *(u16 __force *) walker = val;
188 dw_pcie_writel_dbi(pci, reg, reg_val); 190 dw_pcie_writel_dbi(pci, base, reg, reg_val);
189 } else if (size == 1) { 191 } else if (size == 1) {
190 reg_val = dw_pcie_readl_dbi(pci, reg); 192 reg_val = dw_pcie_readl_dbi(pci, base, reg);
191 *(u8 __force *) walker = val; 193 *(u8 __force *) walker = val;
192 dw_pcie_writel_dbi(pci, reg, reg_val); 194 dw_pcie_writel_dbi(pci, base, reg, reg_val);
193 } else 195 } else
194 return PCIBIOS_BAD_REGISTER_NUMBER; 196 return PCIBIOS_BAD_REGISTER_NUMBER;
195 197
@@ -209,9 +211,10 @@ static int hisi_pcie_link_up_hip05(struct hisi_pcie *hisi_pcie)
209static int hisi_pcie_link_up_hip06(struct hisi_pcie *hisi_pcie) 211static int hisi_pcie_link_up_hip06(struct hisi_pcie *hisi_pcie)
210{ 212{
211 struct dw_pcie *pci = hisi_pcie->pci; 213 struct dw_pcie *pci = hisi_pcie->pci;
214 void __iomem *base = pci->dbi_base;
212 u32 val; 215 u32 val;
213 216
214 val = dw_pcie_readl_dbi(pci, PCIE_SYS_STATE4); 217 val = dw_pcie_readl_dbi(pci, base, PCIE_SYS_STATE4);
215 218
216 return ((val & PCIE_LTSSM_STATE_MASK) == PCIE_LTSSM_LINKUP_STATE); 219 return ((val & PCIE_LTSSM_STATE_MASK) == PCIE_LTSSM_LINKUP_STATE);
217} 220}