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authorStephen Warren2014-04-01 15:13:17 -0500
committerArnd Bergmann2014-04-24 08:37:08 -0500
commit9ef1af9ea28c23d0eaed97f7f5142788b6cf570a (patch)
tree1c1c017be7711c7ea7245f963ef88775a31b5007 /include
parent9ba71705706aa83bcd7f9b74ae2d167da934c951 (diff)
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dt: tegra: remove non-existent clock IDs
The Tegra124 clock DT binding currently provides 3 clocks that don't actually exist; 2 for NAND and one for UART5/UARTE. Delete these. While this is technically an incompatible DT ABI change, nothing could have used these clock IDs for anything practical, since the HW doesn't exist. Cc: <stable@vger.kernel.org> Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Diffstat (limited to 'include')
-rw-r--r--include/dt-bindings/clock/tegra124-car.h6
1 files changed, 3 insertions, 3 deletions
diff --git a/include/dt-bindings/clock/tegra124-car.h b/include/dt-bindings/clock/tegra124-car.h
index 8c1603b10665..433528ab5161 100644
--- a/include/dt-bindings/clock/tegra124-car.h
+++ b/include/dt-bindings/clock/tegra124-car.h
@@ -29,7 +29,7 @@
29/* 10 (register bit affects spdif_in and spdif_out) */ 29/* 10 (register bit affects spdif_in and spdif_out) */
30#define TEGRA124_CLK_I2S1 11 30#define TEGRA124_CLK_I2S1 11
31#define TEGRA124_CLK_I2C1 12 31#define TEGRA124_CLK_I2C1 12
32#define TEGRA124_CLK_NDFLASH 13 32/* 13 */
33#define TEGRA124_CLK_SDMMC1 14 33#define TEGRA124_CLK_SDMMC1 14
34#define TEGRA124_CLK_SDMMC4 15 34#define TEGRA124_CLK_SDMMC4 15
35/* 16 */ 35/* 16 */
@@ -83,7 +83,7 @@
83 83
84/* 64 */ 84/* 64 */
85#define TEGRA124_CLK_UARTD 65 85#define TEGRA124_CLK_UARTD 65
86#define TEGRA124_CLK_UARTE 66 86/* 66 */
87#define TEGRA124_CLK_I2C3 67 87#define TEGRA124_CLK_I2C3 67
88#define TEGRA124_CLK_SBC4 68 88#define TEGRA124_CLK_SBC4 68
89#define TEGRA124_CLK_SDMMC3 69 89#define TEGRA124_CLK_SDMMC3 69
@@ -97,7 +97,7 @@
97#define TEGRA124_CLK_TRACE 77 97#define TEGRA124_CLK_TRACE 77
98#define TEGRA124_CLK_SOC_THERM 78 98#define TEGRA124_CLK_SOC_THERM 78
99#define TEGRA124_CLK_DTV 79 99#define TEGRA124_CLK_DTV 79
100#define TEGRA124_CLK_NDSPEED 80 100/* 80 */
101#define TEGRA124_CLK_I2CSLOW 81 101#define TEGRA124_CLK_I2CSLOW 81
102#define TEGRA124_CLK_DSIB 82 102#define TEGRA124_CLK_DSIB 82
103#define TEGRA124_CLK_TSEC 83 103#define TEGRA124_CLK_TSEC 83