diff options
| -rw-r--r-- | arch/arm/boot/dts/dra7.dtsi | 39 |
1 files changed, 39 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/dra7.dtsi b/arch/arm/boot/dts/dra7.dtsi index 3c7e7f2b933a..eaeccaff67a3 100644 --- a/arch/arm/boot/dts/dra7.dtsi +++ b/arch/arm/boot/dts/dra7.dtsi | |||
| @@ -912,6 +912,45 @@ | |||
| 912 | clock-names = "sysclk"; | 912 | clock-names = "sysclk"; |
| 913 | #phy-cells = <0>; | 913 | #phy-cells = <0>; |
| 914 | }; | 914 | }; |
| 915 | |||
| 916 | pcie1_phy: pciephy@4a094000 { | ||
| 917 | compatible = "ti,phy-pipe3-pcie"; | ||
| 918 | reg = <0x4A094000 0x80>, /* phy_rx */ | ||
| 919 | <0x4A094400 0x64>; /* phy_tx */ | ||
| 920 | reg-names = "phy_rx", "phy_tx"; | ||
| 921 | ctrl-module = <&omap_control_pcie1phy>; | ||
| 922 | clocks = <&dpll_pcie_ref_ck>, | ||
| 923 | <&dpll_pcie_ref_m2ldo_ck>, | ||
| 924 | <&optfclk_pciephy1_32khz>, | ||
| 925 | <&optfclk_pciephy1_clk>, | ||
| 926 | <&optfclk_pciephy1_div_clk>, | ||
| 927 | <&optfclk_pciephy_div>; | ||
| 928 | clock-names = "dpll_ref", "dpll_ref_m2", | ||
| 929 | "wkupclk", "refclk", | ||
| 930 | "div-clk", "phy-div"; | ||
| 931 | #phy-cells = <0>; | ||
| 932 | ti,hwmods = "pcie1-phy"; | ||
| 933 | }; | ||
| 934 | |||
| 935 | pcie2_phy: pciephy@4a095000 { | ||
| 936 | compatible = "ti,phy-pipe3-pcie"; | ||
| 937 | reg = <0x4A095000 0x80>, /* phy_rx */ | ||
| 938 | <0x4A095400 0x64>; /* phy_tx */ | ||
| 939 | reg-names = "phy_rx", "phy_tx"; | ||
| 940 | ctrl-module = <&omap_control_pcie1phy>; | ||
| 941 | clocks = <&dpll_pcie_ref_ck>, | ||
| 942 | <&dpll_pcie_ref_m2ldo_ck>, | ||
| 943 | <&optfclk_pciephy2_32khz>, | ||
| 944 | <&optfclk_pciephy2_clk>, | ||
| 945 | <&optfclk_pciephy2_div_clk>, | ||
| 946 | <&optfclk_pciephy_div>; | ||
| 947 | clock-names = "dpll_ref", "dpll_ref_m2", | ||
| 948 | "wkupclk", "refclk", | ||
| 949 | "div-clk", "phy-div"; | ||
| 950 | #phy-cells = <0>; | ||
| 951 | ti,hwmods = "pcie2-phy"; | ||
| 952 | status = "disabled"; | ||
| 953 | }; | ||
| 915 | }; | 954 | }; |
| 916 | 955 | ||
| 917 | omap_dwc3_1@48880000 { | 956 | omap_dwc3_1@48880000 { |