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authorElena Demikhovsky2015-01-22 04:01:36 -0600
committerElena Demikhovsky2015-01-22 04:01:36 -0600
commit9cb8df2c7541ed15cc3cf545e215a5ceefdb61c2 (patch)
treee0246d7dd3841c8623fd869230594f5d94757e16
parentcdce03426d357164c1d15154e251d22e02cc8bc1 (diff)
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Fixed a comment
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@226806 91177308-0d34-0410-b5e6-96231b3b80d8
-rw-r--r--lib/CodeGen/SelectionDAG/DAGCombiner.cpp2
1 files changed, 1 insertions, 1 deletions
diff --git a/lib/CodeGen/SelectionDAG/DAGCombiner.cpp b/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
index 4a9ae20066..6bd38ae616 100644
--- a/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
+++ b/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
@@ -9497,7 +9497,7 @@ SDValue DAGCombiner::ReduceLoadOpStoreWidth(SDNode *N) {
9497 unsigned MSB = BitWidth - Imm.countLeadingZeros() - 1; 9497 unsigned MSB = BitWidth - Imm.countLeadingZeros() - 1;
9498 unsigned NewBW = NextPowerOf2(MSB - ShAmt); 9498 unsigned NewBW = NextPowerOf2(MSB - ShAmt);
9499 EVT NewVT = EVT::getIntegerVT(*DAG.getContext(), NewBW); 9499 EVT NewVT = EVT::getIntegerVT(*DAG.getContext(), NewBW);
9500 // The narowwing should be profitable, the load/store operation should be 9500 // The narrowwing should be profitable, the load/store operation should be
9501 // legal (or custom) and the store size should be equal to the NewVT width. 9501 // legal (or custom) and the store size should be equal to the NewVT width.
9502 while (NewBW < BitWidth && 9502 while (NewBW < BitWidth &&
9503 (NewVT.getStoreSizeInBits() != NewBW || 9503 (NewVT.getStoreSizeInBits() != NewBW ||