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* ci: remame WD to OPTEE_OS_TO_TESTHEADmasterJerome Forissier2024-03-221-8/+8
| | | | | | | | | | | WD is not a very good variable name, it stands for "working directory" but does not express what this directory contains. Use OPTEE_OS_TO_TEST instead, since it is actually the optee_os directory checked out by CI (i.e., the current branch or PR to test). Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org> Acked-by: Jens Wiklander <jens.wiklander@linaro.org> Reviewed-by: Joakim Bech <joakim.bech@linaro.org>
* ci: update QEMUv8 jobs to use newer Docker imageJerome Forissier2024-03-221-8/+8
| | | | | | | | | | | Update the QEMUv8 jobs to use the newer Docker image: jforissier/optee_os_ci:qemu_check, which has a more generic script to clone the OP-TEE environment [1]. Link: https://github.com/jforissier/docker_optee_os_ci/blob/qemu_check/get_optee.sh [1] Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org> Acked-by: Jens Wiklander <jens.wiklander@linaro.org> Reviewed-by: Joakim Bech <joakim.bech@linaro.org>
* core: kernel: Fix typo in __do_panic()Alvin Chang2024-03-211-1/+1
| | | | | | | Must be "preemption" instead of "prehemption". Signed-off-by: Alvin Chang <alvinga@andestech.com> Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
* drivers: regulator: use mutex_pm_awareEtienne Carriere2024-03-202-24/+9
| | | | | | | | Use newly introduced struct mutex_pm_aware semaphore to protect regulator accesses. Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org> Signed-off-by: Etienne Carriere <etienne.carriere@foss.st.com>
* drivers: clk: replace clock main spinlock with a mutexEtienne Carriere2024-03-202-16/+26
| | | | | | | | | | | | | | | | | Change clock framework lock from an interrupts masked spinning lock to a mutex. This allows the clock framework to better handle slow stabilizing clocks as PLLs without masking the system interrupt which can have side effects on the REE or even the TEE. To support clock accesses during low power state transition sequences while non-secure world is no operating, the lock is not taken when the execution is not in the scope of a TEE thread. This change is not expected to impact supported platforms that currently only access clock operation from thread contexts or atomic PM sequences. Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org> Signed-off-by: Etienne Carriere <etienne.carriere@foss.st.com>
* core: kernel: mutex compliant with PM sequencesEtienne Carriere2024-03-202-0/+77
| | | | | | | | | | | | | | | Add mutex_pm_aware_*() functions for mutex used on resources accessed at runtime using a conventional mutex and also during low power sequences that execute in a non-thread context. This change defines MUTEX_PM_AWARE_INITIALIZER macro from a new header file (mutex_pm_aware.h) instead of existing mutex.h to prevent a circular dependency between spinlock.h (requires thread.h), thread.h (indirectly includes mutex.h) and mutex.h (that would depend on spinlock.h for definition of the SPINLOCK_UNLOCK macro ). Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org> Signed-off-by: Etienne Carriere <etienne.carriere@foss.st.com>
* core: kernel: thread spin lockingEtienne Carriere2024-03-201-0/+22
| | | | | | | | | | | | | | Add thread_spin_lock() and thread_spin_unlock() for active spinning locks in situation where we need an exclusive lock in a thread and interruptible context even at the cost of a high CPU usage. These function are intended to be used in thread context hence they assert being executed in such a context. This is to prevent on mistakenly spin in an atomic context which potentially leads to a deadlock situation. Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org> Signed-off-by: Etienne Carriere <etienne.carriere@foss.st.com>
* core: spmc, sp: cleanup FF-A ID handlingBalint Dobszay2024-03-204-59/+125
| | | | | | | | | | | | | | | | | | When OP-TEE implements the S-EL1 SPMC, from an FF-A point-of-view the core OP-TEE functionality is running in a logical SP that resides at the same exception level as the SPMC. This means that the SPMC and the SP should have separate FF-A IDs, i.e. the SPMC ID and a normal endpoint ID for the SP. The SPMC ID is described in the SPMC manifest which gets parsed by the SPMD, so this ID should be queried from the SPMD. OP-TEE's endpoint ID is assigned by the SPMC. Currently OP-TEE's FF-A endpoint ID and the SPMC ID are mixed together and hardcoded, this patch implements the correct ID handling mechanism as described above. Acked-by: Etienne Carriere <etienne.carriere@foss.st.com> Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org> Signed-off-by: Balint Dobszay <balint.dobszay@arm.com>
* core: riscv: Prepare SATP for each hartAlvin Chang2024-03-204-7/+21
| | | | | | | | | | | | | | | | | To support multiple harts environment, we have allocated root page table for each hart. Further more, we need to prepare value of CSR SATP, which holds the physical page number (PPN) of the root page table, for each hart. This commit enlarges the "struct core_mmu_config" for RISC-V architecture to hold the value of CSR SATP for all the harts. In early boot stage, each hart should initialize its CSR SATP from "struct core_mmu_config". Signed-off-by: Alvin Chang <alvinga@andestech.com> Reviewed-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Marouene Boubakri <marouene.boubakri@nxp.com> Acked-by: Etienne Carriere <etienne.carriere@foss.st.com>
* core: riscv: Allocate root page table for each hartAlvin Chang2024-03-201-3/+17
| | | | | | | | | | | | | To support multiple hart environment, each hart must have its dedicated root page table. This commit enlarges the root page table. Also, when the primary hart initializes the page table, we also copy the contents of its root page table to the secondary harts' root page tables. Therefore, all the harts have initial page tables at the boot time. Signed-off-by: Alvin Chang <alvinga@andestech.com> Reviewed-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Marouene Boubakri <marouene.boubakri@nxp.com> Acked-by: Etienne Carriere <etienne.carriere@foss.st.com>
* ci: qemuv8: add test case with CFG_WITH_PAGER=yJerome Forissier2024-03-191-0/+1
| | | | | | | Add a "make check" test with pager enabled on QEMUv8. Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org> Reviewed-by: Joakim Bech <joakim.bech@linaro.org>
* core: arm64: increase STACK_ABT_SIZE from 1024 to 3072 when log level is 0Jerome Forissier2024-03-191-4/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When adding "make check CFG_WITH_PAGER=y CFG_TEE_CORE_LOG_LEVEL=0" to the QEMUv8 CI job, I noticed that OP-TEE fails to boot and hangs with no message printed on the console. The root cause is memory corruption of the translation tables triggered by a stack overflow. Indeed, the pager uses the abort stack to handle unmapped pages, and therefore it requires quite a bit of stack space. The log level is not very relevant. Therefore, fix the issue by removing the particular case for log level 0. More debugging info: build$ make -j$(nproc) CFG_WITH_PAGER=y CFG_TEE_CORE_LOG_LEVEL=0 \ CFG_CORE_ASLR=n build$ aarch64-linux-gnu-nm -n ../optee_os/out/arm/core/tee.elf ... 000000000e115000 B __nozi_start 000000000e115000 b thread_user_kdata_page 000000000e116000 b xlat_tables_ul1 000000000e118000 b xlat_tables 000000000e11d000 b base_xlation_table 000000000e11d100 B __nozi_end 000000000e11d100 B __nozi_stack_start 000000000e11d100 b stack_abt 000000000e11e200 B stack_tmp ... build$ make run-only optee_qemuv8$ gdb-multiarch (gdb) symbol-file optee_os/out/arm/core/tee.elf (gdb) target remote localhost:1234 (gdb) p sizeof(base_xlation_table) $1 = 256 (gdb) watch *(char [256]*)base_xlation_table (gdb) c # 5 times Thread 1 hit Hardware watchpoint 1: *(char [256]*)base_xlation_table (gdb) bt At this point the call stack is: hash_sha256_check() fobj_load_page() pager_deploy_page() pager_get_page() tee_pager_handle_fault() abort_handler() el1_sync_abort() This code is indeed not supposed to touch base_xlation_table, it does so due to the overflow of stack_abt. Suggested-by: Jens Wikander <jens.wiklander@linaro.org> Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org> Acked-by: Joakim Bech <joakim.bech@linaro.org> Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
* core: replace REGISTER_TIME_SOURCE()Jens Wiklander2024-03-186-82/+21
| | | | | | | | | | | | | | Remove REGISTER_TIME_SOURCE() and implement tee_time_get_sys_time() and tee_time_get_sys_time_protection_level() directly in the file where REGISTER_TIME_SOURCE() was used previously. By avoiding indirect calls the linker can optimize the dependency tree properly and we can remove the DECLARE_KEEP_PAGER() directive needed for arm_cntpct_time_source. Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org> Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com> Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>
* core: riscv: Apply SM-based boot flow for secondary hartsAlvin Chang2024-03-151-0/+5
| | | | | | | | | | When the system adopts M-mode secure monitor based solution, the secondary harts need to hand over the control back to the secure monitor after the initial boot sequence. Add related code for this purpose. Signed-off-by: Alvin Chang <alvinga@andestech.com> Reviewed-by: Marouene Boubakri <marouene.boubakri@nxp.com>
* core: riscv: Do not restrict primary hart to hart ID 0 onlyAlvin Chang2024-03-151-1/+13
| | | | | | | | | | | | | | | | | | The ID of primary hart should not be restricted to zero. Thus, determining primary hart and secondart harts by zero hart ID is not feasible. We refer to RISC-V linux kernel [1] to fix this issue, by adding a "hart_lottery" variable. The first hart who enters OP-TEE will win the lottery, atomically increment this variable, and be the primary hart. Other harts enter OP-TEE later won't win the lottery, so they execute the secondary boot sequence. [1]: https://github.com/torvalds/linux/blob/v6.7/arch/riscv/kernel/head.S#L244 Signed-off-by: Alvin Chang <alvinga@andestech.com> Reviewed-by: Marouene Boubakri <marouene.boubakri@nxp.com>
* core: riscv: Change the condition of communication with untrusted domainAlvin Chang2024-03-151-1/+1
| | | | | | | | Use CFG_RISCV_WITH_M_MODE_SM to determine if OP-TEE uses M-mode secure monitor based solution to communicate with the untrusetd domain. Signed-off-by: Alvin Chang <alvinga@andestech.com> Reviewed-by: Marouene Boubakri <marouene.boubakri@nxp.com>
* riscv: plat-virt: Set CFG_RISCV_WITH_M_MODE_SM as 'y'Alvin Chang2024-03-151-0/+1
| | | | | | | | | In RISC-V QEMU virtual platform, OP-TEE OS uses M-mode secure monitor based solution to communicate with the untrusted domain. Therefore, set CFG_RISCV_WITH_M_MODE_SM to 'y' in its configuration file. Signed-off-by: Alvin Chang <alvinga@andestech.com> Reviewed-by: Marouene Boubakri <marouene.boubakri@nxp.com>
* core: riscv: Add CFG_RISCV_WITH_M_MODE_SM and dependency checkingAlvin Chang2024-03-151-0/+7
| | | | | | | | | | | | | | OP-TEE may communicate with the untrusted domain by different solutions, such as M-mode secure monitor based solution, or direct messaging based solution. This commit adds CFG_RISCV_WITH_M_MODE_SM to indicate that OP-TEE uses M-mode secure monitor based solution for the communication. The CFG_RISCV_WITH_M_MODE_SM should depend on CFG_RISCV_S_MODE and CFG_RISCV_SBI, since we are using "ecall" to trap into M-mode secure monitor. Signed-off-by: Alvin Chang <alvinga@andestech.com> Reviewed-by: Marouene Boubakri <marouene.boubakri@nxp.com>
* core: riscv: Apply mask/unmask exceptions when operating page tableAlvin Chang2024-03-151-0/+6
| | | | | | | | | Add missing thread_{mask/unmask}_exceptions() when we operate the page table. This is referenced from ARM architecture. Signed-off-by: Alvin Chang <alvinga@andestech.com> Tested-by: Marouene Boubakri <marouene.boubakri@nxp.com> Reviewed-by: Marouene Boubakri <marouene.boubakri@nxp.com>
* core: riscv: Apply STATUS helper for RPC resumeAlvin Chang2024-03-153-13/+33
| | | | | | | | | | | Since RPC resume is a kind of exception return, we invoke xstatus_for_xret() to prepare the CSR STATUS for exception return. But the actual value of STATUS when calling thread_rpc() is still saved in stack. This is to unify the behavior between RPC suspend and resume. Signed-off-by: Alvin Chang <alvinga@andestech.com> Tested-by: Marouene Boubakri <marouene.boubakri@nxp.com> Reviewed-by: Marouene Boubakri <marouene.boubakri@nxp.com>
* core: riscv: Apply exception return to handle_user_mode_panic()Alvin Chang2024-03-151-1/+1
| | | | | | | | | | Now thread_exit_user_mode() executes exception return to kernel mode. Invoke xstatus_for_xret() helper function to prepare CSR STATUS for exception return. Signed-off-by: Alvin Chang <alvinga@andestech.com> Tested-by: Marouene Boubakri <marouene.boubakri@nxp.com> Reviewed-by: Marouene Boubakri <marouene.boubakri@nxp.com>
* core: riscv: Refine thread trap handlerAlvin Chang2024-03-152-13/+43
| | | | | | | | | | | | In order to support SMP, we made change on CSR SCRATCH from kernel stack pointer to be kernel TP(thread_core_local). So that we can get TP from SCRATCH easily in trap handler when the thread is in user mode. We also save/restore CSR IE, kernel GP and SP so that we can handle task migration to another hart. Signed-off-by: Alvin Chang <alvinga@andestech.com> Tested-by: Marouene Boubakri <marouene.boubakri@nxp.com> Reviewed-by: Marouene Boubakri <marouene.boubakri@nxp.com>
* core: riscv: Refine thread enter/exit user modeAlvin Chang2024-03-152-27/+44
| | | | | | | | | | | | | Now when thread is in user mode, the kernel TP is saved into CSR SCRATCH instead of into kernel stack. The IE is also considered since it contains masks of different exceptions. Apply exception return to thread_exit_user_mode() to let hart correctly back to kernel mode from exception. Signed-off-by: Alvin Chang <alvinga@andestech.com> Tested-by: Marouene Boubakri <marouene.boubakri@nxp.com> Reviewed-by: Marouene Boubakri <marouene.boubakri@nxp.com>
* core: riscv: Apply exception return to resume threadAlvin Chang2024-03-156-11/+87
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In current implementation, the thread is resumed by function return. It is not suitable for all scenarios, especially when the thread should be resumed to user mode. The kernel mode can not return to user mode by pure function return. This commit applies exception return to resume the thread. The EPC and IE are added into thread context. The xstatus_for_xret() helper function is added to prepare the value of CSR STATUS for exception return. Currently we only consider PIE(previous interrupt-enable) and PP(previous privilege mode) for exception return. We clear thread context when the context is reinitialized, enable native interrupt, and setup kernel GP/TP. The thread_resume() now takes care of restoring CSR EPC, STATUS, IE, SCRATCH and all general-purpose registers. Finally it executes exception return to target privilege mode encoded in CSR STATUS. The registers GP and TP are also restored since user mode may use them. This commit also modify the usage of CSR SCRATCH. In current implementation the SCRATCH is used to save kernel stack pointer when the thread is in user mode. The value of TP, which stores thread_core_local structure, is saved into kernel stack before entering user mode. The trap handler can then get TP(thread_core_local) from kernel stack. This is not suitable for SMP system, since the thread might be resumed to another core, and that core gets wrong TP from kernel stack. Fix it by directly storing TP into CSR SCRATCH. Signed-off-by: Alvin Chang <alvinga@andestech.com> Reviewed-by: Marouene Boubakri <marouene.boubakri@nxp.com> Tested-by: Marouene Boubakri <marouene.boubakri@nxp.com>
* core: boot: fix memtag init sequenceOlivier Deprez2024-03-143-5/+26
| | | | | | | | | | | | | | | | | | | | | | | | | Based on following observations on FVP: With boot_init_memtag called before MMU enable, DC GZA hits an alignment fault. This is because all accesses are of device type when MMU is off. Arm ARM states for DC GZA: "If the memory region being modified is any type of Device memory, this instruction can give an alignment fault." Moving boot_init_memtag after MMU enable, DC GZA hits a permission fault, this is because the range returned by core_mmu_get_secure_memory consists of pages mapped RO (text sections) and then RW (data sections) consecutively. DC GZA is a write instruction executed towards an RO page leading to a fault. To fix this, split boot_init_memtag into two halves: - Setup memtag operations before MMU is enabled such that MAIR_EL1 is properly configured for normal tagged memory. - Clear core TEE RW sections after MMU is enabled. Closes: https://github.com/OP-TEE/optee_os/issues/6649 Signed-off-by: Olivier Deprez <olivier.deprez@arm.com> [jw rewrote boot_clear_memtag()] Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org> Acked-by: Jerome Forissier <jerome.forissier@linaro.org> Acked-by: Etienne Carriere <etienne.carriere@foss.st.com>
* ta: pkcs11: Clarify context reference in step_symm_operation()Etienne Carriere2024-03-141-3/+3
| | | | | | | | | | | Function step_symm_operation() defines a local variable to reference the session processing context but uses both session reference and this local variable which can be confusing when reading the code. Change the implementation to only use the local variable for consistency. No functional changes. Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org> Signed-off-by: Etienne Carriere <etienne.carriere@foss.st.com>
* core: introduce CFG_NOTIF_TEST_WDJens Wiklander2024-03-142-1/+6
| | | | | | | | Add CFG_NOTIF_TEST_WD to control if the notification based test watchdog should be enabled. Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org> Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com>
* core: add CFG_CALLOUTJens Wiklander2024-03-144-2/+8
| | | | | | | | | Add CFG_CALLOUT with a default value assigned from CFG_CORE_ASYNC_NOTIF to control if the callout service should be enabled. Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org> Acked-by: Jerome Forissier <jerome.forissier@linaro.org> Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com>
* core: notif: assert callback is unpagedJens Wiklander2024-03-141-1/+1
| | | | | | | | | | Add an assert that the atomic_cb() pointer in notif_register_driver() points to an unpaged address since the callback function will be called from an interrupt handler and must not be paged. Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org> Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org> Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com>
* core: callout: assert callback is unpagedJens Wiklander2024-03-141-1/+1
| | | | | | | | | | Add an assert that the callback parameter passed to callout_add() points to an unpaged address since the callback function will be called from an interrupt handler and must not be paged. Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org> Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org> Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com>
* core: add missing DECLARE_KEEP_PAGER()Jens Wiklander2024-03-143-0/+5
| | | | | | | | | | | | | Adds missing DECLARE_KEEP_PAGER() for timer_desc, timer_itr_cb(), arm_cntpct_time_source, wd_ndrv_atomic_cb(), and periodic_callback(). All possibly accessed from an interrupt handler and must not be paged. Fixes: cf707bd0d695 ("core: add callout service") Fixes: 5b7afacfba96 ("core: arm64: implement timer_init_callout_service()") Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org> Tested-by: Jerome Forissier <jerome.forissier@linaro.org> (vexpress-qemu_armv8a) Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org> Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com>
* plat-synquacer: use cpu_spin_lock_xsave() and friendEtienne Carriere2024-03-141-8/+5
| | | | | | | | | | | | | | Change RNG PTA implementation for synquacer platform to use helper functions cpu_spin_lock_xsave() and cpu_spin_unlock_xrestore() instead of calling thread_mask_exceptions()/cpu_spin_lock() pair and thread_set_exceptions()/cpu_spin_unlock() pair. This makes the implementation more consistent. No functional change. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org> Signed-off-by: Etienne Carriere <etienne.carriere@foss.st.com>
* core: arm: mm: use thread_unmask_exceptions() where applicableEtienne Carriere2024-03-141-1/+1
| | | | | | | | | | | | | Change cache_op_outer() to use thread_unmask_exceptions() instead of thread_set_exceptions() as the function unmasks interruptions it previously masked with thread_set_exceptions(). This change makes the implementation more consistent. No functional change. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org> Signed-off-by: Etienne Carriere <etienne.carriere@foss.st.com>
* core: arm: use cpu_spin_lock_xsave() in generic timer implementationEtienne Carriere2024-03-141-10/+4
| | | | | | | | | | | | | | Change generic timer driver for Arm 64bit architecture to use helper functions cpu_spin_lock_xsave() and cpu_spin_unlock_xrestore() instead of calling thread_mask_exceptions()/cpu_spin_lock() pair and thread_set_exceptions()/cpu_spin_unlock() pair. This makes the implementation more consistent with the rest of the source tree. No functional change. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org> Signed-off-by: Etienne Carriere <etienne.carriere@foss.st.com>
* ta: remoteproc: allow remoteproc_load_fw re-entranceArnaud Pouliquen2024-03-121-0/+4
| | | | | | | | | | | | | | | Instead of returning an error if the TA_RPROC_CMD_LOAD_FW is called several times, just return TEE_SUCCESS if the firmware is already loaded. This commit is the result of a discussion on Linux Kernel mailing list: https://lore.kernel.org/lkml/ZeCujRgH%2FodzU9og@p14s/ Fixes: fcf382e2440c ("ta: remoteproc: add remote processor Trusted Application") Suggested-by: Mathieu Poirier <mathieu.poirier@linaro.org> Signed-off-by: Arnaud Pouliquen <arnaud.pouliquen@foss.st.com> Acked-by: Jerome Forissier <jerome.forissier@linaro.org> Acked-by: Etienne Carriere <etienne.carriere@foss.st.com>
* core: notif_send_async(): remove debug printJens Wiklander2024-03-111-1/+0
| | | | | | | | | | Remove the debug print D/TC:0 notif_send_async:93 0x0 from notif_send_async(). Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org> Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org> Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com>
* core: tests: add a notification test watchdogJens Wiklander2024-03-112-0/+127
| | | | | | | | | | | | | | | | | Add test watchdog for asynchronous notifications where a timer interrupt triggers an asynchronous notification in the normal world kernel driver. The normal world kernel driver responds by doing a OPTEE_MSG_CMD_DO_BOTTOM_HALF call for bottom half processing. The watchdog checks that there has been a response for each timer interrupt but doesn't take any measures if a response is missing. The purpose of the test is to exercise asynchronous notifications. Feedback is limited to debug prints on the UART so eventual regressions will not get caught by xtest unless there is a crash. Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org> Acked-by: Jerome Forissier <jerome.forissier@linaro.org> Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com>
* plat-vexpress: qemu_armv8: define IT_SEC_PHY_TIMERJens Wiklander2024-03-111-0/+1
| | | | | | | | Define the interrupt ID of the secure physical timer. Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org> Acked-by: Jerome Forissier <jerome.forissier@linaro.org> Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com>
* plat-vexpress: initialize callout serviceJens Wiklander2024-03-111-0/+12
| | | | | | | | | | If physical timer interrupt is defined, IT_SEC_PHY_TIMER, and OP-TEE isn't virtualized, CFG_CORE_SEL2_SPMC isn't defined, initialize the callout service using that interrupt ID. Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org> Acked-by: Jerome Forissier <jerome.forissier@linaro.org> Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com>
* core: arm64: implement timer_init_callout_service()Jens Wiklander2024-03-112-0/+67
| | | | | | | | | Implement timer_init_callout_service() needed to initialize and drive the callout service. Only available in AArch64. Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org> Acked-by: Jerome Forissier <jerome.forissier@linaro.org> Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com>
* core: define generic callout service initializerJens Wiklander2024-03-111-1/+20
| | | | | | | | | | | | Add a generic timer_init_callout_service() to be implemented in architecture or platform specific code. The function shall provide an implementation of the abstract timer interface needed by the callout service and register a timer interrupt callback to call callout_service_cb(). Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org> Acked-by: Jerome Forissier <jerome.forissier@linaro.org> Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com>
* core: add callout serviceJens Wiklander2024-03-113-0/+323
| | | | | | | | | | | | | | | | Add a callout service to call registered callback functions at a given time from now. A callout is periodic or oneshot depending on how the callback function returns. Callback functions execute in nexus and interrupt context. The callout service is initialized with callout_service_init() and depends on an abstract timer interface to manage the hardware timer. callout_service_cb() needs to be called from the timer interrupt handler to drive the callout service. Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org> Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org> Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com>
* core: arm64: add {read,write}_cntps_cval()Jens Wiklander2024-03-111-0/+2
| | | | | | | | | Add read_cntps_cval() and write_cntps_cval() to access CNTPS_CVAL_EL1, Counter-timer Physical Secure Timer CompareValue register. Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org> Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org> Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com>
* drivers: clk: clk-stm32mp13: fix memory corruption on oscillator parentEtienne Carriere2024-03-111-0/+6
| | | | | | | | | | | | | Fix oscillators struct clk instances for STM32MP13 clock driver. These clocks have 1 parent that is set during driver initialization, based on device tree content, whereas referred bugged commit defined 0 parents and did not allocate memory for the parent reference. Fixes: 95f2142bf848 ("drivers: clk: clk-stm32mp13: don't gate/ungate oscillators not wired") Tested-by: Thomas Bourgoin <thomas.bourgoin@foss.st.com> Acked-by: Thomas Bourgoin <thomas.bourgoin@foss.st.com> Acked-by: Gatien Chevallier <gatien.chevallier@foss.st.com> Signed-off-by: Etienne Carriere <etienne.carriere@foss.st.com>
* plat-synquacer: add initialization value to local variablesEtienne Carriere2024-03-111-11/+15
| | | | | | | | | | | | Add missing initialization value to local variables in synquacer platform RNG driver to better comply with OP-TEE OS coding style and prevent developers from being confused when using this example as a example. No functional change. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Etienne Carriere <etienne.carriere@foss.st.com>
* drivers: regulator: do not cache voltage level valuePatrick Delaunay2024-03-112-18/+23
| | | | | | | | | | | | Always read current voltage level from the device instead of caching the level in struct regulator. This fixes issues for when the regulator level value depends on the parent regulator (supply). It is up the regulator drivers to cache or not this value in their private data if applicable. Fixes: 1a3d3273040b ("drivers: regulator framework") Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com> Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com>
* core: add __must_check attribute to cpu_spin_lock_xsave()Jens Wiklander2024-03-071-5/+6
| | | | | | | | | | | cpu_spin_lock_xsave() masks exceptions, takes the spinlock and returns previous exception state to be restored by cpu_spin_unlock_xrestore(). The previously returned exception state must always be supplied so add the __must_check attribute to cpu_spin_lock_xsave() and its debug variants. Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org> Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>
* core: kernel: add timeout_elapsed_us()Etienne Carriere2024-03-072-0/+22
| | | | | | | | | | | Add API function timeout_elapsed_us() to measure to time since or until an initialized timeout reference elapses. This function relies on other timeout_*() API functions are therefore depends on CFG_CORE_HAS_GENERIC_TIMER being enabled. Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org> Signed-off-by: Etienne Carriere <etienne.carriere@foss.st.com>
* core: kernel: factorize delay and timeout implementationEtienne Carriere2024-03-073-18/+32
| | | | | | | | | | | | Factorize RISC-V and Arm architectures implementation of delay and timeout API functions into generic core kernel source directory. Architecture or platform only need to implement timer tick count read function delay_cnt_read() and timer tick frequency (in Hertz) delay_cnt_freq() which is related to CFG_CORE_HAS_GENERIC_TIMER support. Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org> Signed-off-by: Etienne Carriere <etienne.carriere@foss.st.com>
* core: riscv: force enable of CFG_CORE_HAS_GENERIC_TIMEREtienne Carriere2024-03-071-0/+3
| | | | | | | | | | | Ensure CFG_CORE_HAS_GENERIC_TIMER is enabled for RISC-V architecture since the current implementation provides the necessary routines in delay_arch.h outside any configuration switch directive. This change clarifies riscv based platforms configuration that previously depended on CFG_CORE_HAS_GENERIC_TIMER default enabling from mk/config.mk. Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org> Signed-off-by: Etienne Carriere <etienne.carriere@foss.st.com>
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