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authorPrasad Konnur2021-03-30 05:37:14 -0500
committerAnkur2021-03-30 09:28:42 -0500
commit3f71b9403f00a92883db757244b7632172b67240 (patch)
tree39a651730c37ffa7420b0bd758f1c2cdd1fa9526
parentaf6f2d416001d9a457c3399be7f80ecbff5fc2e8 (diff)
downloadpdk-3f71b9403f00a92883db757244b7632172b67240.tar.gz
pdk-3f71b9403f00a92883db757244b7632172b67240.tar.xz
pdk-3f71b9403f00a92883db757244b7632172b67240.zip
fixed build issue for awr294x
Signed-off-by: Prasad Konnur <prasadkonnur@ti.com>
Diffstat
-rw-r--r--packages/ti/build/awr294x/linker_c66_freertos.cmd89
-rw-r--r--packages/ti/build/awr294x/linker_r5_freertos.lds92
-rw-r--r--packages/ti/build/makerules/component.mk2
-rw-r--r--packages/ti/drv/hwa/test/awr294x/linker_c66.cmd12
-rw-r--r--packages/ti/drv/hwa/test/awr294x/linker_r5f.cmd11
-rw-r--r--packages/ti/drv/mibspi/test/slavemode/awr294x/dss.cfg82
-rw-r--r--packages/ti/drv/mibspi/test/slavemode/awr294x/dss_spi_linker.cmd94
-rw-r--r--packages/ti/drv/mibspi/test/slavemode/awr294x/mss.cfg126
-rw-r--r--packages/ti/drv/mibspi/test/slavemode/awr294x/mss_spi_linker.cmd74
-rw-r--r--packages/ti/drv/mibspi/test/slavemode/awr294x/r5_mpu.xs118
-rw-r--r--packages/ti/kernel/freertos/config/awr294x/c66/FreeRTOSConfig.h172
-rw-r--r--packages/ti/kernel/freertos/config/awr294x/c66/FreeRTOSConfig_c66xdsp_1.h50
-rw-r--r--packages/ti/kernel/freertos/config/awr294x/c66/FreeRTOS_POSIX_portable.h37
-rw-r--r--packages/ti/kernel/freertos/config/awr294x/r5f/FreeRTOSConfig.h173
-rw-r--r--packages/ti/kernel/freertos/config/awr294x/r5f/FreeRTOSConfig_mcu1_0.h50
-rw-r--r--packages/ti/kernel/freertos/config/awr294x/r5f/FreeRTOS_POSIX_portable.h37
-rw-r--r--packages/ti/osal/soc/awr294x/osal_soc.h5
17 files changed, 1223 insertions, 1 deletions
diff --git a/packages/ti/build/awr294x/linker_c66_freertos.cmd b/packages/ti/build/awr294x/linker_c66_freertos.cmd
new file mode 100644
index 000000000..a7ec6183c
--- /dev/null
+++ b/packages/ti/build/awr294x/linker_c66_freertos.cmd
@@ -0,0 +1,89 @@
1/*
2 * Copyright (c) 2016, Texas Instruments Incorporated
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 *
9 * * Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 *
12 * * Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 *
16 * * Neither the name of Texas Instruments Incorporated nor the names of
17 * its contributors may be used to endorse or promote products derived
18 * from this software without specific prior written permission.
19 *
20 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
21 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
22 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
23 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
24 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
25 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
26 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
27 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
28 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
29 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
30 * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
31 */
32
33#define L1P_CACHE_SIZE (16*1024)
34#define L1D_CACHE_SIZE (16*1024)
35
36MEMORY
37{
38PAGE 0:
39
40#if (L1P_CACHE_SIZE < 0x8000)
41 L1PSRAM: o = 0x00E00000, l = (0x00008000 - L1P_CACHE_SIZE)
42#endif
43#if (L1D_CACHE_SIZE < 0x8000)
44 L1DSRAM: o = 0x00F00000, l = (0x00008000 - L1D_CACHE_SIZE)
45#endif
46 L2SRAM: o = 0x00800000, l = 0x00060000
47 L3SRAM: o = 0x88000000, l = 0x00390000
48 HWA_RAM: o = 0x82000000, l = 0x00020000
49
50 /* PAGEs 1 and onwards are for overlay purposes for memory optimization.
51 Some examples:
52 1. Overlay one-time only text with uninitialized data.
53 2. Overlay L1PSRAM data path processing fast code and use copy tables
54 to page in (before entering data path) and out of L1PSRAM (when entering
55 sleep/low power).
56 */
57PAGE 1:
58 L3SRAM: o = 0x88000000, l = 0x00390000
59}
60
61-stack 0x2000 /* SOFTWARE STACK SIZE */
62-heap 0x1000 /* HEAP AREA SIZE */
63-u _Hwi_intcVectorTable
64
65SECTIONS
66{
67 /* hard addresses forces vecs to be allocated there */
68 .hwi_vect: {. = align(32); } > 0x00800000
69 .text:csl_entry:{} > L2SRAM
70 .fardata: {} > L2SRAM
71 .const: {} > L2SRAM
72 .switch: {} > L2SRAM
73 .cio: {} > L2SRAM
74 .data: {} > L2SRAM
75 .sysmem: {} > L2SRAM
76
77 GROUP
78 {
79 .rodata:
80 .bss:
81 .neardata:
82 } > L2SRAM
83 .stack: {} > L2SRAM
84 .cinit: {} > L2SRAM
85 .far: {} > L2SRAM
86
87 .text: {} > L2SRAM
88}
89
diff --git a/packages/ti/build/awr294x/linker_r5_freertos.lds b/packages/ti/build/awr294x/linker_r5_freertos.lds
new file mode 100644
index 000000000..02e13d64f
--- /dev/null
+++ b/packages/ti/build/awr294x/linker_r5_freertos.lds
@@ -0,0 +1,92 @@
1/*----------------------------------------------------------------------------*/
2/* r5f_linker.cmd */
3/* */
4/* (c) Texas Instruments 2020, All rights reserved. */
5/* */
6
7/* USER CODE BEGIN (0) */
8/* USER CODE END */
9--retain="*(.intc_text)"
10--retain="*(.irqStack)"
11--retain="*(.fiqStack)"
12--retain="*(.abortStack)"
13--retain="*(.undStack)"
14--retain="*(.svcStack)"
15-stack 0x2000 /* SOFTWARE STACK SIZE */
16-heap 0x1000 /* HEAP AREA SIZE */
17
18-u _freertosresetvectors
19
20/* Stack Sizes for various modes */
21__IRQ_STACK_SIZE = 0x4000;
22__FIQ_STACK_SIZE = 0x4000;
23__ABORT_STACK_SIZE = 0x4000;
24__UND_STACK_SIZE = 0x4000;
25__SVC_STACK_SIZE = 0x4000;
26
27/*----------------------------------------------------------------------------*/
28/* Linker Settings */
29
30/*----------------------------------------------------------------------------*/
31/* Memory Map */
32MEMORY{
33PAGE 0:
34 /* Reset Vectors base address(RESET_VECTORS) should be 64 bytes aligned */
35 RESET_VECTORS (X) : origin=0x00000000 length=0x100
36 /* RESET_VECTORS (X) : origin=0x00020000 length=0x100 */
37 TCMA_RAM (RX) : origin=0x00000100 length=0x00007F00
38 TCMB_RAM (RW) : origin=0x00080000 length=0x00008000
39 SBL_RESERVED_L2_RAM (RW) : origin=0x10200000 length=0x00060000
40 L2_RAM (RW) : origin=0x10260000 length=0x00090000
41 L3_RAM (RW) : origin=0x88000000 length=0x00390000
42 HWA_RAM (RW) : origin=0x82000000 length=0x00020000
43
44PAGE 1:
45 L3_RAM (RW) : origin=0x88000000 length=0x00390000
46}
47
48/*----------------------------------------------------------------------------*/
49/* Section Configuration */
50SECTIONS{
51 .freertosrstvectors : {} palign(8) > RESET_VECTORS
52 .bootCode : {} palign(8) > TCMA_RAM
53 .startupCode : {} palign(8) > TCMA_RAM
54 .text.hwi : {} palign(8) > TCMA_RAM
55 .startupData : {} palign(8) > TCMB_RAM, type = NOINIT
56
57 /* The linker notation "X >> Y | Z" indicates section X is first allocated in Y
58 and allowed to overflow into Z and can be split from Y to Z.
59 The linker notation "X > Y | Z" indicates section X is first allocated in Y
60 and allowed to overflow into Z and cannot be split from Y to Z. Some sections
61 like bss are not allowed to be split so > notation is used for them
62 */
63 .text : {} >> TCMA_RAM | L2_RAM
64
65 .const : {} > L2_RAM
66 .switch : {} > L2_RAM
67 .cio: : {} > SBL_RESERVED_L2_RAM | L2_RAM
68 .data: : {} > L2_RAM
69
70 .cinit : {} > L2_RAM
71 .pinit : {} > L2_RAM
72 .bss : {} > SBL_RESERVED_L2_RAM | L2_RAM
73 .stack : {} > TCMB_RAM | SBL_RESERVED_L2_RAM | L2_RAM
74 .sysmem : {} > SBL_RESERVED_L2_RAM | L2_RAM
75 .irqStack : {. = . + __IRQ_STACK_SIZE;} align(4) > L2_RAM (HIGH)
76 RUN_START(__IRQ_STACK_START)
77 RUN_END(__IRQ_STACK_END)
78 .fiqStack : {. = . + __FIQ_STACK_SIZE;} align(4) > L2_RAM (HIGH)
79 RUN_START(__FIQ_STACK_START)
80 RUN_END(__FIQ_STACK_END)
81 .abortStack : {. = . + __ABORT_STACK_SIZE;} align(4)> L2_RAM (HIGH)
82 RUN_START(__ABORT_STACK_START)
83 RUN_END(__ABORT_STACK_END)
84 .undStack : {. = . + __UND_STACK_SIZE;} align(4) > L2_RAM (HIGH)
85 RUN_START(__UND_STACK_START)
86 RUN_END(__UND_STACK_END)
87 .svcStack : {. = . + __SVC_STACK_SIZE;} align(4) > L2_RAM (HIGH)
88 RUN_START(__SVC_STACK_START)
89 RUN_END(__SVC_STACK_END)
90}
91/*----------------------------------------------------------------------------*/
92
diff --git a/packages/ti/build/makerules/component.mk b/packages/ti/build/makerules/component.mk
index 1e8f00bb8..30999b930 100644
--- a/packages/ti/build/makerules/component.mk
+++ b/packages/ti/build/makerules/component.mk
@@ -1264,7 +1264,7 @@ else
1264 endif 1264 endif
1265endif 1265endif
1266 1266
1267ifeq ($(SOC),$(filter $(SOC), am65xx j721e j7200 tpr12)) 1267ifeq ($(SOC),$(filter $(SOC), am65xx j721e j7200 tpr12 awr294x))
1268 PDK_COMMON_FREERTOS_COMP = $(PDK_COMMON_COMP) osal_freertos 1268 PDK_COMMON_FREERTOS_COMP = $(PDK_COMMON_COMP) osal_freertos
1269 PDK_COMMON_FREERTOS_COMP += freertos 1269 PDK_COMMON_FREERTOS_COMP += freertos
1270ifeq ($(ARCH),c66x) 1270ifeq ($(ARCH),c66x)
diff --git a/packages/ti/drv/hwa/test/awr294x/linker_c66.cmd b/packages/ti/drv/hwa/test/awr294x/linker_c66.cmd
new file mode 100644
index 000000000..3d2704662
--- /dev/null
+++ b/packages/ti/drv/hwa/test/awr294x/linker_c66.cmd
@@ -0,0 +1,12 @@
1/*----------------------------------------------------------------------------*/
2/* Linker Settings */
3
4/*----------------------------------------------------------------------------*/
5/* Section Configuration */
6SECTIONS
7{
8 .benchmarkL2 : { } > L2SRAM
9 .benchmarkL1 : { } > L1DSRAM
10 .FFT4KtestVector : { } > L3SRAM
11}
12/*----------------------------------------------------------------------------*/
diff --git a/packages/ti/drv/hwa/test/awr294x/linker_r5f.cmd b/packages/ti/drv/hwa/test/awr294x/linker_r5f.cmd
new file mode 100644
index 000000000..1d61f2942
--- /dev/null
+++ b/packages/ti/drv/hwa/test/awr294x/linker_r5f.cmd
@@ -0,0 +1,11 @@
1/*----------------------------------------------------------------------------*/
2/* Linker Settings */
3
4/*----------------------------------------------------------------------------*/
5/* Section Configuration */
6SECTIONS
7{
8 .benchmarkL1 : { } > TCMA_RAM | TCMB_RAM
9 .benchmarkL2 : { } > L2_RAM
10}
11/*----------------------------------------------------------------------------*/
diff --git a/packages/ti/drv/mibspi/test/slavemode/awr294x/dss.cfg b/packages/ti/drv/mibspi/test/slavemode/awr294x/dss.cfg
new file mode 100644
index 000000000..0eaf36eeb
--- /dev/null
+++ b/packages/ti/drv/mibspi/test/slavemode/awr294x/dss.cfg
@@ -0,0 +1,82 @@
1/* =============================================================================
2 * Copyright (c) Texas Instruments Incorporated 2020
3 *
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions
6 * are met:
7 *
8 * Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 *
11 * Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the
14 * distribution.
15 *
16 * Neither the name of Texas Instruments Incorporated nor the names of
17 * its contributors may be used to endorse or promote products derived
18 * from this software without specific prior written permission.
19 *
20 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
21 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
22 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
23 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
24 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
25 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
26 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
27 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
28 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
30 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
31 */
32environment['xdc.cfg.check.fatal'] = 'false';
33
34/********************************************************************
35 ************************** BIOS Modules ****************************
36 ********************************************************************/
37var Memory = xdc.useModule('xdc.runtime.Memory');
38var BIOS = xdc.useModule('ti.sysbios.BIOS');
39var HeapMem = xdc.useModule('ti.sysbios.heaps.HeapMem');
40var HeapBuf = xdc.useModule('ti.sysbios.heaps.HeapBuf');
41var Task = xdc.useModule('ti.sysbios.knl.Task');
42var Idle = xdc.useModule('ti.sysbios.knl.Idle');
43var SEM = xdc.useModule('ti.sysbios.knl.Semaphore');
44var Event = xdc.useModule('ti.sysbios.knl.Event');
45var System = xdc.useModule('xdc.runtime.System');
46var SysStd = xdc.useModule('xdc.runtime.SysStd');
47var SysMin = xdc.useModule('xdc.runtime.SysMin');
48var Timestamp = xdc.useModule('xdc.runtime.Timestamp');
49var Hwi = xdc.useModule('ti.sysbios.family.c64p.Hwi');
50var EventCombiner = xdc.useModule('ti.sysbios.family.c64p.EventCombiner');
51var Cache = xdc.useModule('ti.sysbios.hal.Cache');
52
53/* Enable Timer */
54var Timer = xdc.useModule('ti.sysbios.timers.rti.Timer');
55
56/*
57 * for (var i=0; i < Timer.numTimerDevices; i++) {
58 * Timer.intFreqs[i].lo = 200000000;
59 * Timer.intFreqs[i].hi = 0;
60 *}
61*/
62SysMin.bufSize = 16 * 1024;
63SysMin.flushAtExit = false;
64System.SupportProxy = SysMin;
65
66/* Default Heap Creation: Local L2 memory */
67var heapMemParams = new HeapMem.Params();
68heapMemParams.size = 32*1024;
69Program.global.heap0 = HeapMem.create(heapMemParams);
70Memory.defaultHeapInstance = Program.global.heap0;
71
72/* Remove clock while we are profiling for cycles and don't want BIOS
73 periodic interruption */
74BIOS.clockEnabled = true;
75
76/* Enable BIOS Task Scheduler */
77BIOS.taskEnabled = true;
78
79/*
80 * BIOS.cpuFreq.lo = 450000000;
81 * BIOS.cpuFreq.hi = 0;
82 */
diff --git a/packages/ti/drv/mibspi/test/slavemode/awr294x/dss_spi_linker.cmd b/packages/ti/drv/mibspi/test/slavemode/awr294x/dss_spi_linker.cmd
new file mode 100644
index 000000000..fc5097379
--- /dev/null
+++ b/packages/ti/drv/mibspi/test/slavemode/awr294x/dss_spi_linker.cmd
@@ -0,0 +1,94 @@
1/*
2 * Copyright (c) 2016, Texas Instruments Incorporated
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 *
9 * * Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 *
12 * * Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 *
16 * * Neither the name of Texas Instruments Incorporated nor the names of
17 * its contributors may be used to endorse or promote products derived
18 * from this software without specific prior written permission.
19 *
20 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
21 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
22 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
23 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
24 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
25 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
26 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
27 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
28 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
29 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
30 * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
31 */
32
33#define L1P_CACHE_SIZE (16*1024)
34#define L1D_CACHE_SIZE (16*1024)
35
36MEMORY
37{
38PAGE 0:
39
40#if (L1P_CACHE_SIZE < 0x8000)
41 L1PSRAM: o = 0x00E00000, l = (0x00008000 - L1P_CACHE_SIZE)
42#endif
43#if (L1D_CACHE_SIZE < 0x8000)
44 L1DSRAM: o = 0x00F00000, l = (0x00008000 - L1D_CACHE_SIZE)
45#endif
46 L2SRAM: o = 0x00800000, l = 0x00060000
47 L3SRAM: o = 0x88000000, l = 0x00300000
48 HWA_RAM : o = 0x28000000, l = 0x00020000
49
50 /* PAGEs 1 and onwards are for overlay purposes for memory optimization.
51 Some examples:
52 1. Overlay one-time only text with uninitialized data.
53 2. Overlay L1PSRAM data path processing fast code and use copy tables
54 to page in (before entering data path) and out of L1PSRAM (when entering
55 sleep/low power).
56 */
57PAGE 1:
58 L3SRAM: o = 0x88000000, l = 0x00300000
59}
60
61-stack 0x2000 /* SOFTWARE STACK SIZE */
62-heap 0x2000 /* HEAP AREA SIZE */
63
64/* Set L1D, L1P and L2 Cache Sizes */
65ti_sysbios_family_c66_Cache_l1dSize = L1D_CACHE_SIZE;
66ti_sysbios_family_c66_Cache_l1pSize = L1P_CACHE_SIZE;
67ti_sysbios_family_c66_Cache_l2Size = 0;
68
69SECTIONS
70{
71 /* hard addresses forces vecs to be allocated there */
72 .vecs: {. = align(32); } > 0x00800000
73
74 .csl_vect: load > L2SRAM
75
76 .fardata: {} > L2SRAM
77 .const: {} > L2SRAM
78 .switch: {} > L2SRAM
79 .cio: {} > L2SRAM
80 .data: {} > L2SRAM
81 .sysmem: {} > L2SRAM
82
83 .rodata: {} > L2SRAM
84 .bss: {} > L2SRAM
85 .neardata: {} > L2SRAM
86 .stack: {} > L2SRAM
87 .cinit: {} > L2SRAM
88 .far: {} > L2SRAM
89
90 .text: {} > L2SRAM
91 .l2ram: {} > L2SRAM
92 .l3ram: {} > L3SRAM
93
94}
diff --git a/packages/ti/drv/mibspi/test/slavemode/awr294x/mss.cfg b/packages/ti/drv/mibspi/test/slavemode/awr294x/mss.cfg
new file mode 100644
index 000000000..d39c5f9a3
--- /dev/null
+++ b/packages/ti/drv/mibspi/test/slavemode/awr294x/mss.cfg
@@ -0,0 +1,126 @@
1/*
2 * Copyright 2016 by Texas Instruments Incorporated.
3 *
4 * All rights reserved. Property of Texas Instruments Incorporated.
5 * Restricted rights to use, duplicate or disclose this code are
6 * granted through contract.
7 *
8 */
9/* environment['xdc.cfg.check.fatal'] = 'false'; */
10
11/********************************************************************
12 ************************** BIOS Modules ****************************
13 ********************************************************************/
14var Memory = xdc.useModule('xdc.runtime.Memory');
15var BIOS = xdc.useModule('ti.sysbios.BIOS');
16var HeapMem = xdc.useModule('ti.sysbios.heaps.HeapMem');
17var HeapBuf = xdc.useModule('ti.sysbios.heaps.HeapBuf');
18var Task = xdc.useModule('ti.sysbios.knl.Task');
19var Idle = xdc.useModule('ti.sysbios.knl.Idle');
20var SEM = xdc.useModule('ti.sysbios.knl.Semaphore');
21var Event = xdc.useModule('ti.sysbios.knl.Event');
22var Hwi = xdc.useModule('ti.sysbios.family.arm.v7r.keystone3.Hwi');
23var System = xdc.useModule('xdc.runtime.System');
24var SysMin = xdc.useModule('xdc.runtime.SysMin');
25var SysStd = xdc.useModule('xdc.runtime.SysStd');
26var Diags = xdc.useModule('xdc.runtime.Diags');
27var Pmu = xdc.useModule('ti.sysbios.family.arm.v7a.Pmu');
28var Timestamp = xdc.useModule('xdc.runtime.Timestamp');
29
30/* Enable extended format for System_printf() */
31System.extendedFormats = '%$L%$S%$F%f';
32
33/*
34 * Create and install logger for the whole system
35 */
36 /*
37var loggerBufParams = new LoggerBuf.Params();
38loggerBufParams.numEntries = 4;
39var logger0 = LoggerBuf.create(loggerBufParams);
40Defaults.common$.logger = logger0;
41Main.common$.diags_INFO = Diags.ALWAYS_ON;
42//Defaults.common$.diags_USER1 = Diags.ALWAYS_ON;
43//Task.common$.diags_USER1 = Diags.ALWAYS_ON;
44*/
45
46/*
47 * Build a custom BIOS library. The custom library will be smaller than the
48 * pre-built "instrumented" (default) and "non-instrumented" libraries.
49 *
50 * The BIOS.logsEnabled parameter specifies whether the Logging is enabled
51 * within BIOS for this custom build. These logs are used by the RTA and
52 * UIA analysis tools.
53 *
54 * The BIOS.assertsEnabled parameter specifies whether BIOS code will
55 * include Assert() checks. Setting this parameter to 'false' will generate
56 * smaller and faster code, but having asserts enabled is recommended for
57 * early development as the Assert() checks will catch lots of programming
58 * errors (invalid parameters, etc.)
59 */
60BIOS.logsEnabled = true;
61BIOS.assertsEnabled = true;
62
63
64/*
65 * Initialize MPU and enable it
66 *
67 * Note: MPU must be enabled and properly configured for caching to work.
68 */
69xdc.loadCapsule("r5_mpu.xs");
70
71/* Enable cache */
72var Cache = xdc.useModule('ti.sysbios.family.arm.v7r.Cache');
73Cache.enableCache = true;
74
75SysMin.bufSize = 16 * 1024;
76SysMin.flushAtExit = false;
77System.SupportProxy = SysMin;
78
79/* FIQ Stack Usage: */
80Hwi.fiqStackSize = 2048;
81Hwi.fiqStackSection = ".myFiqStack"
82
83/* Sysbios supports workaround for Silicon issue https://jira.itg.ti.com/browse/K3_OPEN_SI-148
84 * Details of silicon issue : https://confluence.itg.ti.com/display/PROCIPDEV/%2310+The+same+interrupt+cannot+be+nested+back-2-back+within+another+interrupt
85 * Sysbios Requirement Details: https://jira.itg.ti.com/browse/SYSBIOS-1419
86 * Workaround requires use of a resevred dummyIRQ.
87 * Using DummyIRQ#255 as per cslr_intr_mss.h it is a reserved interrupt not connected to any
88 * peripheral interrupt sources
89 */
90Hwi.dummyIRQ = 255;
91
92Program.sectMap[".myFiqStack"] = "TCMB_RAM";
93
94/* Default Heap Creation: Local L2 memory */
95var heapMemParams = new HeapMem.Params();
96heapMemParams.size = 32*1024;
97Program.global.heap0 = HeapMem.create(heapMemParams);
98Memory.defaultHeapInstance = Program.global.heap0;
99
100/* Enable Timer */
101var Timer = xdc.useModule('ti.sysbios.timers.rti.Timer');
102
103/*
104 * for (var i=0; i < Timer.numTimerDevices; i++) {
105 * Timer.intFreqs[i].lo = 200000000;
106 * Timer.intFreqs[i].hi = 0;
107 *}
108*/
109
110/* Remove clock while we are profiling for cycles and don't want BIOS
111 periodic interruption. */
112BIOS.clockEnabled = true;
113
114/* Enable BIOS Task Scheduler */
115BIOS.taskEnabled = true;
116
117Program.sectMap[".vecs"] = "VECTORS";
118
119/* Make sure libraries are built with 32-bit enum types to be compatible with DSP enum types*/
120BIOS.includeXdcRuntime = true;
121BIOS.libType = BIOS.LibType_Custom;
122BIOS.customCCOpts += " --enum_type=int ";
123/*
124 * BIOS.cpuFreq.lo = 400000000;
125 * BIOS.cpuFreq.hi = 0;
126 */
diff --git a/packages/ti/drv/mibspi/test/slavemode/awr294x/mss_spi_linker.cmd b/packages/ti/drv/mibspi/test/slavemode/awr294x/mss_spi_linker.cmd
new file mode 100644
index 000000000..34300b479
--- /dev/null
+++ b/packages/ti/drv/mibspi/test/slavemode/awr294x/mss_spi_linker.cmd
@@ -0,0 +1,74 @@
1/*----------------------------------------------------------------------------*/
2/* r4f_linker.cmd */
3/* */
4/* (c) Texas Instruments 2016, All rights reserved. */
5/* */
6
7/* USER CODE BEGIN (0) */
8/* USER CODE END */
9
10
11/*----------------------------------------------------------------------------*/
12/* Linker Settings */
13--retain="*(.intvecs)"
14
15/*----------------------------------------------------------------------------*/
16/* Memory Map */
17MEMORY{
18PAGE 0:
19 VECTORS (X) : origin=0x00000000 length=0x00000100
20 TCMA_RAM (RX) : origin=0x00000100 length=0x00007F00
21 TCMB_RAM (RW) : origin=0x00080000 length=0x00008000
22 SBL_RESERVED_L2_RAM (RW) : origin=0x10200000 length=0x00060000
23 L2_RAM_BANK0 (RW) : origin=0x10260000 length=0x00020000
24 L2_RAM_BANK1 (RW) : origin=0x10280000 length=0x00070000
25 L3_RAM (RW) : origin=0x88000000 length=0x00300000
26 HWA_RAM (RW) : origin=0x82000000 length=0x00020000
27
28PAGE 1:
29 L3_RAM (RW) : origin=0x88000000 length=0x00300000
30}
31
32/*----------------------------------------------------------------------------*/
33/* Section Configuration */
34SECTIONS{
35 .intvecs : {} > VECTORS
36
37 /* Allocate data preferentially in one bank and code (.text) in another,
38 this can improve performance due to simultaneous misses from L1P
39 and L1D caches to L2 SRAM.
40 The linker notation "X >> Y | Z" indicates section X is first allocated in Y
41 and allowed to overflow into Z and can be split from Y to Z.
42 The linker notation "X > Y | Z" indicates section X is first allocated in Y
43 and allowed to overflow into Z and cannot be split from Y to Z. Some sections
44 like bss are not allowed to be split so > notation is used for them
45 */
46 .text : {} >> TCMA_RAM | L2_RAM_BANK0 | L2_RAM_BANK1
47
48 .const : {} >> L2_RAM_BANK1 | L2_RAM_BANK0
49 .switch : {} >> L2_RAM_BANK1 | L2_RAM_BANK0
50 .cio: : {} >> SBL_RESERVED_L2_RAM | L2_RAM_BANK1 | L2_RAM_BANK0
51 .data: : {} >> L2_RAM_BANK1 | L2_RAM_BANK0
52
53 .cinit : {} > L2_RAM_BANK1 | L2_RAM_BANK0
54 .pinit : {} > L2_RAM_BANK1 | L2_RAM_BANK0
55 .bss : {} > SBL_RESERVED_L2_RAM | L2_RAM_BANK1 | L2_RAM_BANK0
56 .stack : {} > TCMB_RAM | SBL_RESERVED_L2_RAM | L2_RAM_BANK1 | L2_RAM_BANK0
57
58 .boot:{
59 *.*(*ti_sysbios_family_arm_MPU*)
60 boot.aer5f*(*.text)
61 *.*(*startup*)
62 *.*(*Startup*)
63 *.*(*Cache*)
64 } > TCMA_RAM | TCMB_RAM
65 .l3ram : {} > L3_RAM
66}
67/*----------------------------------------------------------------------------*/
68
69
70/*----------------------------------------------------------------------------*/
71/* Section Configuration */
72/* systemHeap : { } > DATA_RAM */
73/* .MCPILogBuffer : { } > DATA_RAM */
74/*----------------------------------------------------------------------------*/
diff --git a/packages/ti/drv/mibspi/test/slavemode/awr294x/r5_mpu.xs b/packages/ti/drv/mibspi/test/slavemode/awr294x/r5_mpu.xs
new file mode 100644
index 000000000..cf85c4d06
--- /dev/null
+++ b/packages/ti/drv/mibspi/test/slavemode/awr294x/r5_mpu.xs
@@ -0,0 +1,118 @@
1/*
2 * Copyright (c) 2020, Texas Instruments Incorporated
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 *
9 * * Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 *
12 * * Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 *
16 * * Neither the name of Texas Instruments Incorporated nor the names of
17 * its contributors may be used to endorse or promote products derived
18 * from this software without specific prior written permission.
19 *
20 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
21 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
22 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
23 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
24 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
25 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
26 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
27 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
28 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
29 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
30 * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
31 */
32/*
33 * ======== event_MPU.xs ========
34 * MPU Settings for TPR12 device's Cortex-R5F
35 */
36
37/*
38 * -------------------------------------------------------------------------------------------------------------
39 * | Id | Base Address | Size | En | Cacheable | XN | AccPerm | Mask |
40 * |-------------------------------------------------------------------------------------------------------------|
41 * | 0 | 0x00000000 | 4GB | T | Strongly Ordered, Shareable | T | RW at PL 1 | 0x0 |
42 * |----|--------------|------|----|-------------------------------------------|----|---------------------|------|
43 * | 1 | 0x00000000 | 32K | T | Write-Back, Write-Allocate, Non-Shareable | F | RW at PL 1 | 0x0 |
44 * |----|--------------|------|----|-------------------------------------------|----|---------------------|------|
45 * | 2 | 0x00080000 | 32K | T | Write-Back, Write-Allocate, Non-Shareable | F | RW at PL 1 | 0x0 |
46 * |----|--------------|------|----|-------------------------------------------|----|---------------------|------|
47 * | 3 | 0x10200000 | 1M | T | Write-Back, Write-Allocate, Non-Shareable | F | RW at PL 1 | 0x0 |
48 * |----|--------------|------|----|-------------------------------------------|----|---------------------|------|
49 * | 4 | 0x88000000 | 4M | T | Write-Back, Write-Allocate, Non-Shareable | F | RW at PL 1 | 0x0 |
50 * -------------------------------------------------------------------------------------------------------------
51 */
52
53/*
54 * Note: Marking a region as shareable will cause the region to behave as outer shareable with write through
55 * no write-allocate caching policy irrespective of the actual cache policy set. Therefore, only select
56 * regions that are actually shared outside the R5 CPUSS must be marked as shared.
57 */
58
59var MPU = xdc.useModule('ti.sysbios.family.arm.MPU');
60MPU.enableMPU = true;
61MPU.enableBackgroundRegion = true;
62
63var attrs = new MPU.RegionAttrs();
64MPU.initRegionAttrsMeta(attrs);
65
66attrs.enable = true;
67attrs.bufferable = false;
68attrs.cacheable = false;
69attrs.shareable = true;
70attrs.noExecute = true;
71attrs.accPerm = 1; /* RW at PL1 */
72attrs.tex = 0;
73attrs.subregionDisableMask = 0;
74MPU.setRegionMeta(0, 0x00000000, MPU.RegionSize_4G, attrs);
75
76/* TCMA */
77attrs.enable = true;
78attrs.bufferable = true;
79attrs.cacheable = true;
80attrs.shareable = false;
81attrs.noExecute = false;
82attrs.accPerm = 1; /* RW at PL1 */
83attrs.tex = 1;
84attrs.subregionDisableMask = 0;
85MPU.setRegionMeta(1, 0x00000000, MPU.RegionSize_32K, attrs);
86
87/* TCMB */
88attrs.enable = true;
89attrs.bufferable = true;
90attrs.cacheable = true;
91attrs.shareable = false;
92attrs.noExecute = false;
93attrs.accPerm = 1; /* RW at PL1 */
94attrs.tex = 1;
95attrs.subregionDisableMask = 0;
96MPU.setRegionMeta(2, 0x00080000, MPU.RegionSize_32K, attrs);
97
98/* L2 */
99attrs.enable = true;
100attrs.bufferable = true;
101attrs.cacheable = true;
102attrs.shareable = false;
103attrs.noExecute = false;
104attrs.accPerm = 1; /* RW at PL1 */
105attrs.tex = 1;
106attrs.subregionDisableMask = 0;
107MPU.setRegionMeta(3, 0x10200000, MPU.RegionSize_1M, attrs);
108
109/* L3 */
110attrs.enable = true;
111attrs.bufferable = true;
112attrs.cacheable = true;
113attrs.shareable = false;
114attrs.noExecute = false;
115attrs.accPerm = 1; /* RW at PL1 */
116attrs.tex = 1;
117attrs.subregionDisableMask = 0;
118MPU.setRegionMeta(4, 0x88000000, MPU.RegionSize_4M, attrs);
diff --git a/packages/ti/kernel/freertos/config/awr294x/c66/FreeRTOSConfig.h b/packages/ti/kernel/freertos/config/awr294x/c66/FreeRTOSConfig.h
new file mode 100644
index 000000000..8db916d5d
--- /dev/null
+++ b/packages/ti/kernel/freertos/config/awr294x/c66/FreeRTOSConfig.h
@@ -0,0 +1,172 @@
1/*
2 * Copyright (C) 2018-2021 Texas Instruments Incorporated
3 *
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions
6 * are met:
7 *
8 * Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 *
11 * Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the
14 * distribution.
15 *
16 * Neither the name of Texas Instruments Incorporated nor the names of
17 * its contributors may be used to endorse or promote products derived
18 * from this software without specific prior written permission.
19 *
20 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
21 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
22 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
23 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
24 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
25 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
26 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
27 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
28 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
30 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
31 */
32
33
34#ifndef TI_FREERTOS_CONFIG_H
35#define TI_FREERTOS_CONFIG_H
36
37#include <ti/osal/DebugP.h>
38#ifdef BUILD_C66X_1
39#include "FreeRTOSConfig_c66xdsp_1.h"
40#endif
41
42/*-----------------------------------------------------------
43 * Application specific definitions.
44 *
45 * These definitions should be adjusted for your particular hardware and
46 * application requirements.
47 *
48 * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE
49 * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE AND IN THE
50 * FreeRTOS REFERENCE MANUAL.
51 *----------------------------------------------------------*/
52
53/* Keep below as 1 if the most optmized task switching latency is needed.
54 * This disables tracing, logging, assert and other error checks.
55 * So unless every last cycle of task switching is important leave this as 0.
56 *
57 * This is not a FreeRTOS defined config and is defined by TI to quickly switch
58 * between optimized and not-so-optimized config
59 */
60#define configOPTIMIZE_FOR_LATENCY (0)
61
62#define configUSE_PREEMPTION (1)
63#define configUSE_PORT_OPTIMISED_TASK_SELECTION (1)
64#define configUSE_TICKLESS_IDLE (0)
65#define configUSE_IDLE_HOOK (0)
66#define configUSE_MALLOC_FAILED_HOOK (0)
67#define configUSE_DAEMON_TASK_STARTUP_HOOK (0)
68#define configUSE_TICK_HOOK (0)
69#define configCPU_CLOCK_HZ (450 * 1000 * 1000)
70#define configSYSTICK_CLOCK_HZ (200 * 1000 * 1000)
71#define configTICK_RATE_HZ (1000)
72#define configMAX_PRIORITIES (16)
73#define configMINIMAL_STACK_SIZE (1024) /* in units of configSTACK_DEPTH_TYPE, not bytes */
74#define configMAX_TASK_NAME_LEN (32)
75#define configUSE_TRACE_FACILITY (1)
76#define configUSE_STATS_FORMATTING_FUNCTIONS (0)
77#define configUSE_16_BIT_TICKS (0)
78#define configIDLE_SHOULD_YIELD (1)
79#define configUSE_TASK_NOTIFICATIONS (1)
80#define configTASK_NOTIFICATION_ARRAY_ENTRIES (1)
81#define configUSE_MUTEXES (1)
82#define configUSE_RECURSIVE_MUTEXES (1)
83#define configUSE_COUNTING_SEMAPHORES (1)
84#define configUSE_ALTERNATIVE_API (0)
85
86/* when = 1, Need to provied below,
87 * void vApplicationStackOverflowHook( TaskHandle_t xTask,
88 * char *pcTaskName );
89 */
90#if (configOPTIMIZE_FOR_LATENCY==0)
91#define configCHECK_FOR_STACK_OVERFLOW (2)
92#else
93#define configCHECK_FOR_STACK_OVERFLOW (0)
94#endif
95#define configRECORD_STACK_HIGH_ADDRESS (1)
96#define configQUEUE_REGISTRY_SIZE (0)
97#define configUSE_QUEUE_SETS (0)
98#define configUSE_TIME_SLICING (0) /* keep as 0 to get same functionality as SysBIOS6 */
99#define configUSE_NEWLIB_REENTRANT (0)
100#define configENABLE_BACKWARD_COMPATIBILITY (0)
101#define configNUM_THREAD_LOCAL_STORAGE_POINTERS (4)
102#define configSTACK_DEPTH_TYPE UBaseType_t
103#define configMESSAGE_BUFFER_LENGTH_TYPE size_t
104#define configSUPPORT_STATIC_ALLOCATION (1) /* when = 1, need to provide below,
105 *
106 * void vApplicationGetTimerTaskMemory( StaticTask_t **ppxTimerTaskTCBBuffer,
107 * StackType_t **ppxTimerTaskStackBuffer,
108 * uint32_t *pulTimerTaskStackSize );
109 *
110 * void vApplicationGetIdleTaskMemory( StaticTask_t **ppxIdleTaskTCBBuffer,
111 * StackType_t **ppxIdleTaskStackBuffer,
112 * uint32_t *pulIdleTaskStackSize );
113 */
114#define configSUPPORT_DYNAMIC_ALLOCATION (1)
115#define configTOTAL_HEAP_SIZE (32*1024) /* not used when heap_3.c is the selected heap */
116#define configAPPLICATION_ALLOCATED_HEAP (0)
117
118/* run-time stats config */
119#if (configOPTIMIZE_FOR_LATENCY==0)
120#define configGENERATE_RUN_TIME_STATS (1)
121#else
122#define configGENERATE_RUN_TIME_STATS (0)
123#endif
124void vPortConfigTimerForRunTimeStats();
125#define portCONFIGURE_TIMER_FOR_RUN_TIME_STATS() vPortConfigTimerForRunTimeStats()
126uint32_t uiPortGetRunTimeCounterValue();
127#define portGET_RUN_TIME_COUNTER_VALUE() uiPortGetRunTimeCounterValue()
128
129/* co-routine related config */
130#define configUSE_CO_ROUTINES (0)
131#define configMAX_CO_ROUTINE_PRIORITIES (0)
132
133/* timer related config */
134#define configUSE_TIMERS (1)
135#define configTIMER_TASK_PRIORITY (configMAX_PRIORITIES - 1)
136#define configTIMER_QUEUE_LENGTH (16)
137#define configTIMER_TASK_STACK_DEPTH (256)
138
139#define configMAX_SYSCALL_INTERRUPT_PRIORITY (0xE0U)
140#define configKERNEL_INTERRUPT_PRIORITY (configMAX_SYSCALL_INTERRUPT_PRIORITY)
141#define configMAX_API_CALL_INTERRUPT_PRIORITY (configMAX_SYSCALL_INTERRUPT_PRIORITY)
142
143#if (configOPTIMIZE_FOR_LATENCY==0)
144#define configASSERT(x) DebugP_assert( (uint32_t)(x))
145#endif
146
147/* MPU aware FreeRTOS, not supported as TI */
148#define configINCLUDE_APPLICATION_DEFINED_PRIVILEGED_FUNCTIONS (0)
149#define configTOTAL_MPU_REGIONS (0)
150#undef configTEX_S_C_B_FLASH
151#undef configTEX_S_C_B_SRAM
152#define configENFORCE_SYSTEM_CALLS_FROM_KERNEL_ONLY (0)
153
154/* defines need for FreeRTOS+POSIX*/
155#define configUSE_POSIX_ERRNO (1)
156#define configUSE_APPLICATION_TASK_TAG (1)
157
158/* include specific functions */
159#define INCLUDE_vTaskDelete (1)
160#define INCLUDE_vTaskDelay (1)
161#define INCLUDE_vTaskSuspend (1)
162#define INCLUDE_xTimerDelete (1)
163#define INCLUDE_vSemaphoreDelete (1)
164#define INCLUDE_xTaskAbortDelay (1)
165#define INCLUDE_xTaskGetCurrentTaskHandle (1)
166
167/* Size of ISR Stack in c66x */
168#define configHWI_TASK_STACK_DEPTH (4096)
169#define configTIMER_ID (0)
170#define configTIMER_INT_NUM (15)
171
172#endif /* TI_FREERTOS_CONFIG_H */
diff --git a/packages/ti/kernel/freertos/config/awr294x/c66/FreeRTOSConfig_c66xdsp_1.h b/packages/ti/kernel/freertos/config/awr294x/c66/FreeRTOSConfig_c66xdsp_1.h
new file mode 100644
index 000000000..49d5af267
--- /dev/null
+++ b/packages/ti/kernel/freertos/config/awr294x/c66/FreeRTOSConfig_c66xdsp_1.h
@@ -0,0 +1,50 @@
1/*
2 * Copyright (C) 2018-2021 Texas Instruments Incorporated
3 *
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions
6 * are met:
7 *
8 * Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 *
11 * Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the
14 * distribution.
15 *
16 * Neither the name of Texas Instruments Incorporated nor the names of
17 * its contributors may be used to endorse or promote products derived
18 * from this software without specific prior written permission.
19 *
20 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
21 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
22 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
23 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
24 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
25 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
26 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
27 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
28 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
30 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
31 */
32
33
34#ifndef TI_FREERTOS_C66XDSP_1_CONFIG_H
35#define TI_FREERTOS_C66XDSP_1_CONFIG_H
36
37
38/*-----------------------------------------------------------
39 * Application specific definitions.
40 *
41 * These definitions should be adjusted for your particular hardware and
42 * application requirements.
43 *
44 * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE
45 * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE AND IN THE
46 * FreeRTOS REFERENCE MANUAL.
47 *----------------------------------------------------------*/
48
49#define configTIMER_ID (0)
50#endif /* TI_FREERTOS_C66XDSP_1_CONFIG_H */
diff --git a/packages/ti/kernel/freertos/config/awr294x/c66/FreeRTOS_POSIX_portable.h b/packages/ti/kernel/freertos/config/awr294x/c66/FreeRTOS_POSIX_portable.h
new file mode 100644
index 000000000..1022f4b17
--- /dev/null
+++ b/packages/ti/kernel/freertos/config/awr294x/c66/FreeRTOS_POSIX_portable.h
@@ -0,0 +1,37 @@
1/*
2 * Amazon FreeRTOS+POSIX V1.0.4
3 * Copyright (C) 2018 Amazon.com, Inc. or its affiliates. All Rights Reserved.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a copy of
6 * this software and associated documentation files (the "Software"), to deal in
7 * the Software without restriction, including without limitation the rights to
8 * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
9 * the Software, and to permit persons to whom the Software is furnished to do so,
10 * subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice shall be included in all
13 * copies or substantial portions of the Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
17 * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
18 * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
19 * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
20 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * http://aws.amazon.com/freertos
23 * http://www.FreeRTOS.org
24 */
25
26/**
27 * @file FreeRTOS_POSIX_portable.h
28 * @brief Port-specific configuration of FreeRTOS+POSIX.
29 */
30
31#ifndef _FREERTOS_POSIX_PORTABLE_H_
32#define _FREERTOS_POSIX_PORTABLE_H_
33
34/* This port uses the defaults in FreeRTOS_POSIX_portable_default.h, so this
35 * file is empty. */
36
37#endif /* _FREERTOS_POSIX_PORTABLE_H_ */
diff --git a/packages/ti/kernel/freertos/config/awr294x/r5f/FreeRTOSConfig.h b/packages/ti/kernel/freertos/config/awr294x/r5f/FreeRTOSConfig.h
new file mode 100644
index 000000000..7f9f72d11
--- /dev/null
+++ b/packages/ti/kernel/freertos/config/awr294x/r5f/FreeRTOSConfig.h
@@ -0,0 +1,173 @@
1/*
2 * Copyright (C) 2018-2021 Texas Instruments Incorporated
3 *
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions
6 * are met:
7 *
8 * Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 *
11 * Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the
14 * distribution.
15 *
16 * Neither the name of Texas Instruments Incorporated nor the names of
17 * its contributors may be used to endorse or promote products derived
18 * from this software without specific prior written permission.
19 *
20 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
21 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
22 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
23 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
24 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
25 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
26 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
27 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
28 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
30 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
31 */
32
33
34#ifndef TI_FREERTOS_CONFIG_H
35#define TI_FREERTOS_CONFIG_H
36
37#include <ti/osal/DebugP.h>
38#ifdef BUILD_MCU1_0
39#include "FreeRTOSConfig_mcu1_0.h"
40#endif
41
42/*-----------------------------------------------------------
43 * Application specific definitions.
44 *
45 * These definitions should be adjusted for your particular hardware and
46 * application requirements.
47 *
48 * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE
49 * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE AND IN THE
50 * FreeRTOS REFERENCE MANUAL.
51 *----------------------------------------------------------*/
52
53/* Keep below as 1 if the most optmized task switching latency is needed.
54 * This disables tracing, logging, assert and other error checks.
55 * So unless every last cycle of task switching is important leave this as 0.
56 *
57 * This is not a FreeRTOS defined config and is defined by TI to quickly switch
58 * between optimized and not-so-optimized config
59 */
60#define configOPTIMIZE_FOR_LATENCY (0)
61
62#define configUSE_PREEMPTION (1)
63#define configUSE_PORT_OPTIMISED_TASK_SELECTION (1)
64#define configUSE_TICKLESS_IDLE (0)
65#define configUSE_IDLE_HOOK (0)
66#define configUSE_MALLOC_FAILED_HOOK (0)
67#define configUSE_DAEMON_TASK_STARTUP_HOOK (0)
68#define configUSE_TICK_HOOK (0)
69#define configCPU_CLOCK_HZ (400 * 1000 * 1000)
70#define configSYSTICK_CLOCK_HZ (200 * 1000 * 1000)
71#define configTICK_RATE_HZ (1000)
72#define configMAX_PRIORITIES (16)
73#define configMINIMAL_STACK_SIZE (1024) /* in units of configSTACK_DEPTH_TYPE, not bytes */
74#define configMAX_TASK_NAME_LEN (32)
75#define configUSE_TRACE_FACILITY (1)
76#define configUSE_STATS_FORMATTING_FUNCTIONS (0)
77#define configUSE_16_BIT_TICKS (0)
78#define configIDLE_SHOULD_YIELD (1)
79#define configUSE_TASK_NOTIFICATIONS (1)
80#define configTASK_NOTIFICATION_ARRAY_ENTRIES (1)
81#define configUSE_MUTEXES (1)
82#define configUSE_RECURSIVE_MUTEXES (1)
83#define configUSE_COUNTING_SEMAPHORES (1)
84#define configUSE_ALTERNATIVE_API (0)
85
86/* when = 1, Need to provied below,
87 * void vApplicationStackOverflowHook( TaskHandle_t xTask,
88 * char *pcTaskName );
89 */
90#if (configOPTIMIZE_FOR_LATENCY==0)
91#define configCHECK_FOR_STACK_OVERFLOW (2)
92#else
93#define configCHECK_FOR_STACK_OVERFLOW (0)
94#endif
95#define configRECORD_STACK_HIGH_ADDRESS (1)
96#define configQUEUE_REGISTRY_SIZE (0)
97#define configUSE_QUEUE_SETS (0)
98#define configUSE_TIME_SLICING (0) /* keep as 0 to get same functionality as SysBIOS6 */
99#define configUSE_NEWLIB_REENTRANT (0)
100#define configENABLE_BACKWARD_COMPATIBILITY (0)
101#define configNUM_THREAD_LOCAL_STORAGE_POINTERS (4)
102#define configSTACK_DEPTH_TYPE UBaseType_t
103#define configMESSAGE_BUFFER_LENGTH_TYPE size_t
104#define configSUPPORT_STATIC_ALLOCATION (1) /* when = 1, need to provide below,
105 *
106 * void vApplicationGetTimerTaskMemory( StaticTask_t **ppxTimerTaskTCBBuffer,
107 * StackType_t **ppxTimerTaskStackBuffer,
108 * uint32_t *pulTimerTaskStackSize );
109 *
110 * void vApplicationGetIdleTaskMemory( StaticTask_t **ppxIdleTaskTCBBuffer,
111 * StackType_t **ppxIdleTaskStackBuffer,
112 * uint32_t *pulIdleTaskStackSize );
113 */
114#define configSUPPORT_DYNAMIC_ALLOCATION (1)
115#define configTOTAL_HEAP_SIZE (32*1024) /* not used when heap_3.c is the selected heap */
116#define configAPPLICATION_ALLOCATED_HEAP (0)
117
118/* run-time stats config */
119#if (configOPTIMIZE_FOR_LATENCY==0)
120#define configGENERATE_RUN_TIME_STATS (1)
121#else
122#define configGENERATE_RUN_TIME_STATS (0)
123#endif
124void vPortConfigTimerForRunTimeStats();
125#define portCONFIGURE_TIMER_FOR_RUN_TIME_STATS() vPortConfigTimerForRunTimeStats()
126uint32_t uiPortGetRunTimeCounterValue();
127#define portGET_RUN_TIME_COUNTER_VALUE() uiPortGetRunTimeCounterValue()
128
129/* co-routine related config */
130#define configUSE_CO_ROUTINES (0)
131#define configMAX_CO_ROUTINE_PRIORITIES (0)
132
133/* timer related config */
134#define configUSE_TIMERS (1)
135#define configTIMER_TASK_PRIORITY (configMAX_PRIORITIES - 1)
136#define configTIMER_QUEUE_LENGTH (16)
137#define configTIMER_TASK_STACK_DEPTH (256)
138
139#define configMAX_SYSCALL_INTERRUPT_PRIORITY (0xE0U)
140#define configKERNEL_INTERRUPT_PRIORITY (configMAX_SYSCALL_INTERRUPT_PRIORITY)
141#define configMAX_API_CALL_INTERRUPT_PRIORITY (configMAX_SYSCALL_INTERRUPT_PRIORITY)
142
143#if (configOPTIMIZE_FOR_LATENCY==0)
144#define configASSERT(x) DebugP_assert( (uint32_t)(x))
145#endif
146
147/* MPU aware FreeRTOS, not supported as TI */
148#define configINCLUDE_APPLICATION_DEFINED_PRIVILEGED_FUNCTIONS (0)
149#define configTOTAL_MPU_REGIONS (0)
150#undef configTEX_S_C_B_FLASH
151#undef configTEX_S_C_B_SRAM
152#define configENFORCE_SYSTEM_CALLS_FROM_KERNEL_ONLY (0)
153
154/* defines need for FreeRTOS+POSIX*/
155#define configUSE_POSIX_ERRNO (1)
156#define configUSE_APPLICATION_TASK_TAG (1)
157
158/* include specific functions */
159#define INCLUDE_vTaskDelete (1)
160#define INCLUDE_vTaskDelay (1)
161#define INCLUDE_vTaskSuspend (1)
162#define INCLUDE_xTimerDelete (1)
163#define INCLUDE_vSemaphoreDelete (1)
164#define INCLUDE_xTaskGetCurrentTaskHandle (1)
165
166/*
167 * This is not a FreeRTOS defined config and is defined by TI to enable
168 * copy of _freertosresetvectors to ATCM
169 */
170#define configCOPY_RESET_VECTORS (0)
171#define configMCU_ATCM_BASE (0x0UL)
172
173#endif /* TI_FREERTOS_CONFIG_H */
diff --git a/packages/ti/kernel/freertos/config/awr294x/r5f/FreeRTOSConfig_mcu1_0.h b/packages/ti/kernel/freertos/config/awr294x/r5f/FreeRTOSConfig_mcu1_0.h
new file mode 100644
index 000000000..c5c8c67b4
--- /dev/null
+++ b/packages/ti/kernel/freertos/config/awr294x/r5f/FreeRTOSConfig_mcu1_0.h
@@ -0,0 +1,50 @@
1/*
2 * Copyright (C) 2018-2021 Texas Instruments Incorporated
3 *
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions
6 * are met:
7 *
8 * Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 *
11 * Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the
14 * distribution.
15 *
16 * Neither the name of Texas Instruments Incorporated nor the names of
17 * its contributors may be used to endorse or promote products derived
18 * from this software without specific prior written permission.
19 *
20 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
21 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
22 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
23 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
24 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
25 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
26 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
27 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
28 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
30 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
31 */
32
33
34#ifndef TI_FREERTOS_MCU1_0_CONFIG_H
35#define TI_FREERTOS_MCU1_0_CONFIG_H
36
37
38/*-----------------------------------------------------------
39 * Application specific definitions.
40 *
41 * These definitions should be adjusted for your particular hardware and
42 * application requirements.
43 *
44 * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE
45 * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE AND IN THE
46 * FreeRTOS REFERENCE MANUAL.
47 *----------------------------------------------------------*/
48
49#define configTIMER_ID (0)
50#endif /* TI_FREERTOS_MCU1_0_CONFIG_H */
diff --git a/packages/ti/kernel/freertos/config/awr294x/r5f/FreeRTOS_POSIX_portable.h b/packages/ti/kernel/freertos/config/awr294x/r5f/FreeRTOS_POSIX_portable.h
new file mode 100644
index 000000000..1022f4b17
--- /dev/null
+++ b/packages/ti/kernel/freertos/config/awr294x/r5f/FreeRTOS_POSIX_portable.h
@@ -0,0 +1,37 @@
1/*
2 * Amazon FreeRTOS+POSIX V1.0.4
3 * Copyright (C) 2018 Amazon.com, Inc. or its affiliates. All Rights Reserved.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a copy of
6 * this software and associated documentation files (the "Software"), to deal in
7 * the Software without restriction, including without limitation the rights to
8 * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
9 * the Software, and to permit persons to whom the Software is furnished to do so,
10 * subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice shall be included in all
13 * copies or substantial portions of the Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
17 * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
18 * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
19 * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
20 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * http://aws.amazon.com/freertos
23 * http://www.FreeRTOS.org
24 */
25
26/**
27 * @file FreeRTOS_POSIX_portable.h
28 * @brief Port-specific configuration of FreeRTOS+POSIX.
29 */
30
31#ifndef _FREERTOS_POSIX_PORTABLE_H_
32#define _FREERTOS_POSIX_PORTABLE_H_
33
34/* This port uses the defaults in FreeRTOS_POSIX_portable_default.h, so this
35 * file is empty. */
36
37#endif /* _FREERTOS_POSIX_PORTABLE_H_ */
diff --git a/packages/ti/osal/soc/awr294x/osal_soc.h b/packages/ti/osal/soc/awr294x/osal_soc.h
index 3518984ed..59a10f1d0 100644
--- a/packages/ti/osal/soc/awr294x/osal_soc.h
+++ b/packages/ti/osal/soc/awr294x/osal_soc.h
@@ -74,6 +74,11 @@ extern "C" {
74#define OSAL_TIRTOS_MAX_HWIP_PER_SOC ((uint32_t) 40U) 74#define OSAL_TIRTOS_MAX_HWIP_PER_SOC ((uint32_t) 40U)
75#define OSAL_TIRTOS_MAX_TIMERP_PER_SOC (TimerP_numTimerDevices) 75#define OSAL_TIRTOS_MAX_TIMERP_PER_SOC (TimerP_numTimerDevices)
76 76
77#define OSAL_FREERTOS_MAX_SEMAPHOREP_PER_SOC ((uint32_t) 150U)
78#define OSAL_FREERTOS_MAX_HWIP_PER_SOC ((uint32_t) 40U)
79#define OSAL_FREERTOS_MAX_TIMERP_PER_SOC (TimerP_numTimerDevices)
80#define OSAL_FREERTOS_MAX_TASKP_PER_SOC ((uint32_t) 20U)
81
77#define OSAL_ARCH_TIMER_INST_FOR_TS (TimerP_ANY) 82#define OSAL_ARCH_TIMER_INST_FOR_TS (TimerP_ANY)
78/* external references */ 83/* external references */
79extern Osal_HwAttrs gOsal_HwAttrs; 84extern Osal_HwAttrs gOsal_HwAttrs;
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