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authorErick Narvaez2021-01-20 16:49:36 -0600
committerAnkur2021-04-06 08:15:03 -0500
commit9758f4f6b98d00e33f4ecdf892955ffa34fd0b8b (patch)
tree001d06d388f7ca84f4de34c81155e12d08c33a94
parent75e96a103ada020eb638b6d0439eda53f9b14887 (diff)
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[PDK-8179]: ICSSG HwAttrs error
Update incorrect marcro used for prussPru[0,1,2]IramSize. Previously using IRAM_SIZE which is the size of the CTRL Registers (0x100), now fixed to use the size of IRAM RAM size (0x4000). Signed-off-by: Erick Narvaez <e-narvaez@ti.com>
Diffstat
-rw-r--r--packages/ti/drv/pruss/soc/am64x/pruicss_soc.c8
-rw-r--r--packages/ti/drv/pruss/soc/am65xx/pruicss_soc.c12
-rw-r--r--packages/ti/drv/pruss/soc/j721e/pruicss_soc.c8
3 files changed, 14 insertions, 14 deletions
diff --git a/packages/ti/drv/pruss/soc/am64x/pruicss_soc.c b/packages/ti/drv/pruss/soc/am64x/pruicss_soc.c
index 00562b7cc..ee767b83d 100644
--- a/packages/ti/drv/pruss/soc/am64x/pruicss_soc.c
+++ b/packages/ti/drv/pruss/soc/am64x/pruicss_soc.c
@@ -70,8 +70,8 @@ PRUICSS_HwAttrs prussInitCfg[PRUICSS_INSTANCE_MAX-1] =
70 CSL_PRU_ICSSG0_PR1_PDSP_TX1_IRAM_RAM_BASE, /* prussTxPru1IramBase */ 70 CSL_PRU_ICSSG0_PR1_PDSP_TX1_IRAM_RAM_BASE, /* prussTxPru1IramBase */
71 CSL_PRU_ICSSG0_DRAM0_SLV_RAM_SIZE, /* prussPru0DramSize */ 71 CSL_PRU_ICSSG0_DRAM0_SLV_RAM_SIZE, /* prussPru0DramSize */
72 CSL_PRU_ICSSG0_DRAM1_SLV_RAM_SIZE, /* prussPru1DramSize */ 72 CSL_PRU_ICSSG0_DRAM1_SLV_RAM_SIZE, /* prussPru1DramSize */
73 CSL_PRU_ICSSG0_PR1_PDSP0_IRAM_SIZE, /* prussPru0IramSize */ 73 CSL_PRU_ICSSG0_PR1_PDSP0_IRAM_RAM_SIZE, /* prussPru0IramSize */
74 CSL_PRU_ICSSG0_PR1_PDSP1_IRAM_SIZE, /* prussPru1IramSize */ 74 CSL_PRU_ICSSG0_PR1_PDSP1_IRAM_RAM_SIZE, /* prussPru1IramSize */
75 CSL_PRU_ICSSG0_RAM_SLV_RAM_SIZE, /* prussSharedDramSize */ 75 CSL_PRU_ICSSG0_RAM_SLV_RAM_SIZE, /* prussSharedDramSize */
76 CSL_PRU_ICSSG0_PR1_RTU0_PR1_RTU0_IRAM_RAM_SIZE, /* prussRtu0IramSize */ 76 CSL_PRU_ICSSG0_PR1_RTU0_PR1_RTU0_IRAM_RAM_SIZE, /* prussRtu0IramSize */
77 CSL_PRU_ICSSG0_PR1_RTU1_PR1_RTU1_IRAM_RAM_SIZE, /* prussRtu1IramSize */ 77 CSL_PRU_ICSSG0_PR1_RTU1_PR1_RTU1_IRAM_RAM_SIZE, /* prussRtu1IramSize */
@@ -105,8 +105,8 @@ PRUICSS_HwAttrs prussInitCfg[PRUICSS_INSTANCE_MAX-1] =
105 CSL_PRU_ICSSG1_PR1_PDSP_TX1_IRAM_RAM_BASE, /* prussTxPru1IramBase */ 105 CSL_PRU_ICSSG1_PR1_PDSP_TX1_IRAM_RAM_BASE, /* prussTxPru1IramBase */
106 CSL_PRU_ICSSG1_DRAM0_SLV_RAM_SIZE, /* prussPru0DramSize */ 106 CSL_PRU_ICSSG1_DRAM0_SLV_RAM_SIZE, /* prussPru0DramSize */
107 CSL_PRU_ICSSG1_DRAM1_SLV_RAM_SIZE, /* prussPru1DramSize */ 107 CSL_PRU_ICSSG1_DRAM1_SLV_RAM_SIZE, /* prussPru1DramSize */
108 CSL_PRU_ICSSG1_PR1_PDSP0_IRAM_SIZE, /* prussPru0IramSize */ 108 CSL_PRU_ICSSG1_PR1_PDSP0_IRAM_RAM_SIZE, /* prussPru0IramSize */
109 CSL_PRU_ICSSG1_PR1_PDSP1_IRAM_SIZE, /* prussPru1IramSize */ 109 CSL_PRU_ICSSG1_PR1_PDSP1_IRAM_RAM_SIZE, /* prussPru1IramSize */
110 CSL_PRU_ICSSG1_RAM_SLV_RAM_SIZE, /* prussSharedDramSize */ 110 CSL_PRU_ICSSG1_RAM_SLV_RAM_SIZE, /* prussSharedDramSize */
111 CSL_PRU_ICSSG1_PR1_RTU0_PR1_RTU0_IRAM_RAM_SIZE, /* prussRtu0IramSize */ 111 CSL_PRU_ICSSG1_PR1_RTU0_PR1_RTU0_IRAM_RAM_SIZE, /* prussRtu0IramSize */
112 CSL_PRU_ICSSG1_PR1_RTU1_PR1_RTU1_IRAM_RAM_SIZE, /* prussRtu1IramSize */ 112 CSL_PRU_ICSSG1_PR1_RTU1_PR1_RTU1_IRAM_RAM_SIZE, /* prussRtu1IramSize */
diff --git a/packages/ti/drv/pruss/soc/am65xx/pruicss_soc.c b/packages/ti/drv/pruss/soc/am65xx/pruicss_soc.c
index f44964f52..9b90f2bf9 100644
--- a/packages/ti/drv/pruss/soc/am65xx/pruicss_soc.c
+++ b/packages/ti/drv/pruss/soc/am65xx/pruicss_soc.c
@@ -70,8 +70,8 @@ PRUICSS_HwAttrs prussInitCfg[3] =
70 CSL_PRU_ICSSG0_PR1_TX1_PR1_TX1_IRAM_RAM_BASE, /* prussTxPru1IramBase */ 70 CSL_PRU_ICSSG0_PR1_TX1_PR1_TX1_IRAM_RAM_BASE, /* prussTxPru1IramBase */
71 CSL_PRU_ICSSG0_DRAM0_SLV_RAM_SIZE, /* prussPru0DramSize */ 71 CSL_PRU_ICSSG0_DRAM0_SLV_RAM_SIZE, /* prussPru0DramSize */
72 CSL_PRU_ICSSG0_DRAM1_SLV_RAM_SIZE, /* prussPru1DramSize */ 72 CSL_PRU_ICSSG0_DRAM1_SLV_RAM_SIZE, /* prussPru1DramSize */
73 CSL_PRU_ICSSG0_PR1_PDSP0_IRAM_SIZE, /* prussPru0IramSize */ 73 CSL_PRU_ICSSG0_PR1_PDSP0_IRAM_RAM_SIZE, /* prussPru0IramSize */
74 CSL_PRU_ICSSG0_PR1_PDSP1_IRAM_SIZE, /* prussPru1IramSize */ 74 CSL_PRU_ICSSG0_PR1_PDSP1_IRAM_RAM_SIZE, /* prussPru1IramSize */
75 CSL_PRU_ICSSG0_RAM_SLV_RAM_SIZE, /* prussSharedDramSize */ 75 CSL_PRU_ICSSG0_RAM_SLV_RAM_SIZE, /* prussSharedDramSize */
76 CSL_PRU_ICSSG0_PR1_RTU0_PR1_RTU0_IRAM_RAM_SIZE, /* prussRtu0IramSize */ 76 CSL_PRU_ICSSG0_PR1_RTU0_PR1_RTU0_IRAM_RAM_SIZE, /* prussRtu0IramSize */
77 CSL_PRU_ICSSG0_PR1_RTU1_PR1_RTU1_IRAM_RAM_SIZE, /* prussRtu1IramSize */ 77 CSL_PRU_ICSSG0_PR1_RTU1_PR1_RTU1_IRAM_RAM_SIZE, /* prussRtu1IramSize */
@@ -105,8 +105,8 @@ PRUICSS_HwAttrs prussInitCfg[3] =
105 CSL_PRU_ICSSG1_PR1_TX1_PR1_TX1_IRAM_RAM_BASE, /* prussTxPru1IramBase */ 105 CSL_PRU_ICSSG1_PR1_TX1_PR1_TX1_IRAM_RAM_BASE, /* prussTxPru1IramBase */
106 CSL_PRU_ICSSG1_DRAM0_SLV_RAM_SIZE, /* prussPru0DramSize */ 106 CSL_PRU_ICSSG1_DRAM0_SLV_RAM_SIZE, /* prussPru0DramSize */
107 CSL_PRU_ICSSG1_DRAM1_SLV_RAM_SIZE, /* prussPru1DramSize */ 107 CSL_PRU_ICSSG1_DRAM1_SLV_RAM_SIZE, /* prussPru1DramSize */
108 CSL_PRU_ICSSG1_PR1_PDSP0_IRAM_SIZE, /* prussPru0IramSize */ 108 CSL_PRU_ICSSG1_PR1_PDSP0_IRAM_RAM_SIZE, /* prussPru0IramSize */
109 CSL_PRU_ICSSG1_PR1_PDSP1_IRAM_SIZE, /* prussPru1IramSize */ 109 CSL_PRU_ICSSG1_PR1_PDSP1_IRAM_RAM_SIZE, /* prussPru1IramSize */
110 CSL_PRU_ICSSG1_RAM_SLV_RAM_SIZE, /* prussSharedDramSize */ 110 CSL_PRU_ICSSG1_RAM_SLV_RAM_SIZE, /* prussSharedDramSize */
111 CSL_PRU_ICSSG1_PR1_RTU0_PR1_RTU0_IRAM_RAM_SIZE, /* prussRtu0IramSize */ 111 CSL_PRU_ICSSG1_PR1_RTU0_PR1_RTU0_IRAM_RAM_SIZE, /* prussRtu0IramSize */
112 CSL_PRU_ICSSG1_PR1_RTU1_PR1_RTU1_IRAM_RAM_SIZE, /* prussRtu1IramSize */ 112 CSL_PRU_ICSSG1_PR1_RTU1_PR1_RTU1_IRAM_RAM_SIZE, /* prussRtu1IramSize */
@@ -140,8 +140,8 @@ PRUICSS_HwAttrs prussInitCfg[3] =
140 CSL_PRU_ICSSG2_PR1_TX1_PR1_TX1_IRAM_RAM_BASE, /* prussTxPru1IramBase */ 140 CSL_PRU_ICSSG2_PR1_TX1_PR1_TX1_IRAM_RAM_BASE, /* prussTxPru1IramBase */
141 CSL_PRU_ICSSG2_DRAM0_SLV_RAM_SIZE, /* prussPru0DramSize */ 141 CSL_PRU_ICSSG2_DRAM0_SLV_RAM_SIZE, /* prussPru0DramSize */
142 CSL_PRU_ICSSG2_DRAM1_SLV_RAM_SIZE, /* prussPru1DramSize */ 142 CSL_PRU_ICSSG2_DRAM1_SLV_RAM_SIZE, /* prussPru1DramSize */
143 CSL_PRU_ICSSG2_PR1_PDSP0_IRAM_SIZE, /* prussPru0IramSize */ 143 CSL_PRU_ICSSG2_PR1_PDSP0_IRAM_RAM_SIZE, /* prussPru0IramSize */
144 CSL_PRU_ICSSG2_PR1_PDSP1_IRAM_SIZE, /* prussPru1IramSize */ 144 CSL_PRU_ICSSG2_PR1_PDSP1_IRAM_RAM_SIZE, /* prussPru1IramSize */
145 CSL_PRU_ICSSG2_RAM_SLV_RAM_SIZE, /* prussSharedDramSize */ 145 CSL_PRU_ICSSG2_RAM_SLV_RAM_SIZE, /* prussSharedDramSize */
146 CSL_PRU_ICSSG2_PR1_RTU0_PR1_RTU0_IRAM_RAM_SIZE, /* prussRtu0IramSize */ 146 CSL_PRU_ICSSG2_PR1_RTU0_PR1_RTU0_IRAM_RAM_SIZE, /* prussRtu0IramSize */
147 CSL_PRU_ICSSG2_PR1_RTU1_PR1_RTU1_IRAM_RAM_SIZE, /* prussRtu1IramSize */ 147 CSL_PRU_ICSSG2_PR1_RTU1_PR1_RTU1_IRAM_RAM_SIZE, /* prussRtu1IramSize */
diff --git a/packages/ti/drv/pruss/soc/j721e/pruicss_soc.c b/packages/ti/drv/pruss/soc/j721e/pruicss_soc.c
index 0ddcfd9f9..9ce0339d1 100644
--- a/packages/ti/drv/pruss/soc/j721e/pruicss_soc.c
+++ b/packages/ti/drv/pruss/soc/j721e/pruicss_soc.c
@@ -70,8 +70,8 @@ PRUICSS_HwAttrs prussInitCfg[PRUICSS_INSTANCE_TWO] =
70 CSL_PRU_ICSSG0_PR1_TX1_PR1_TX1_IRAM_RAM_BASE, /* prussTxPru1IramBase */ 70 CSL_PRU_ICSSG0_PR1_TX1_PR1_TX1_IRAM_RAM_BASE, /* prussTxPru1IramBase */
71 CSL_PRU_ICSSG0_DRAM0_SLV_RAM_SIZE, /* prussPru0DramSize */ 71 CSL_PRU_ICSSG0_DRAM0_SLV_RAM_SIZE, /* prussPru0DramSize */
72 CSL_PRU_ICSSG0_DRAM1_SLV_RAM_SIZE, /* prussPru1DramSize */ 72 CSL_PRU_ICSSG0_DRAM1_SLV_RAM_SIZE, /* prussPru1DramSize */
73 CSL_PRU_ICSSG0_PR1_PDSP0_IRAM_SIZE, /* prussPru0IramSize */ 73 CSL_PRU_ICSSG0_PR1_PDSP0_IRAM_RAM_SIZE, /* prussPru0IramSize */
74 CSL_PRU_ICSSG0_PR1_PDSP1_IRAM_SIZE, /* prussPru1IramSize */ 74 CSL_PRU_ICSSG0_PR1_PDSP1_IRAM_RAM_SIZE, /* prussPru1IramSize */
75 CSL_PRU_ICSSG0_RAM_SLV_RAM_SIZE, /* prussSharedDramSize */ 75 CSL_PRU_ICSSG0_RAM_SLV_RAM_SIZE, /* prussSharedDramSize */
76 CSL_PRU_ICSSG0_PR1_RTU0_PR1_RTU0_IRAM_RAM_SIZE, /* prussRtu0IramSize */ 76 CSL_PRU_ICSSG0_PR1_RTU0_PR1_RTU0_IRAM_RAM_SIZE, /* prussRtu0IramSize */
77 CSL_PRU_ICSSG0_PR1_RTU1_PR1_RTU1_IRAM_RAM_SIZE, /* prussRtu1IramSize */ 77 CSL_PRU_ICSSG0_PR1_RTU1_PR1_RTU1_IRAM_RAM_SIZE, /* prussRtu1IramSize */
@@ -105,8 +105,8 @@ PRUICSS_HwAttrs prussInitCfg[PRUICSS_INSTANCE_TWO] =
105 CSL_PRU_ICSSG1_PR1_TX1_PR1_TX1_IRAM_RAM_BASE, /* prussTxPru1IramBase */ 105 CSL_PRU_ICSSG1_PR1_TX1_PR1_TX1_IRAM_RAM_BASE, /* prussTxPru1IramBase */
106 CSL_PRU_ICSSG1_DRAM0_SLV_RAM_SIZE, /* prussPru0DramSize */ 106 CSL_PRU_ICSSG1_DRAM0_SLV_RAM_SIZE, /* prussPru0DramSize */
107 CSL_PRU_ICSSG1_DRAM1_SLV_RAM_SIZE, /* prussPru1DramSize */ 107 CSL_PRU_ICSSG1_DRAM1_SLV_RAM_SIZE, /* prussPru1DramSize */
108 CSL_PRU_ICSSG1_PR1_PDSP0_IRAM_SIZE, /* prussPru0IramSize */ 108 CSL_PRU_ICSSG1_PR1_PDSP0_IRAM_RAM_SIZE, /* prussPru0IramSize */
109 CSL_PRU_ICSSG1_PR1_PDSP1_IRAM_SIZE, /* prussPru1IramSize */ 109 CSL_PRU_ICSSG1_PR1_PDSP1_IRAM_RAM_SIZE, /* prussPru1IramSize */
110 CSL_PRU_ICSSG1_RAM_SLV_RAM_SIZE, /* prussSharedDramSize */ 110 CSL_PRU_ICSSG1_RAM_SLV_RAM_SIZE, /* prussSharedDramSize */
111 CSL_PRU_ICSSG1_PR1_RTU0_PR1_RTU0_IRAM_RAM_SIZE, /* prussRtu0IramSize */ 111 CSL_PRU_ICSSG1_PR1_RTU0_PR1_RTU0_IRAM_RAM_SIZE, /* prussRtu0IramSize */
112 CSL_PRU_ICSSG1_PR1_RTU1_PR1_RTU1_IRAM_RAM_SIZE, /* prussRtu1IramSize */ 112 CSL_PRU_ICSSG1_PR1_RTU1_PR1_RTU1_IRAM_RAM_SIZE, /* prussRtu1IramSize */
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