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authorNick Saulnier2018-07-11 17:41:43 -0500
committerNick Saulnier2018-07-24 20:06:33 -0500
commit81b568741b8b98e6f590271a9aea5956d2b2d9ce (patch)
treeb502286a3db9de10d3f84c1d3b09694cb76997cb /include
parentdf05814b6f63beb90ee77336dd2aefa3c5dcbb9b (diff)
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examples/am335x: Add PRU_ADC example
Add PRU_ADC example for am335x. This example demonstrates how to control an on-chip peripheral (in this case, the ADC) with the PRU. The example also demonstrates an implementation of RPMsg to communicate between userspace and the PRU. The example was developed on a BeagleBone Black. Signed-off-by: Nick Saulnier <nsaulnier@ti.com>
Diffstat (limited to 'include')
-rw-r--r--include/am335x/sys_tscAdcSs.h963
1 files changed, 963 insertions, 0 deletions
diff --git a/include/am335x/sys_tscAdcSs.h b/include/am335x/sys_tscAdcSs.h
new file mode 100644
index 0000000..39fa3a9
--- /dev/null
+++ b/include/am335x/sys_tscAdcSs.h
@@ -0,0 +1,963 @@
1#ifndef _SYS_TSC_ADC_SS_H_
2#define _SYS_TSC_ADC_SS_H_
3
4/* SYS TSC ADC SS register set */
5typedef struct {
6
7 /* SYS_TSC_ADC_SS_REVISION register bit field */
8 union {
9 volatile uint32_t REVISION;
10
11 volatile struct {
12 uint32_t Y_MINOR : 6; // 5:0
13 uint32_t CUSTOM : 2; // 7:6
14 uint32_t X_MAJOR : 3; // 10:8
15 uint32_t R_RTL : 5; // 15:11
16 uint32_t FUNC : 12; // 27:16
17 uint32_t rsvd28 : 2; // 29:28
18 uint32_t SCHEME : 2; // 31:30
19 } REVISION_bit;
20 }; // 0x0
21
22 uint8_t rsvd4[12]; // 0x4 - 0xf
23
24 /* SYS_TSC_ADC_SS_SYSCONFIG register bit field */
25 union {
26 volatile uint32_t SYSCONFIG;
27
28 volatile struct {
29 uint32_t rsvd0 : 2; // 1:0
30 uint32_t IDLEMODE : 2; // 3:2
31 uint32_t rsvd4 : 28; // 31:4
32 } SYSCONFIG_bit;
33 }; // 0x10
34
35 uint8_t rsvd14[16]; // 0x14 - 0x23
36
37 /* SYS_TSC_ADC_SS_IRQSTATUS_RAW register bit field */
38 union {
39 volatile uint32_t IRQSTATUS_RAW;
40
41 volatile struct {
42 uint32_t HW_PEN_EVENT_ASYNCHRONOUS : 1; // 0
43 uint32_t END_OF_SEQUENCE : 1; // 1
44 uint32_t FIFO0_THRESHOLD : 1; // 2
45 uint32_t FIFO0_OVERRUN : 1; // 3
46 uint32_t FIFO0_UNDERFLOW : 1; // 4
47 uint32_t FIFO1_THRESHOLD : 1; // 5
48 uint32_t FIFO1_OVERRUN : 1; // 6
49 uint32_t FIFO1_UNDERFLOW : 1; // 7
50 uint32_t OUT_OF_RANGE : 1; // 8
51 uint32_t PEN_UP_EVENT : 1; // 9
52 uint32_t PEN_IRQ_SYNCHRONIZED : 1; // 10
53 uint32_t rsvd11 : 21; // 31:11
54 } IRQSTATUS_RAW_bit;
55 }; // 0x24
56
57 /* SYS_TSC_ADC_SS_IRQSTATUS register bit field */
58 union {
59 volatile uint32_t IRQSTATUS;
60
61 volatile struct {
62 uint32_t HW_PEN_EVENT_ASYNCHRONOUS : 1; // 0
63 uint32_t END_OF_SEQUENCE : 1; // 1
64 uint32_t FIFO0_THRESHOLD : 1; // 2
65 uint32_t FIFO0_OVERRUN : 1; // 3
66 uint32_t FIFO0_UNDERFLOW : 1; // 4
67 uint32_t FIFO1_THRESHOLD : 1; // 5
68 uint32_t FIFO1_OVERRUN : 1; // 6
69 uint32_t FIFO1_UNDERFLOW : 1; // 7
70 uint32_t OUT_OF_RANGE : 1; // 8
71 uint32_t PEN_UP_EVENT : 1; // 9
72 uint32_t HW_PEN_EVENT_SYNCHRONOUS : 1; // 10
73 uint32_t rsvd11 : 21; // 31:11
74 } IRQSTATUS_bit;
75 }; // 0x28
76
77 /* SYS_TSC_ADC_SS_IRQENABLE_SET register bit field */
78 union {
79 volatile uint32_t IRQENABLE_SET;
80
81 volatile struct {
82 uint32_t HW_PEN_EVENT_ASYNCHRONOUS : 1; // 0
83 uint32_t END_OF_SEQUENCE : 1; // 1
84 uint32_t FIFO0_THRESHOLD : 1; // 2
85 uint32_t FIFO0_OVERRUN : 1; // 3
86 uint32_t FIFO0_UNDERFLOW : 1; // 4
87 uint32_t FIFO1_THRESHOLD : 1; // 5
88 uint32_t FIFO1_OVERRUN : 1; // 6
89 uint32_t FIFO1_UNDERFLOW : 1; // 7
90 uint32_t OUT_OF_RANGE : 1; // 8
91 uint32_t PEN_UP_EVENT : 1; // 9
92 uint32_t HW_PEN_EVENT_SYNCHRONOUS : 1; // 10
93 uint32_t rsvd11 : 21; // 31:11
94 } IRQENABLE_SET_bit;
95 }; // 0x2c
96
97 /* SYS_TSC_ADC_SS_IRQENABLE_CLR register bit field */
98 union {
99 volatile uint32_t IRQENABLE_CLR;
100
101 volatile struct {
102 uint32_t HW_PEN_EVENT_ASYNCHRONOUS : 1; // 0
103 uint32_t END_OF_SEQUENCE : 1; // 1
104 uint32_t FIFO0_THRESHOLD : 1; // 2
105 uint32_t FIFO0_OVERRUN : 1; // 3
106 uint32_t FIFO0_UNDERFLOW : 1; // 4
107 uint32_t FIFO1_THRESHOLD : 1; // 5
108 uint32_t FIFO1_OVERRUN : 1; // 6
109 uint32_t FIFO1_UNDERFLOW : 1; // 7
110 uint32_t OUT_OF_RANGE : 1; // 8
111 uint32_t PEN_UP_EVENT : 1; // 9
112 uint32_t HW_PEN_EVENT_SYNCHRONOUS : 1; // 10
113 uint32_t rsvd11 : 21; // 31:11
114 } IRQENABLE_CLR_bit;
115 }; // 0x30
116
117 /* SYS_TSC_ADC_SS_IRQWAKEUP register bit field */
118 union {
119 volatile uint32_t IRQWAKEUP;
120
121 volatile struct {
122 uint32_t WAKEEN0 : 1; // 0
123 uint32_t rsvd1 : 31; // 31:1
124 } IRQWAKEUP_bit;
125 }; // 0x34
126
127 /* SYS_TSC_ADC_SS_DMAENABLE_SET register bit field */
128 union {
129 volatile uint32_t DMAENABLE_SET;
130
131 volatile struct {
132 uint32_t ENABLE_0 : 1; // 0
133 uint32_t ENABLE_1 : 1; // 1
134 uint32_t rsvd2 : 30; // 31:2
135 } DMAENABLE_SET_bit;
136 }; // 0x38
137
138 /* SYS_TSC_ADC_SS_DMAENABLE_CLR register bit field */
139 union {
140 volatile uint32_t DMAENABLE_CLR;
141
142 volatile struct {
143 uint32_t ENABLE_0 : 1; // 0
144 uint32_t ENABLE_1 : 1; // 1
145 uint32_t rsvd2 : 30; // 31:2
146 } DMAENABLE_CLR_bit;
147 }; // 0x3c
148
149 /* SYS_TSC_ADC_SS_CTRL register bit field */
150 union {
151 volatile uint32_t CTRL;
152
153 volatile struct {
154 uint32_t ENABLE : 1; // 0
155 uint32_t STEP_ID_TAG : 1; // 1
156 uint32_t STEPCONFIG_WRITEPROTECT_N_ACTIVE_LOW : 1; // 2
157 uint32_t ADC_BIAS_SELECT : 1; // 3
158 uint32_t POWER_DOWN : 1; // 4
159 uint32_t AFE_PEN_CTRL : 2; // 6:5
160 uint32_t TOUCH_SCREEN_ENABLE : 1; // 7
161 uint32_t HW_EVENT_MAPPING : 1; // 8
162 uint32_t HW_PREEMPT : 1; // 9
163 uint32_t rsvd10 : 22; // 31:10
164 } CTRL_bit;
165 }; // 0x40
166
167 /* SYS_TSC_ADC_SS_ADCSTAT register bit field */
168 union {
169 volatile uint32_t ADCSTAT;
170
171 volatile struct {
172 uint32_t STEP_ID : 5; // 4:0
173 uint32_t FSM_BUSY : 1; // 5
174 uint32_t PEN_IRQ0 : 1; // 6
175 uint32_t PEN_IRQ1 : 1; // 7
176 uint32_t rsvd8 : 24; // 31:8
177 } ADCSTAT_bit;
178 }; // 0x44
179
180 /* SYS_TSC_ADC_SS_ADCRANGE register bit field */
181 union {
182 volatile uint32_t ADCRANGE;
183
184 volatile struct {
185 uint32_t LOW_RANGE_DATA : 12; // 11:0
186 uint32_t rsvd12 : 4; // 15:12
187 uint32_t HIGH_RANGE_DATA : 12; // 27:16
188 uint32_t rsvd28 : 4; // 31:28
189 } ADCRANGE_bit;
190 }; // 0x48
191
192 /* SYS_TSC_ADC_SS_ADC_CLKDIV register bit field */
193 union {
194 volatile uint32_t ADC_CLKDIV;
195
196 volatile struct {
197 uint32_t ADC_CLKDIV : 16; // 15:0
198 uint32_t rsvd16 : 16; // 31:16
199 } ADC_CLKDIV_bit;
200 }; // 0x4c
201
202 /* SYS_TSC_ADC_SS_ADC_MISC register bit field */
203 union {
204 volatile uint32_t ADC_MISC;
205
206 volatile struct {
207 uint32_t AFE_SPARE_INPUT : 4; // 3:0
208 uint32_t AFE_SPARE_OUTPUT : 4; // 7:4
209 uint32_t rsvd8 : 24; // 31:8
210 } ADC_MISC_bit;
211 }; // 0x50
212
213 /* SYS_TSC_ADC_SS_STEPENABLE register bit field */
214 union {
215 volatile uint32_t STEPENABLE;
216
217 volatile struct {
218 uint32_t TS_CHARGE : 1; // 0
219 uint32_t STEP1 : 1; // 1
220 uint32_t STEP2 : 1; // 2
221 uint32_t STEP3 : 1; // 3
222 uint32_t STEP4 : 1; // 4
223 uint32_t STEP5 : 1; // 5
224 uint32_t STEP6 : 1; // 6
225 uint32_t STEP7 : 1; // 7
226 uint32_t STEP8 : 1; // 8
227 uint32_t STEP9 : 1; // 9
228 uint32_t STEP10 : 1; // 10
229 uint32_t STEP11 : 1; // 11
230 uint32_t STEP12 : 1; // 12
231 uint32_t STEP13 : 1; // 13
232 uint32_t STEP14 : 1; // 14
233 uint32_t STEP15 : 1; // 15
234 uint32_t STEP16 : 1; // 16
235 uint32_t rsvd17 : 15; // 31:17
236 } STEPENABLE_bit;
237 }; // 0x54
238
239 /* SYS_TSC_ADC_SS_IDLECONFIG register bit field */
240 union {
241 volatile uint32_t IDLECONFIG;
242
243 volatile struct {
244 uint32_t rsvd0 : 5; // 4:0
245 uint32_t XPPSW_SWC : 1; // 5
246 uint32_t XNNSW_SWC : 1; // 6
247 uint32_t YPPSW_SWC : 1; // 7
248 uint32_t YNNSW_SWC : 1; // 8
249 uint32_t XNPSW_SWC : 1; // 9
250 uint32_t YPNSW_SWC : 1; // 10
251 uint32_t WPNSW_SWC : 1; // 11
252 uint32_t SEL_RFP_SWC_2_0 : 3; // 14:12
253 uint32_t SEL_INM_SWC_3_0 : 4; // 18:15
254 uint32_t SEL_INP_SWC_3_0 : 4; // 22:19
255 uint32_t SEL_RFM_SWC_1_0 : 2; // 24:23
256 uint32_t DIFF_CNTRL : 1; // 25
257 uint32_t rsvd26 : 6; // 31:26
258 } IDLECONFIG_bit;
259 }; // 0x58
260
261 /* SYS_TSC_ADC_SS_TS_CHARGE_STEPCONFIG register bit field */
262 union {
263 volatile uint32_t TS_CHARGE_STEPCONFIG;
264
265 volatile struct {
266 uint32_t rsvd0 : 5; // 4:0
267 uint32_t XPPSW_SWC : 1; // 5
268 uint32_t XNNSW_SWC : 1; // 6
269 uint32_t YPPSW_SWC : 1; // 7
270 uint32_t YNNSW_SWC : 1; // 8
271 uint32_t XNPSW_SWC : 1; // 9
272 uint32_t YPNSW_SWC : 1; // 10
273 uint32_t WPNSW_SWC : 1; // 11
274 uint32_t SEL_RFP_SWC_2_0 : 3; // 14:12
275 uint32_t SEL_INM_SWM3_0 : 4; // 18:15
276 uint32_t SEL_INP_SWC_3_0 : 4; // 22:19
277 uint32_t SEL_RFM_SWC_1_0 : 2; // 24:23
278 uint32_t DIFF_CNTRL : 1; // 25
279 uint32_t rsvd26 : 6; // 31:26
280 } TS_CHARGE_STEPCONFIG_bit;
281 }; // 0x5c
282
283 /* SYS_TSC_ADC_SS_TS_CHARGE_DELAY register bit field */
284 union {
285 volatile uint32_t TS_CHARGE_DELAY;
286
287 volatile struct {
288 uint32_t OPENDELAY : 18; // 17:0
289 uint32_t rsvd18 : 14; // 31:18
290 } TS_CHARGE_DELAY_bit;
291 }; // 0x60
292
293 /* SYS_TSC_ADC_SS_STEPCONFIG1 register bit field */
294 union {
295 volatile uint32_t STEPCONFIG1;
296
297 volatile struct {
298 uint32_t MODE : 2; // 1:0
299 uint32_t AVERAGING : 3; // 4:2
300 uint32_t XPPSW_SWC : 1; // 5
301 uint32_t XNNSW_SWC : 1; // 6
302 uint32_t YPPSW_SWC : 1; // 7
303 uint32_t YNNSW_SWC : 1; // 8
304 uint32_t XNPSW_SWC : 1; // 9
305 uint32_t YPNSW_SWC : 1; // 10
306 uint32_t WPNSW_SWC : 1; // 11
307 uint32_t SEL_RFP_SWC_2_0 : 3; // 14:12
308 uint32_t SEL_INM_SWC_3_0 : 4; // 18:15
309 uint32_t SEL_INP_SWC_3_0 : 4; // 22:19
310 uint32_t SEL_RFM_SWC_1_0 : 2; // 24:23
311 uint32_t DIFF_CNTRL : 1; // 25
312 uint32_t FIFO_SELECT : 1; // 26
313 uint32_t RANGE_CHECK : 1; // 27
314 uint32_t rsvd28 : 4; // 31:28
315 } STEPCONFIG1_bit;
316 }; // 0x64
317
318 /* SYS_TSC_ADC_SS_STEPDELAY1 register bit field */
319 union {
320 volatile uint32_t STEPDELAY1;
321
322 volatile struct {
323 uint32_t OPENDELAY : 18; // 17:0
324 uint32_t rsvd18 : 6; // 23:18
325 uint32_t SAMPLEDELAY : 8; // 31:24
326 } STEPDELAY1_bit;
327 }; // 0x68
328
329 /* SYS_TSC_ADC_SS_STEPCONFIG2 register bit field */
330 union {
331 volatile uint32_t STEPCONFIG2;
332
333 volatile struct {
334 uint32_t MODE : 2; // 1:0
335 uint32_t AVERAGING : 3; // 4:2
336 uint32_t XPPSW_SWC : 1; // 5
337 uint32_t XNNSW_SWC : 1; // 6
338 uint32_t YPPSW_SWC : 1; // 7
339 uint32_t YNNSW_SWC : 1; // 8
340 uint32_t XNPSW_SWC : 1; // 9
341 uint32_t YPNSW_SWC : 1; // 10
342 uint32_t WPNSW_SWC : 1; // 11
343 uint32_t SEL_RFP_SWC_2_0 : 3; // 14:12
344 uint32_t SEL_INM_SWC_3_0 : 4; // 18:15
345 uint32_t SEL_INP_SWC_3_0 : 4; // 22:19
346 uint32_t SEL_RFM_SWC_1_0 : 2; // 24:23
347 uint32_t DIFF_CNTRL : 1; // 25
348 uint32_t FIFO_SELECT : 1; // 26
349 uint32_t RANGE_CHECK : 1; // 27
350 uint32_t rsvd28 : 4; // 31:28
351 } STEPCONFIG2_bit;
352 }; // 0x6c
353
354 /* SYS_TSC_ADC_SS_STEPDELAY2 register bit field */
355 union {
356 volatile uint32_t STEPDELAY2;
357
358 volatile struct {
359 uint32_t OPENDELAY : 18; // 17:0
360 uint32_t rsvd18 : 6; // 23:18
361 uint32_t SAMPLEDELAY : 8; // 31:24
362 } STEPDELAY2_bit;
363 }; // 0x70
364
365 /* SYS_TSC_ADC_SS_STEPCONFIG3 register bit field */
366 union {
367 volatile uint32_t STEPCONFIG3;
368
369 volatile struct {
370 uint32_t MODE : 2; // 1:0
371 uint32_t AVERAGING : 3; // 4:2
372 uint32_t XPPSW_SWC : 1; // 5
373 uint32_t XNNSW_SWC : 1; // 6
374 uint32_t YPPSW_SWC : 1; // 7
375 uint32_t YNNSW_SWC : 1; // 8
376 uint32_t XNPSW_SWC : 1; // 9
377 uint32_t YPNSW_SWC : 1; // 10
378 uint32_t WPNSW_SWC : 1; // 11
379 uint32_t SEL_RFP_SWC_2_0 : 3; // 14:12
380 uint32_t SEL_INM_SWC_3_0 : 4; // 18:15
381 uint32_t SEL_INP_SWC_3_0 : 4; // 22:19
382 uint32_t SEL_RFM_SWC_1_0 : 2; // 24:23
383 uint32_t DIFF_CNTRL : 1; // 25
384 uint32_t FIFO_SELECT : 1; // 26
385 uint32_t RANGE_CHECK : 1; // 27
386 uint32_t rsvd28 : 4; // 31:28
387 } STEPCONFIG3_bit;
388 }; // 0x74
389
390 /* SYS_TSC_ADC_SS_STEPDELAY3 register bit field */
391 union {
392 volatile uint32_t STEPDELAY3;
393
394 volatile struct {
395 uint32_t OPENDELAY : 18; // 17:0
396 uint32_t rsvd18 : 6; // 23:18
397 uint32_t SAMPLEDELAY : 8; // 31:24
398 } STEPDELAY3_bit;
399 }; // 0x78
400
401 /* SYS_TSC_ADC_SS_STEPCONFIG4 register bit field */
402 union {
403 volatile uint32_t STEPCONFIG4;
404
405 volatile struct {
406 uint32_t MODE : 2; // 1:0
407 uint32_t AVERAGING : 3; // 4:2
408 uint32_t XPPSW_SWC : 1; // 5
409 uint32_t XNNSW_SWC : 1; // 6
410 uint32_t YPPSW_SWC : 1; // 7
411 uint32_t YNNSW_SWC : 1; // 8
412 uint32_t XNPSW_SWC : 1; // 9
413 uint32_t YPNSW_SWC : 1; // 10
414 uint32_t WPNSW_SWC : 1; // 11
415 uint32_t SEL_RFP_SWC_2_0 : 3; // 14:12
416 uint32_t SEL_INM_SWC_3_0 : 4; // 18:15
417 uint32_t SEL_INP_SWC_3_0 : 4; // 22:19
418 uint32_t SEL_RFM_SWC_1_0 : 2; // 24:23
419 uint32_t DIFF_CNTRL : 1; // 25
420 uint32_t FIFO_SELECT : 1; // 26
421 uint32_t RANGE_CHECK : 1; // 27
422 uint32_t rsvd28 : 4; // 31:28
423 } STEPCONFIG4_bit;
424 }; // 0x7c
425
426 /* SYS_TSC_ADC_SS_STEPDELAY4 register bit field */
427 union {
428 volatile uint32_t STEPDELAY4;
429
430 volatile struct {
431 uint32_t OPENDELAY : 18; // 17:0
432 uint32_t rsvd18 : 6; // 23:18
433 uint32_t SAMPLEDELAY : 8; // 31:24
434 } STEPDELAY4_bit;
435 }; // 0x80
436
437 /* SYS_TSC_ADC_SS_STEPCONFIG5 register bit field */
438 union {
439 volatile uint32_t STEPCONFIG5;
440
441 volatile struct {
442 uint32_t MODE : 2; // 1:0
443 uint32_t AVERAGING : 3; // 4:2
444 uint32_t XPPSW_SWC : 1; // 5
445 uint32_t XNNSW_SWC : 1; // 6
446 uint32_t YPPSW_SWC : 1; // 7
447 uint32_t YNNSW_SWC : 1; // 8
448 uint32_t XNPSW_SWC : 1; // 9
449 uint32_t YPNSW_SWC : 1; // 10
450 uint32_t WPNSW_SWC : 1; // 11
451 uint32_t SEL_RFP_SWC_2_0 : 3; // 14:12
452 uint32_t SEL_INM_SWC_3_0 : 4; // 18:15
453 uint32_t SEL_INP_SWC_3_0 : 4; // 22:19
454 uint32_t SEL_RFM_SWC_1_0 : 2; // 24:23
455 uint32_t DIFF_CNTRL : 1; // 25
456 uint32_t FIFO_SELECT : 1; // 26
457 uint32_t RANGE_CHECK : 1; // 27
458 uint32_t rsvd28 : 4; // 31:28
459 } STEPCONFIG5_bit;
460 }; // 0x84
461
462 /* SYS_TSC_ADC_SS_STEPDELAY5 register bit field */
463 union {
464 volatile uint32_t STEPDELAY5;
465
466 volatile struct {
467 uint32_t OPENDELAY : 18; // 17:0
468 uint32_t rsvd18 : 6; // 23:18
469 uint32_t SAMPLEDELAY : 8; // 31:24
470 } STEPDELAY5_bit;
471 }; // 0x88
472
473 /* SYS_TSC_ADC_SS_STEPCONFIG6 register bit field */
474 union {
475 volatile uint32_t STEPCONFIG6;
476
477 volatile struct {
478 uint32_t MODE : 2; // 1:0
479 uint32_t AVERAGING : 3; // 4:2
480 uint32_t XPPSW_SWC : 1; // 5
481 uint32_t XNNSW_SWC : 1; // 6
482 uint32_t YPPSW_SWC : 1; // 7
483 uint32_t YNNSW_SWC : 1; // 8
484 uint32_t XNPSW_SWC : 1; // 9
485 uint32_t YPNSW_SWC : 1; // 10
486 uint32_t WPNSW_SWC : 1; // 11
487 uint32_t SEL_RFP_SWC_2_0 : 3; // 14:12
488 uint32_t SEL_INM_SWC_3_0 : 4; // 18:15
489 uint32_t SEL_INP_SWC_3_0 : 4; // 22:19
490 uint32_t SEL_RFM_SWC_1_0 : 2; // 24:23
491 uint32_t DIFF_CNTRL : 1; // 25
492 uint32_t FIFO_SELECT : 1; // 26
493 uint32_t RANGE_CHECK : 1; // 27
494 uint32_t rsvd28 : 4; // 31:28
495 } STEPCONFIG6_bit;
496 }; // 0x8c
497
498 /* SYS_TSC_ADC_SS_STEPDELAY6 register bit field */
499 union {
500 volatile uint32_t STEPDELAY6;
501
502 volatile struct {
503 uint32_t OPENDELAY : 18; // 17:0
504 uint32_t rsvd18 : 6; // 23:18
505 uint32_t SAMPLEDELAY : 8; // 31:24
506 } STEPDELAY6_bit;
507 }; // 0x90
508
509 /* SYS_TSC_ADC_SS_STEPCONFIG7 register bit field */
510 union {
511 volatile uint32_t STEPCONFIG7;
512
513 volatile struct {
514 uint32_t MODE : 2; // 1:0
515 uint32_t AVERAGING : 3; // 4:2
516 uint32_t XPPSW_SWC : 1; // 5
517 uint32_t XNNSW_SWC : 1; // 6
518 uint32_t YPPSW_SWC : 1; // 7
519 uint32_t YNNSW_SWC : 1; // 8
520 uint32_t XNPSW_SWC : 1; // 9
521 uint32_t YPNSW_SWC : 1; // 10
522 uint32_t WPNSW_SWC : 1; // 11
523 uint32_t SEL_RFP_SWC_2_0 : 3; // 14:12
524 uint32_t SEL_INM_SWC_3_0 : 4; // 18:15
525 uint32_t SEL_INP_SWC_3_0 : 4; // 22:19
526 uint32_t SEL_RFM_SWC_1_0 : 2; // 24:23
527 uint32_t DIFF_CNTRL : 1; // 25
528 uint32_t FIFO_SELECT : 1; // 26
529 uint32_t RANGE_CHECK : 1; // 27
530 uint32_t rsvd28 : 4; // 31:28
531 } STEPCONFIG7_bit;
532 }; // 0x94
533
534 /* SYS_TSC_ADC_SS_STEPDELAY7 register bit field */
535 union {
536 volatile uint32_t STEPDELAY7;
537
538 volatile struct {
539 uint32_t OPENDELAY : 18; // 17:0
540 uint32_t rsvd18 : 6; // 23:18
541 uint32_t SAMPLEDELAY : 8; // 31:24
542 } STEPDELAY7_bit;
543 }; // 0x98
544
545 /* SYS_TSC_ADC_SS_STEPCONFIG8 register bit field */
546 union {
547 volatile uint32_t STEPCONFIG8;
548
549 volatile struct {
550 uint32_t MODE : 2; // 1:0
551 uint32_t AVERAGING : 3; // 4:2
552 uint32_t XPPSW_SWC : 1; // 5
553 uint32_t XNNSW_SWC : 1; // 6
554 uint32_t YPPSW_SWC : 1; // 7
555 uint32_t YNNSW_SWC : 1; // 8
556 uint32_t XNPSW_SWC : 1; // 9
557 uint32_t YPNSW_SWC : 1; // 10
558 uint32_t WPNSW_SWC : 1; // 11
559 uint32_t SEL_RFP_SWC_2_0 : 3; // 14:12
560 uint32_t SEL_INM_SWC_3_0 : 4; // 18:15
561 uint32_t SEL_INP_SWC_3_0 : 4; // 22:19
562 uint32_t SEL_RFM_SWC_1_0 : 2; // 24:23
563 uint32_t DIFF_CNTRL : 1; // 25
564 uint32_t FIFO_SELECT : 1; // 26
565 uint32_t RANGE_CHECK : 1; // 27
566 uint32_t rsvd28 : 4; // 31:28
567 } STEPCONFIG8_bit;
568 }; // 0x9c
569
570 /* SYS_TSC_ADC_SS_STEPDELAY8 register bit field */
571 union {
572 volatile uint32_t STEPDELAY8;
573
574 volatile struct {
575 uint32_t OPENDELAY : 18; // 17:0
576 uint32_t rsvd18 : 6; // 23:18
577 uint32_t SAMPLEDELAY : 8; // 31:24
578 } STEPDELAY8_bit;
579 }; // 0xa0
580
581 /* SYS_TSC_ADC_SS_STEPCONFIG9 register bit field */
582 union {
583 volatile uint32_t STEPCONFIG9;
584
585 volatile struct {
586 uint32_t MODE : 2; // 1:0
587 uint32_t AVERAGING : 3; // 4:2
588 uint32_t XPPSW_SWC : 1; // 5
589 uint32_t XNNSW_SWC : 1; // 6
590 uint32_t YPPSW_SWC : 1; // 7
591 uint32_t YNNSW_SWC : 1; // 8
592 uint32_t XNPSW_SWC : 1; // 9
593 uint32_t YPNSW_SWC : 1; // 10
594 uint32_t WPNSW_SWC : 1; // 11
595 uint32_t SEL_RFP_SWC_2_0 : 3; // 14:12
596 uint32_t SEL_INM_SWC_3_0 : 4; // 18:15
597 uint32_t SEL_INP_SWC_3_0 : 4; // 22:19
598 uint32_t SEL_RFM_SWC_1_0 : 2; // 24:23
599 uint32_t DIFF_CNTRL : 1; // 25
600 uint32_t FIFO_SELECT : 1; // 26
601 uint32_t RANGE_CHECK : 1; // 27
602 uint32_t rsvd28 : 4; // 31:28
603 } STEPCONFIG9_bit;
604 }; // 0xa4
605
606 /* SYS_TSC_ADC_SS_STEPDELAY9 register bit field */
607 union {
608 volatile uint32_t STEPDELAY9;
609
610 volatile struct {
611 uint32_t OPENDELAY : 18; // 17:0
612 uint32_t rsvd18 : 6; // 23:18
613 uint32_t SAMPLEDELAY : 8; // 31:24
614 } STEPDELAY9_bit;
615 }; // 0xa8
616
617 /* SYS_TSC_ADC_SS_STEPCONFIG10 register bit field */
618 union {
619 volatile uint32_t STEPCONFIG10;
620
621 volatile struct {
622 uint32_t MODE : 2; // 1:0
623 uint32_t AVERAGING : 3; // 4:2
624 uint32_t XPPSW_SWC : 1; // 5
625 uint32_t XNNSW_SWC : 1; // 6
626 uint32_t YPPSW_SWC : 1; // 7
627 uint32_t YNNSW_SWC : 1; // 8
628 uint32_t XNPSW_SWC : 1; // 9
629 uint32_t YPNSW_SWC : 1; // 10
630 uint32_t WPNSW_SWC : 1; // 11
631 uint32_t SEL_RFP_SWC_2_0 : 3; // 14:12
632 uint32_t SEL_INM_SWC_3_0 : 4; // 18:15
633 uint32_t SEL_INP_SWC_3_0 : 4; // 22:19
634 uint32_t SEL_RFM_SWC_1_0 : 2; // 24:23
635 uint32_t DIFF_CNTRL : 1; // 25
636 uint32_t FIFO_SELECT : 1; // 26
637 uint32_t RANGE_CHECK : 1; // 27
638 uint32_t rsvd28 : 4; // 31:28
639 } STEPCONFIG10_bit;
640 }; // 0xac
641
642 /* SYS_TSC_ADC_SS_STEPDELAY10 register bit field */
643 union {
644 volatile uint32_t STEPDELAY10;
645
646 volatile struct {
647 uint32_t OPENDELAY : 18; // 17:0
648 uint32_t rsvd18 : 6; // 23:18
649 uint32_t SAMPLEDELAY : 8; // 31:24
650 } STEPDELAY10_bit;
651 }; // 0xb0
652
653 /* SYS_TSC_ADC_SS_STEPCONFIG11 register bit field */
654 union {
655 volatile uint32_t STEPCONFIG11;
656
657 volatile struct {
658 uint32_t MODE : 2; // 1:0
659 uint32_t AVERAGING : 3; // 4:2
660 uint32_t XPPSW_SWC : 1; // 5
661 uint32_t XNNSW_SWC : 1; // 6
662 uint32_t YPPSW_SWC : 1; // 7
663 uint32_t YNNSW_SWC : 1; // 8
664 uint32_t XNPSW_SWC : 1; // 9
665 uint32_t YPNSW_SWC : 1; // 10
666 uint32_t WPNSW_SWC : 1; // 11
667 uint32_t SEL_RFP_SWC_2_0 : 3; // 14:12
668 uint32_t SEL_INM_SWC_3_0 : 4; // 18:15
669 uint32_t SEL_INP_SWC_3_0 : 4; // 22:19
670 uint32_t SEL_RFM_SWC_1_0 : 2; // 24:23
671 uint32_t DIFF_CNTRL : 1; // 25
672 uint32_t FIFO_SELECT : 1; // 26
673 uint32_t RANGE_CHECK : 1; // 27
674 uint32_t rsvd28 : 4; // 31:28
675 } STEPCONFIG11_bit;
676 }; // 0xb4
677
678 /* SYS_TSC_ADC_SS_STEPDELAY11 register bit field */
679 union {
680 volatile uint32_t STEPDELAY11;
681
682 volatile struct {
683 uint32_t OPENDELAY : 18; // 17:0
684 uint32_t rsvd18 : 6; // 23:18
685 uint32_t SAMPLEDELAY : 8; // 31:24
686 } STEPDELAY11_bit;
687 }; // 0xb8
688
689 /* SYS_TSC_ADC_SS_STEPCONFIG12 register bit field */
690 union {
691 volatile uint32_t STEPCONFIG12;
692
693 volatile struct {
694 uint32_t MODE : 2; // 1:0
695 uint32_t AVERAGING : 3; // 4:2
696 uint32_t XPPSW_SWC : 1; // 5
697 uint32_t XNNSW_SWC : 1; // 6
698 uint32_t YPPSW_SWC : 1; // 7
699 uint32_t YNNSW_SWC : 1; // 8
700 uint32_t XNPSW_SWC : 1; // 9
701 uint32_t YPNSW_SWC : 1; // 10
702 uint32_t WPNSW_SWC : 1; // 11
703 uint32_t SEL_RFP_SWC_2_0 : 3; // 14:12
704 uint32_t SEL_INM_SWC_3_0 : 4; // 18:15
705 uint32_t SEL_INP_SWC_3_0 : 4; // 22:19
706 uint32_t SEL_RFM_SWC_1_0 : 2; // 24:23
707 uint32_t DIFF_CNTRL : 1; // 25
708 uint32_t FIFO_SELECT : 1; // 26
709 uint32_t RANGE_CHECK : 1; // 27
710 uint32_t rsvd28 : 4; // 31:28
711 } STEPCONFIG12_bit;
712 }; // 0xbc
713
714 /* SYS_TSC_ADC_SS_STEPDELAY12 register bit field */
715 union {
716 volatile uint32_t STEPDELAY12;
717
718 volatile struct {
719 uint32_t OPENDELAY : 18; // 17:0
720 uint32_t rsvd18 : 6; // 23:18
721 uint32_t SAMPLEDELAY : 8; // 31:24
722 } STEPDELAY12_bit;
723 }; // 0xc0
724
725 /* SYS_TSC_ADC_SS_STEPCONFIG13 register bit field */
726 union {
727 volatile uint32_t STEPCONFIG13;
728
729 volatile struct {
730 uint32_t MODE : 2; // 1:0
731 uint32_t AVERAGING : 3; // 4:2
732 uint32_t XPPSW_SWC : 1; // 5
733 uint32_t XNNSW_SWC : 1; // 6
734 uint32_t YPPSW_SWC : 1; // 7
735 uint32_t YNNSW_SWC : 1; // 8
736 uint32_t XNPSW_SWC : 1; // 9
737 uint32_t YPNSW_SWC : 1; // 10
738 uint32_t WPNSW_SWC : 1; // 11
739 uint32_t SEL_RFP_SWC_2_0 : 3; // 14:12
740 uint32_t SEL_INM_SWC_3_0 : 4; // 18:15
741 uint32_t SEL_INP_SWC_3_0 : 4; // 22:19
742 uint32_t SEL_RFM_SWC_1_0 : 2; // 24:23
743 uint32_t DIFF_CNTRL : 1; // 25
744 uint32_t FIFO_SELECT : 1; // 26
745 uint32_t RANGE_CHECK : 1; // 27
746 uint32_t rsvd28 : 4; // 31:28
747 } STEPCONFIG13_bit;
748 }; // 0xc4
749
750 /* SYS_TSC_ADC_SS_STEPDELAY13 register bit field */
751 union {
752 volatile uint32_t STEPDELAY13;
753
754 volatile struct {
755 uint32_t OPENDELAY : 18; // 17:0
756 uint32_t rsvd18 : 6; // 23:18
757 uint32_t SAMPLEDELAY : 8; // 31:24
758 } STEPDELAY13_bit;
759 }; // 0xc8
760
761 /* SYS_TSC_ADC_SS_STEPCONFIG14 register bit field */
762 union {
763 volatile uint32_t STEPCONFIG14;
764
765 volatile struct {
766 uint32_t MODE : 2; // 1:0
767 uint32_t AVERAGING : 3; // 4:2
768 uint32_t XPPSW_SWC : 1; // 5
769 uint32_t XNNSW_SWC : 1; // 6
770 uint32_t YPPSW_SWC : 1; // 7
771 uint32_t YNNSW_SWC : 1; // 8
772 uint32_t XNPSW_SWC : 1; // 9
773 uint32_t YPNSW_SWC : 1; // 10
774 uint32_t WPNSW_SWC : 1; // 11
775 uint32_t SEL_RFP_SWC_2_0 : 3; // 14:12
776 uint32_t SEL_INM_SWC_3_0 : 4; // 18:15
777 uint32_t SEL_INP_SWC_3_0 : 4; // 22:19
778 uint32_t SEL_RFM_SWC_1_0 : 2; // 24:23
779 uint32_t DIFF_CNTRL : 1; // 25
780 uint32_t FIFO_SELECT : 1; // 26
781 uint32_t RANGE_CHECK : 1; // 27
782 uint32_t rsvd28 : 4; // 31:28
783 } STEPCONFIG14_bit;
784 }; // 0xcc
785
786 /* SYS_TSC_ADC_SS_STEPDELAY14 register bit field */
787 union {
788 volatile uint32_t STEPDELAY14;
789
790 volatile struct {
791 uint32_t OPENDELAY : 18; // 17:0
792 uint32_t rsvd18 : 6; // 23:18
793 uint32_t SAMPLEDELAY : 8; // 31:24
794 } STEPDELAY14_bit;
795 }; // 0xd0
796
797 /* SYS_TSC_ADC_SS_STEPCONFIG15 register bit field */
798 union {
799 volatile uint32_t STEPCONFIG15;
800
801 volatile struct {
802 uint32_t MODE : 2; // 1:0
803 uint32_t AVERAGING : 3; // 4:2
804 uint32_t XPPSW_SWC : 1; // 5
805 uint32_t XNNSW_SWC : 1; // 6
806 uint32_t YPPSW_SWC : 1; // 7
807 uint32_t YNNSW_SWC : 1; // 8
808 uint32_t XNPSW_SWC : 1; // 9
809 uint32_t YPNSW_SWC : 1; // 10
810 uint32_t WPNSW_SWC : 1; // 11
811 uint32_t SEL_RFP_SWC_2_0 : 3; // 14:12
812 uint32_t SEL_INM_SWC_3_0 : 4; // 18:15
813 uint32_t SEL_INP_SWC_3_0 : 4; // 22:19
814 uint32_t SEL_RFM_SWC_1_0 : 2; // 24:23
815 uint32_t DIFF_CNTRL : 1; // 25
816 uint32_t FIFO_SELECT : 1; // 26
817 uint32_t RANGE_CHECK : 1; // 27
818 uint32_t rsvd28 : 4; // 31:28
819 } STEPCONFIG15_bit;
820 }; // 0xd4
821
822 /* SYS_TSC_ADC_SS_STEPDELAY15 register bit field */
823 union {
824 volatile uint32_t STEPDELAY15;
825
826 volatile struct {
827 uint32_t OPENDELAY : 18; // 17:0
828 uint32_t rsvd18 : 6; // 23:18
829 uint32_t SAMPLEDELAY : 8; // 31:24
830 } STEPDELAY15_bit;
831 }; // 0xd8
832
833 /* SYS_TSC_ADC_SS_STEPCONFIG16 register bit field */
834 union {
835 volatile uint32_t STEPCONFIG16;
836
837 volatile struct {
838 uint32_t MODE : 2; // 1:0
839 uint32_t AVERAGING : 3; // 4:2
840 uint32_t XPPSW_SWC : 1; // 5
841 uint32_t XNNSW_SWC : 1; // 6
842 uint32_t YPPSW_SWC : 1; // 7
843 uint32_t YNNSW_SWC : 1; // 8
844 uint32_t XNPSW_SWC : 1; // 9
845 uint32_t YPNSW_SWC : 1; // 10
846 uint32_t WPNSW_SWC : 1; // 11
847 uint32_t SEL_RFP_SWC_2_0 : 3; // 14:12
848 uint32_t SEL_INM_SWC_3_0 : 4; // 18:15
849 uint32_t SEL_INP_SWC_3_0 : 4; // 22:19
850 uint32_t SEL_RFM_SWC_1_0 : 2; // 24:23
851 uint32_t DIFF_CNTRL : 1; // 25
852 uint32_t FIFO_SELECT : 1; // 26
853 uint32_t RANGE_CHECK : 1; // 27
854 uint32_t rsvd28 : 4; // 31:28
855 } STEPCONFIG16_bit;
856 }; // 0xdc
857
858 /* SYS_TSC_ADC_SS_STEPDELAY16 register bit field */
859 union {
860 volatile uint32_t STEPDELAY16;
861
862 volatile struct {
863 uint32_t OPENDELAY : 18; // 17:0
864 uint32_t rsvd18 : 6; // 23:18
865 uint32_t SAMPLEDELAY : 8; // 31:24
866 } STEPDELAY16_bit;
867 }; // 0xe0
868
869 /* SYS_TSC_ADC_SS_FIFO0COUNT register bit field */
870 union {
871 volatile uint32_t FIFO0COUNT;
872
873 volatile struct {
874 uint32_t WORDS_IN_FIFO0 : 7; // 6:0
875 uint32_t rsvd7 : 25; // 31:7
876 } FIFO0COUNT_bit;
877 }; // 0xe4
878
879 /* SYS_TSC_ADC_SS_FIFO0THRESHOLD register bit field */
880 union {
881 volatile uint32_t FIFO0THRESHOLD;
882
883 volatile struct {
884 uint32_t FIFO0_THRESHOLD_LEVEL : 6; // 5:0
885 uint32_t rsvd6 : 26; // 31:6
886 } FIFO0THRESHOLD_bit;
887 }; // 0xe8
888
889 /* SYS_TSC_ADC_SS_DMA0REQ register bit field */
890 union {
891 volatile uint32_t DMA0REQ;
892
893 volatile struct {
894 uint32_t DMA_REQUEST_LEVEL : 6; // 5:0
895 uint32_t rsvd6 : 26; // 31:6
896 } DMA0REQ_bit;
897 }; // 0xec
898
899 /* SYS_TSC_ADC_SS_FIFO1COUNT register bit field */
900 union {
901 volatile uint32_t FIFO1COUNT;
902
903 volatile struct {
904 uint32_t WORDS_IN_FIFO0 : 7; // 6:0
905 uint32_t rsvd7 : 25; // 31:7
906 } FIFO1COUNT_bit;
907 }; // 0xf0
908
909 /* SYS_TSC_ADC_SS_FIFO1THRESHOLD register bit field */
910 union {
911 volatile uint32_t FIFO1THRESHOLD;
912
913 volatile struct {
914 uint32_t FIFO0_THRESHOLD_LEVEL : 6; // 5:0
915 uint32_t rsvd6 : 26; // 31:6
916 } FIFO1THRESHOLD_bit;
917 }; // 0xf4
918
919 /* SYS_TSC_ADC_SS_DMA1REQ register bit field */
920 union {
921 volatile uint32_t DMA1REQ;
922
923 volatile struct {
924 uint32_t DMA_REQUEST_LEVEL : 6; // 5:0
925 uint32_t rsvd6 : 26; // 31:6
926 } DMA1REQ_bit;
927 }; // 0xf8
928
929 uint8_t rsvdfc[4]; // 0xfc - 0xff
930
931 /* SYS_TSC_ADC_SS_FIFO0DATA register bit field */
932 union {
933 volatile uint32_t FIFO0DATA;
934
935 volatile struct {
936 uint32_t ADCDATA : 12; // 11:0
937 uint32_t rsvd12 : 4; // 15:12
938 uint32_t ADCCHNLID : 4; // 19:16
939 uint32_t rsvd20 : 12; // 31:20
940 } FIFO0DATA_bit;
941 }; // 0x100
942
943 uint8_t rsvd104[252]; // 0x104 - 0x1ff
944
945 /* SYS_TSC_ADC_SS_FIFO1DATA register bit field */
946 union {
947 volatile uint32_t FIFO1DATA;
948
949 volatile struct {
950 uint32_t ADCDATA : 12; // 11:0
951 uint32_t rsvd12 : 4; // 15:12
952 uint32_t ADCCHNLID : 4; // 19:16
953 uint32_t rsvd20 : 12; // 31:20
954 } FIFO1DATA_bit;
955 }; // 0x200
956
957} sysTscAdcSs;
958
959/* Definition of Touchscreen/ADC register structures. */
960#define ADC_TSC (*((volatile sysTscAdcSs*)0x44E0D000))
961
962#endif /* _SYS_TSC_ADC_SS_H_ */
963
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