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-rw-r--r--labs/Getting_Started_Labs/assembly_code/solution/am572x/AM57xx_PRU.cmd2
-rw-r--r--labs/Getting_Started_Labs/assembly_code/solution/am65x/AM65x_PRU0.cmd89
-rw-r--r--labs/Getting_Started_Labs/c_and_assembly/solution/am65x/AM65x_PRU0.cmd89
-rw-r--r--labs/Getting_Started_Labs/c_and_inline_assembly/solution/am65x/AM65x_PRU0.cmd89
-rw-r--r--labs/Getting_Started_Labs/c_code/solution/am65x/AM65x_PRU0.cmd89
-rw-r--r--labs/Getting_Started_Labs/linker_cmd/AM65x_PRU0.cmd55
-rw-r--r--labs/Getting_Started_Labs/linker_cmd/AM65x_PRU1.cmd57
-rw-r--r--labs/Getting_Started_Labs/linker_cmd/AM65x_RTU0.cmd55
-rw-r--r--labs/Getting_Started_Labs/linker_cmd/AM65x_RTU1.cmd55
9 files changed, 298 insertions, 282 deletions
diff --git a/labs/Getting_Started_Labs/assembly_code/solution/am572x/AM57xx_PRU.cmd b/labs/Getting_Started_Labs/assembly_code/solution/am572x/AM57xx_PRU.cmd
index f054677..07e1884 100644
--- a/labs/Getting_Started_Labs/assembly_code/solution/am572x/AM57xx_PRU.cmd
+++ b/labs/Getting_Started_Labs/assembly_code/solution/am572x/AM57xx_PRU.cmd
@@ -1,6 +1,6 @@
1/****************************************************************************/ 1/****************************************************************************/
2/* AM57xx_PRU.cmd */ 2/* AM57xx_PRU.cmd */
3/* Copyright (c) 2015 Texas Instruments Incorporated */ 3/* Copyright (c) 2015-2018 Texas Instruments Incorporated */
4/* */ 4/* */
5/* Description: This file is a linker command file that can be used for */ 5/* Description: This file is a linker command file that can be used for */
6/* linking PRU programs built with the C compiler and */ 6/* linking PRU programs built with the C compiler and */
diff --git a/labs/Getting_Started_Labs/assembly_code/solution/am65x/AM65x_PRU0.cmd b/labs/Getting_Started_Labs/assembly_code/solution/am65x/AM65x_PRU0.cmd
index fed8ee4..45f8722 100644
--- a/labs/Getting_Started_Labs/assembly_code/solution/am65x/AM65x_PRU0.cmd
+++ b/labs/Getting_Started_Labs/assembly_code/solution/am65x/AM65x_PRU0.cmd
@@ -4,7 +4,7 @@
4 * Example Linker command file for linking programs built with the C compiler 4 * Example Linker command file for linking programs built with the C compiler
5 * on AM65x PRU0 cores 5 * on AM65x PRU0 cores
6 * 6 *
7 * Copyright (C) 2017-2018 Texas Instruments Incorporated - http://www.ti.com/ 7 * Copyright (C) 2017-2020 Texas Instruments Incorporated - http://www.ti.com/
8 * 8 *
9 * Redistribution and use in source and binary forms, with or without 9 * Redistribution and use in source and binary forms, with or without
10 * modification, are permitted provided that the following conditions 10 * modification, are permitted provided that the following conditions
@@ -41,25 +41,28 @@
41MEMORY 41MEMORY
42{ 42{
43 PAGE 0: 43 PAGE 0:
44 /* 16kB PRU Instruction RAM */ 44 /* 16 KB PRU Instruction RAM */
45 PRU_IMEM : org = 0x00000000 len = 0x00004000 45 PRU_IMEM : org = 0x00000000 len = 0x00004000
46 46
47 PAGE 1: 47 PAGE 1:
48 /* Data RAMs */ 48 /* Data RAMs */
49 /* 8kB PRU Data RAM 0_1; use only the first page for PRU0 and reserve 49 /* 8 KB PRU Data RAM 0; use only the first 4 KB for PRU0 and reserve
50 * the second page for RTU0 */ 50 * the second 4 KB for RTU0 and Tx_PRU0 */
51 PRU_DMEM_0_1 : org = 0x00000000 len = 0x00001000 CREGISTER=24 51 PRU0_DMEM_0 : org = 0x00000000 len = 0x00001000 CREGISTER=24
52 /* 8kB PRU Data RAM 1_0; use only the first page for PRU1 and reserve 52 /* 8 KB PRU Data RAM 1; reserved completely for Slice1 cores - PRU1,
53 * the second page for RTU1 */ 53 * RTU1 and Tx_PRU1; do not use for any Slice0 cores */
54 PRU_DMEM_1_0 : org = 0x00002000 len = 0x00001000 CREGISTER=25 54 PRU0_DMEM_1 : org = 0x00002000 len = 0x00001000 CREGISTER=25
55 /* NOTE: Customized to reserve the second 4K of ICSS Data RAMs 0 and 1 so 55 /* NOTE: Custom split of the second 4 KB of ICSS Data RAMs 0 and 1
56 as not to conflict with corresponding RTU core usage */ 56 * split equally between the corresponding RTU and Tx_PRU cores in
57 RTU_DMEM_0_1 : org = 0x00001000 len = 0x00001000 57 * each slice */
58 RTU_DMEM_1_0 : org = 0x00003000 len = 0x00001000 58 RTU0_DMEM_0 : org = 0x00001000 len = 0x00000800
59 TX_PRU0_DMEM_0 : org = 0x00001800 len = 0x00000800
60 RTU0_DMEM_1 : org = 0x00003000 len = 0x00000800
61 TX_PRU0_DMEM_1 : org = 0x00003800 len = 0x00000800
59 62
60 PAGE 2: 63 PAGE 2:
61 /* C28 needs to be programmed to point to SHAREDMEM, default is 0 */ 64 /* C28 needs to be programmed to point to SHAREDMEM, default is 0 */
62 /* 64kB PRU Shared RAM */ 65 /* 64 KB PRU Shared RAM */
63 PRU_SHAREDMEM : org = 0x00010000 len = 0x00010000 CREGISTER=28 66 PRU_SHAREDMEM : org = 0x00010000 len = 0x00010000 CREGISTER=28
64 67
65 /* Internal Peripherals */ 68 /* Internal Peripherals */
@@ -68,17 +71,17 @@ MEMORY
68 * Register #6 that starts at 0x200 offset within INTC */ 71 * Register #6 that starts at 0x200 offset within INTC */
69 PRU_INTC : org = 0x00020000 len = 0x00001504 CREGISTER=0 72 PRU_INTC : org = 0x00020000 len = 0x00001504 CREGISTER=0
70 PRU_IEP1 : org = 0x0002F000 len = 0x00000100 CREGISTER=1 73 PRU_IEP1 : org = 0x0002F000 len = 0x00000100 CREGISTER=1
71 PRU_IEP1_EXT : org = 0x0002F100 len = 0x0000021C CREGISTER=2 74 PRU_IEP1_0x100 : org = 0x0002F100 len = 0x0000021C CREGISTER=2
72 PRU_ECAP : org = 0x00030000 len = 0x00000060 CREGISTER=3 75 PRU_ECAP : org = 0x00030000 len = 0x00000060 CREGISTER=3
73 PRU_CFG : org = 0x00026000 len = 0x00000100 CREGISTER=4 76 PRU_CFG : org = 0x00026000 len = 0x00000100 CREGISTER=4
74 PRU_CFG_EXT : org = 0x00026100 len = 0x00000098 CREGISTER=5 77 PRU_CFG_0x100 : org = 0x00026100 len = 0x00000098 CREGISTER=5
75 /* XXX: This value is part of INTC space, and is therefore commented 78 /* XXX: This value is part of INTC space, and is therefore commented
76 * out as it conflicts with PRU_INTC size above. Using this requires 79 * out as it conflicts with PRU_INTC size above. Using this requires
77 * splitting up the pruIntc structure and CT_INTC variable from 80 * splitting up the pruIntc structure and CT_INTC variable from
78 * pru_intc.h */ 81 * pru_intc.h */
79 /*PRU_INTC_EXT : org = 0x00040200 len = 0x00001304 CREGISTER=6*/ 82 /*PRU_INTC_0x200: org = 0x00020200 len = 0x00001304 CREGISTER=6*/
80 PRU_UART : org = 0x00028000 len = 0x00000038 CREGISTER=7 83 PRU_UART : org = 0x00028000 len = 0x00000038 CREGISTER=7
81 PRU_IEP0_EXT : org = 0x0002E100 len = 0x0000021C CREGISTER=8 84 PRU_IEP0_0x100 : org = 0x0002E100 len = 0x0000021C CREGISTER=8
82 MII_G_RT : org = 0x00033000 len = 0x00000C18 CREGISTER=9 85 MII_G_RT : org = 0x00033000 len = 0x00000C18 CREGISTER=9
83 TM_CFG_PRU0 : org = 0x0002A000 len = 0x0000004C CREGISTER=10 86 TM_CFG_PRU0 : org = 0x0002A000 len = 0x0000004C CREGISTER=10
84 PRU0_CTRL : org = 0x00022000 len = 0x00000088 CREGISTER=11 87 PRU0_CTRL : org = 0x00022000 len = 0x00000088 CREGISTER=11
@@ -89,23 +92,21 @@ MEMORY
89 MII_MDIO : org = 0x00032400 len = 0x00000090 CREGISTER=21 92 MII_MDIO : org = 0x00032400 len = 0x00000090 CREGISTER=21
90 PRU_RTU_RAT0 : org = 0x00008000 len = 0x00000854 CREGISTER=22 93 PRU_RTU_RAT0 : org = 0x00008000 len = 0x00000854 CREGISTER=22
91 PRU_IEP0 : org = 0x0002E000 len = 0x00000100 CREGISTER=26 94 PRU_IEP0 : org = 0x0002E000 len = 0x00000100 CREGISTER=26
92 MII_RT_CFG : org = 0x00032000 len = 0x0000024C CREGISTER=27 95 MII_RT : org = 0x00032000 len = 0x0000024C CREGISTER=27
93 96
94 /* External Regions */ 97 /* External Regions */
95 /* FIXME: Random length of 0x1000 assigned to the below regions */ 98 /* Random length 0x1000 assigned to the below regions */
96 TIMER_MANAGER : org = 0x60000000 len = 0x00001000 CREGISTER=15 99 RSVD15 : org = 0x60000000 len = 0x00001000 CREGISTER=15
97 RING_ACCELERATOR: org = 0x70000000 len = 0x00001000 CREGISTER=16 100 RSVD16 : org = 0x70000000 len = 0x00001000 CREGISTER=16
98 INTERRUPT_AGGREGATOR: org = 0x80000000 len = 0x00001000 CREGISTER=17 101 RSVD17 : org = 0x80000000 len = 0x00001000 CREGISTER=17
99 GPMC : org = 0x90000000 len = 0x00001000 CREGISTER=18 102 RSVD18 : org = 0x90000000 len = 0x00001000 CREGISTER=18
100 PCIE : org = 0xA0000000 len = 0x00001000 CREGISTER=19 103 RSVD19 : org = 0xA0000000 len = 0x00001000 CREGISTER=19
101 UDMA_P : org = 0xB0000000 len = 0x00001000 CREGISTER=20 104 RSVD20 : org = 0xB0000000 len = 0x00001000 CREGISTER=20
102 ADC : org = 0xC0000000 len = 0x00001000 CREGISTER=23 105 RSVD23 : org = 0xC0000000 len = 0x00001000 CREGISTER=23
103 106 /* Random length 0x10000 (max len value) assigned to programmable C29-31*/
104 /* External Memory */ 107 RSVD29 : org = 0xD0000000 len = 0x00010000 CREGISTER=29
105 /* Random length of 0x10000 (max len value) assigned to all regions */ 108 RSVD30 : org = 0xE0000000 len = 0x00010000 CREGISTER=30
106 DDR : org = 0xD0000000 len = 0x00010000 CREGISTER=29 109 RSVD31 : org = 0xF0000000 len = 0x00010000 CREGISTER=31
107 MSMC : org = 0xE0000000 len = 0x00010000 CREGISTER=30
108 R5_RAM : org = 0xF0000000 len = 0x00010000 CREGISTER=31
109} 110}
110 111
111/* Specify the sections allocation into memory */ 112/* Specify the sections allocation into memory */
@@ -115,17 +116,17 @@ SECTIONS {
115 .text:_c_int00* > 0x0, PAGE 0 116 .text:_c_int00* > 0x0, PAGE 0
116 117
117 .text > PRU_IMEM, PAGE 0 118 .text > PRU_IMEM, PAGE 0
118 .stack > PRU_DMEM_0_1, PAGE 1 119 .stack > PRU0_DMEM_0, PAGE 1
119 .bss > PRU_DMEM_0_1, PAGE 1 120 .bss > PRU0_DMEM_0, PAGE 1
120 .cio > PRU_DMEM_0_1, PAGE 1 121 .cio > PRU0_DMEM_0, PAGE 1
121 .data > PRU_DMEM_0_1, PAGE 1 122 .data > PRU0_DMEM_0, PAGE 1
122 .switch > PRU_DMEM_0_1, PAGE 1 123 .switch > PRU0_DMEM_0, PAGE 1
123 .sysmem > PRU_DMEM_0_1, PAGE 1 124 .sysmem > PRU0_DMEM_0, PAGE 1
124 .cinit > PRU_DMEM_0_1, PAGE 1 125 .cinit > PRU0_DMEM_0, PAGE 1
125 .rodata > PRU_DMEM_0_1, PAGE 1 126 .rodata > PRU0_DMEM_0, PAGE 1
126 .rofardata > PRU_DMEM_0_1, PAGE 1 127 .rofardata > PRU0_DMEM_0, PAGE 1
127 .farbss > PRU_DMEM_0_1, PAGE 1 128 .farbss > PRU0_DMEM_0, PAGE 1
128 .fardata > PRU_DMEM_0_1, PAGE 1 129 .fardata > PRU0_DMEM_0, PAGE 1
129 130
130 .resource_table > PRU_DMEM_0_1, PAGE 1 131 .resource_table > PRU0_DMEM_0, PAGE 1
131} 132}
diff --git a/labs/Getting_Started_Labs/c_and_assembly/solution/am65x/AM65x_PRU0.cmd b/labs/Getting_Started_Labs/c_and_assembly/solution/am65x/AM65x_PRU0.cmd
index fed8ee4..45f8722 100644
--- a/labs/Getting_Started_Labs/c_and_assembly/solution/am65x/AM65x_PRU0.cmd
+++ b/labs/Getting_Started_Labs/c_and_assembly/solution/am65x/AM65x_PRU0.cmd
@@ -4,7 +4,7 @@
4 * Example Linker command file for linking programs built with the C compiler 4 * Example Linker command file for linking programs built with the C compiler
5 * on AM65x PRU0 cores 5 * on AM65x PRU0 cores
6 * 6 *
7 * Copyright (C) 2017-2018 Texas Instruments Incorporated - http://www.ti.com/ 7 * Copyright (C) 2017-2020 Texas Instruments Incorporated - http://www.ti.com/
8 * 8 *
9 * Redistribution and use in source and binary forms, with or without 9 * Redistribution and use in source and binary forms, with or without
10 * modification, are permitted provided that the following conditions 10 * modification, are permitted provided that the following conditions
@@ -41,25 +41,28 @@
41MEMORY 41MEMORY
42{ 42{
43 PAGE 0: 43 PAGE 0:
44 /* 16kB PRU Instruction RAM */ 44 /* 16 KB PRU Instruction RAM */
45 PRU_IMEM : org = 0x00000000 len = 0x00004000 45 PRU_IMEM : org = 0x00000000 len = 0x00004000
46 46
47 PAGE 1: 47 PAGE 1:
48 /* Data RAMs */ 48 /* Data RAMs */
49 /* 8kB PRU Data RAM 0_1; use only the first page for PRU0 and reserve 49 /* 8 KB PRU Data RAM 0; use only the first 4 KB for PRU0 and reserve
50 * the second page for RTU0 */ 50 * the second 4 KB for RTU0 and Tx_PRU0 */
51 PRU_DMEM_0_1 : org = 0x00000000 len = 0x00001000 CREGISTER=24 51 PRU0_DMEM_0 : org = 0x00000000 len = 0x00001000 CREGISTER=24
52 /* 8kB PRU Data RAM 1_0; use only the first page for PRU1 and reserve 52 /* 8 KB PRU Data RAM 1; reserved completely for Slice1 cores - PRU1,
53 * the second page for RTU1 */ 53 * RTU1 and Tx_PRU1; do not use for any Slice0 cores */
54 PRU_DMEM_1_0 : org = 0x00002000 len = 0x00001000 CREGISTER=25 54 PRU0_DMEM_1 : org = 0x00002000 len = 0x00001000 CREGISTER=25
55 /* NOTE: Customized to reserve the second 4K of ICSS Data RAMs 0 and 1 so 55 /* NOTE: Custom split of the second 4 KB of ICSS Data RAMs 0 and 1
56 as not to conflict with corresponding RTU core usage */ 56 * split equally between the corresponding RTU and Tx_PRU cores in
57 RTU_DMEM_0_1 : org = 0x00001000 len = 0x00001000 57 * each slice */
58 RTU_DMEM_1_0 : org = 0x00003000 len = 0x00001000 58 RTU0_DMEM_0 : org = 0x00001000 len = 0x00000800
59 TX_PRU0_DMEM_0 : org = 0x00001800 len = 0x00000800
60 RTU0_DMEM_1 : org = 0x00003000 len = 0x00000800
61 TX_PRU0_DMEM_1 : org = 0x00003800 len = 0x00000800
59 62
60 PAGE 2: 63 PAGE 2:
61 /* C28 needs to be programmed to point to SHAREDMEM, default is 0 */ 64 /* C28 needs to be programmed to point to SHAREDMEM, default is 0 */
62 /* 64kB PRU Shared RAM */ 65 /* 64 KB PRU Shared RAM */
63 PRU_SHAREDMEM : org = 0x00010000 len = 0x00010000 CREGISTER=28 66 PRU_SHAREDMEM : org = 0x00010000 len = 0x00010000 CREGISTER=28
64 67
65 /* Internal Peripherals */ 68 /* Internal Peripherals */
@@ -68,17 +71,17 @@ MEMORY
68 * Register #6 that starts at 0x200 offset within INTC */ 71 * Register #6 that starts at 0x200 offset within INTC */
69 PRU_INTC : org = 0x00020000 len = 0x00001504 CREGISTER=0 72 PRU_INTC : org = 0x00020000 len = 0x00001504 CREGISTER=0
70 PRU_IEP1 : org = 0x0002F000 len = 0x00000100 CREGISTER=1 73 PRU_IEP1 : org = 0x0002F000 len = 0x00000100 CREGISTER=1
71 PRU_IEP1_EXT : org = 0x0002F100 len = 0x0000021C CREGISTER=2 74 PRU_IEP1_0x100 : org = 0x0002F100 len = 0x0000021C CREGISTER=2
72 PRU_ECAP : org = 0x00030000 len = 0x00000060 CREGISTER=3 75 PRU_ECAP : org = 0x00030000 len = 0x00000060 CREGISTER=3
73 PRU_CFG : org = 0x00026000 len = 0x00000100 CREGISTER=4 76 PRU_CFG : org = 0x00026000 len = 0x00000100 CREGISTER=4
74 PRU_CFG_EXT : org = 0x00026100 len = 0x00000098 CREGISTER=5 77 PRU_CFG_0x100 : org = 0x00026100 len = 0x00000098 CREGISTER=5
75 /* XXX: This value is part of INTC space, and is therefore commented 78 /* XXX: This value is part of INTC space, and is therefore commented
76 * out as it conflicts with PRU_INTC size above. Using this requires 79 * out as it conflicts with PRU_INTC size above. Using this requires
77 * splitting up the pruIntc structure and CT_INTC variable from 80 * splitting up the pruIntc structure and CT_INTC variable from
78 * pru_intc.h */ 81 * pru_intc.h */
79 /*PRU_INTC_EXT : org = 0x00040200 len = 0x00001304 CREGISTER=6*/ 82 /*PRU_INTC_0x200: org = 0x00020200 len = 0x00001304 CREGISTER=6*/
80 PRU_UART : org = 0x00028000 len = 0x00000038 CREGISTER=7 83 PRU_UART : org = 0x00028000 len = 0x00000038 CREGISTER=7
81 PRU_IEP0_EXT : org = 0x0002E100 len = 0x0000021C CREGISTER=8 84 PRU_IEP0_0x100 : org = 0x0002E100 len = 0x0000021C CREGISTER=8
82 MII_G_RT : org = 0x00033000 len = 0x00000C18 CREGISTER=9 85 MII_G_RT : org = 0x00033000 len = 0x00000C18 CREGISTER=9
83 TM_CFG_PRU0 : org = 0x0002A000 len = 0x0000004C CREGISTER=10 86 TM_CFG_PRU0 : org = 0x0002A000 len = 0x0000004C CREGISTER=10
84 PRU0_CTRL : org = 0x00022000 len = 0x00000088 CREGISTER=11 87 PRU0_CTRL : org = 0x00022000 len = 0x00000088 CREGISTER=11
@@ -89,23 +92,21 @@ MEMORY
89 MII_MDIO : org = 0x00032400 len = 0x00000090 CREGISTER=21 92 MII_MDIO : org = 0x00032400 len = 0x00000090 CREGISTER=21
90 PRU_RTU_RAT0 : org = 0x00008000 len = 0x00000854 CREGISTER=22 93 PRU_RTU_RAT0 : org = 0x00008000 len = 0x00000854 CREGISTER=22
91 PRU_IEP0 : org = 0x0002E000 len = 0x00000100 CREGISTER=26 94 PRU_IEP0 : org = 0x0002E000 len = 0x00000100 CREGISTER=26
92 MII_RT_CFG : org = 0x00032000 len = 0x0000024C CREGISTER=27 95 MII_RT : org = 0x00032000 len = 0x0000024C CREGISTER=27
93 96
94 /* External Regions */ 97 /* External Regions */
95 /* FIXME: Random length of 0x1000 assigned to the below regions */ 98 /* Random length 0x1000 assigned to the below regions */
96 TIMER_MANAGER : org = 0x60000000 len = 0x00001000 CREGISTER=15 99 RSVD15 : org = 0x60000000 len = 0x00001000 CREGISTER=15
97 RING_ACCELERATOR: org = 0x70000000 len = 0x00001000 CREGISTER=16 100 RSVD16 : org = 0x70000000 len = 0x00001000 CREGISTER=16
98 INTERRUPT_AGGREGATOR: org = 0x80000000 len = 0x00001000 CREGISTER=17 101 RSVD17 : org = 0x80000000 len = 0x00001000 CREGISTER=17
99 GPMC : org = 0x90000000 len = 0x00001000 CREGISTER=18 102 RSVD18 : org = 0x90000000 len = 0x00001000 CREGISTER=18
100 PCIE : org = 0xA0000000 len = 0x00001000 CREGISTER=19 103 RSVD19 : org = 0xA0000000 len = 0x00001000 CREGISTER=19
101 UDMA_P : org = 0xB0000000 len = 0x00001000 CREGISTER=20 104 RSVD20 : org = 0xB0000000 len = 0x00001000 CREGISTER=20
102 ADC : org = 0xC0000000 len = 0x00001000 CREGISTER=23 105 RSVD23 : org = 0xC0000000 len = 0x00001000 CREGISTER=23
103 106 /* Random length 0x10000 (max len value) assigned to programmable C29-31*/
104 /* External Memory */ 107 RSVD29 : org = 0xD0000000 len = 0x00010000 CREGISTER=29
105 /* Random length of 0x10000 (max len value) assigned to all regions */ 108 RSVD30 : org = 0xE0000000 len = 0x00010000 CREGISTER=30
106 DDR : org = 0xD0000000 len = 0x00010000 CREGISTER=29 109 RSVD31 : org = 0xF0000000 len = 0x00010000 CREGISTER=31
107 MSMC : org = 0xE0000000 len = 0x00010000 CREGISTER=30
108 R5_RAM : org = 0xF0000000 len = 0x00010000 CREGISTER=31
109} 110}
110 111
111/* Specify the sections allocation into memory */ 112/* Specify the sections allocation into memory */
@@ -115,17 +116,17 @@ SECTIONS {
115 .text:_c_int00* > 0x0, PAGE 0 116 .text:_c_int00* > 0x0, PAGE 0
116 117
117 .text > PRU_IMEM, PAGE 0 118 .text > PRU_IMEM, PAGE 0
118 .stack > PRU_DMEM_0_1, PAGE 1 119 .stack > PRU0_DMEM_0, PAGE 1
119 .bss > PRU_DMEM_0_1, PAGE 1 120 .bss > PRU0_DMEM_0, PAGE 1
120 .cio > PRU_DMEM_0_1, PAGE 1 121 .cio > PRU0_DMEM_0, PAGE 1
121 .data > PRU_DMEM_0_1, PAGE 1 122 .data > PRU0_DMEM_0, PAGE 1
122 .switch > PRU_DMEM_0_1, PAGE 1 123 .switch > PRU0_DMEM_0, PAGE 1
123 .sysmem > PRU_DMEM_0_1, PAGE 1 124 .sysmem > PRU0_DMEM_0, PAGE 1
124 .cinit > PRU_DMEM_0_1, PAGE 1 125 .cinit > PRU0_DMEM_0, PAGE 1
125 .rodata > PRU_DMEM_0_1, PAGE 1 126 .rodata > PRU0_DMEM_0, PAGE 1
126 .rofardata > PRU_DMEM_0_1, PAGE 1 127 .rofardata > PRU0_DMEM_0, PAGE 1
127 .farbss > PRU_DMEM_0_1, PAGE 1 128 .farbss > PRU0_DMEM_0, PAGE 1
128 .fardata > PRU_DMEM_0_1, PAGE 1 129 .fardata > PRU0_DMEM_0, PAGE 1
129 130
130 .resource_table > PRU_DMEM_0_1, PAGE 1 131 .resource_table > PRU0_DMEM_0, PAGE 1
131} 132}
diff --git a/labs/Getting_Started_Labs/c_and_inline_assembly/solution/am65x/AM65x_PRU0.cmd b/labs/Getting_Started_Labs/c_and_inline_assembly/solution/am65x/AM65x_PRU0.cmd
index fed8ee4..45f8722 100644
--- a/labs/Getting_Started_Labs/c_and_inline_assembly/solution/am65x/AM65x_PRU0.cmd
+++ b/labs/Getting_Started_Labs/c_and_inline_assembly/solution/am65x/AM65x_PRU0.cmd
@@ -4,7 +4,7 @@
4 * Example Linker command file for linking programs built with the C compiler 4 * Example Linker command file for linking programs built with the C compiler
5 * on AM65x PRU0 cores 5 * on AM65x PRU0 cores
6 * 6 *
7 * Copyright (C) 2017-2018 Texas Instruments Incorporated - http://www.ti.com/ 7 * Copyright (C) 2017-2020 Texas Instruments Incorporated - http://www.ti.com/
8 * 8 *
9 * Redistribution and use in source and binary forms, with or without 9 * Redistribution and use in source and binary forms, with or without
10 * modification, are permitted provided that the following conditions 10 * modification, are permitted provided that the following conditions
@@ -41,25 +41,28 @@
41MEMORY 41MEMORY
42{ 42{
43 PAGE 0: 43 PAGE 0:
44 /* 16kB PRU Instruction RAM */ 44 /* 16 KB PRU Instruction RAM */
45 PRU_IMEM : org = 0x00000000 len = 0x00004000 45 PRU_IMEM : org = 0x00000000 len = 0x00004000
46 46
47 PAGE 1: 47 PAGE 1:
48 /* Data RAMs */ 48 /* Data RAMs */
49 /* 8kB PRU Data RAM 0_1; use only the first page for PRU0 and reserve 49 /* 8 KB PRU Data RAM 0; use only the first 4 KB for PRU0 and reserve
50 * the second page for RTU0 */ 50 * the second 4 KB for RTU0 and Tx_PRU0 */
51 PRU_DMEM_0_1 : org = 0x00000000 len = 0x00001000 CREGISTER=24 51 PRU0_DMEM_0 : org = 0x00000000 len = 0x00001000 CREGISTER=24
52 /* 8kB PRU Data RAM 1_0; use only the first page for PRU1 and reserve 52 /* 8 KB PRU Data RAM 1; reserved completely for Slice1 cores - PRU1,
53 * the second page for RTU1 */ 53 * RTU1 and Tx_PRU1; do not use for any Slice0 cores */
54 PRU_DMEM_1_0 : org = 0x00002000 len = 0x00001000 CREGISTER=25 54 PRU0_DMEM_1 : org = 0x00002000 len = 0x00001000 CREGISTER=25
55 /* NOTE: Customized to reserve the second 4K of ICSS Data RAMs 0 and 1 so 55 /* NOTE: Custom split of the second 4 KB of ICSS Data RAMs 0 and 1
56 as not to conflict with corresponding RTU core usage */ 56 * split equally between the corresponding RTU and Tx_PRU cores in
57 RTU_DMEM_0_1 : org = 0x00001000 len = 0x00001000 57 * each slice */
58 RTU_DMEM_1_0 : org = 0x00003000 len = 0x00001000 58 RTU0_DMEM_0 : org = 0x00001000 len = 0x00000800
59 TX_PRU0_DMEM_0 : org = 0x00001800 len = 0x00000800
60 RTU0_DMEM_1 : org = 0x00003000 len = 0x00000800
61 TX_PRU0_DMEM_1 : org = 0x00003800 len = 0x00000800
59 62
60 PAGE 2: 63 PAGE 2:
61 /* C28 needs to be programmed to point to SHAREDMEM, default is 0 */ 64 /* C28 needs to be programmed to point to SHAREDMEM, default is 0 */
62 /* 64kB PRU Shared RAM */ 65 /* 64 KB PRU Shared RAM */
63 PRU_SHAREDMEM : org = 0x00010000 len = 0x00010000 CREGISTER=28 66 PRU_SHAREDMEM : org = 0x00010000 len = 0x00010000 CREGISTER=28
64 67
65 /* Internal Peripherals */ 68 /* Internal Peripherals */
@@ -68,17 +71,17 @@ MEMORY
68 * Register #6 that starts at 0x200 offset within INTC */ 71 * Register #6 that starts at 0x200 offset within INTC */
69 PRU_INTC : org = 0x00020000 len = 0x00001504 CREGISTER=0 72 PRU_INTC : org = 0x00020000 len = 0x00001504 CREGISTER=0
70 PRU_IEP1 : org = 0x0002F000 len = 0x00000100 CREGISTER=1 73 PRU_IEP1 : org = 0x0002F000 len = 0x00000100 CREGISTER=1
71 PRU_IEP1_EXT : org = 0x0002F100 len = 0x0000021C CREGISTER=2 74 PRU_IEP1_0x100 : org = 0x0002F100 len = 0x0000021C CREGISTER=2
72 PRU_ECAP : org = 0x00030000 len = 0x00000060 CREGISTER=3 75 PRU_ECAP : org = 0x00030000 len = 0x00000060 CREGISTER=3
73 PRU_CFG : org = 0x00026000 len = 0x00000100 CREGISTER=4 76 PRU_CFG : org = 0x00026000 len = 0x00000100 CREGISTER=4
74 PRU_CFG_EXT : org = 0x00026100 len = 0x00000098 CREGISTER=5 77 PRU_CFG_0x100 : org = 0x00026100 len = 0x00000098 CREGISTER=5
75 /* XXX: This value is part of INTC space, and is therefore commented 78 /* XXX: This value is part of INTC space, and is therefore commented
76 * out as it conflicts with PRU_INTC size above. Using this requires 79 * out as it conflicts with PRU_INTC size above. Using this requires
77 * splitting up the pruIntc structure and CT_INTC variable from 80 * splitting up the pruIntc structure and CT_INTC variable from
78 * pru_intc.h */ 81 * pru_intc.h */
79 /*PRU_INTC_EXT : org = 0x00040200 len = 0x00001304 CREGISTER=6*/ 82 /*PRU_INTC_0x200: org = 0x00020200 len = 0x00001304 CREGISTER=6*/
80 PRU_UART : org = 0x00028000 len = 0x00000038 CREGISTER=7 83 PRU_UART : org = 0x00028000 len = 0x00000038 CREGISTER=7
81 PRU_IEP0_EXT : org = 0x0002E100 len = 0x0000021C CREGISTER=8 84 PRU_IEP0_0x100 : org = 0x0002E100 len = 0x0000021C CREGISTER=8
82 MII_G_RT : org = 0x00033000 len = 0x00000C18 CREGISTER=9 85 MII_G_RT : org = 0x00033000 len = 0x00000C18 CREGISTER=9
83 TM_CFG_PRU0 : org = 0x0002A000 len = 0x0000004C CREGISTER=10 86 TM_CFG_PRU0 : org = 0x0002A000 len = 0x0000004C CREGISTER=10
84 PRU0_CTRL : org = 0x00022000 len = 0x00000088 CREGISTER=11 87 PRU0_CTRL : org = 0x00022000 len = 0x00000088 CREGISTER=11
@@ -89,23 +92,21 @@ MEMORY
89 MII_MDIO : org = 0x00032400 len = 0x00000090 CREGISTER=21 92 MII_MDIO : org = 0x00032400 len = 0x00000090 CREGISTER=21
90 PRU_RTU_RAT0 : org = 0x00008000 len = 0x00000854 CREGISTER=22 93 PRU_RTU_RAT0 : org = 0x00008000 len = 0x00000854 CREGISTER=22
91 PRU_IEP0 : org = 0x0002E000 len = 0x00000100 CREGISTER=26 94 PRU_IEP0 : org = 0x0002E000 len = 0x00000100 CREGISTER=26
92 MII_RT_CFG : org = 0x00032000 len = 0x0000024C CREGISTER=27 95 MII_RT : org = 0x00032000 len = 0x0000024C CREGISTER=27
93 96
94 /* External Regions */ 97 /* External Regions */
95 /* FIXME: Random length of 0x1000 assigned to the below regions */ 98 /* Random length 0x1000 assigned to the below regions */
96 TIMER_MANAGER : org = 0x60000000 len = 0x00001000 CREGISTER=15 99 RSVD15 : org = 0x60000000 len = 0x00001000 CREGISTER=15
97 RING_ACCELERATOR: org = 0x70000000 len = 0x00001000 CREGISTER=16 100 RSVD16 : org = 0x70000000 len = 0x00001000 CREGISTER=16
98 INTERRUPT_AGGREGATOR: org = 0x80000000 len = 0x00001000 CREGISTER=17 101 RSVD17 : org = 0x80000000 len = 0x00001000 CREGISTER=17
99 GPMC : org = 0x90000000 len = 0x00001000 CREGISTER=18 102 RSVD18 : org = 0x90000000 len = 0x00001000 CREGISTER=18
100 PCIE : org = 0xA0000000 len = 0x00001000 CREGISTER=19 103 RSVD19 : org = 0xA0000000 len = 0x00001000 CREGISTER=19
101 UDMA_P : org = 0xB0000000 len = 0x00001000 CREGISTER=20 104 RSVD20 : org = 0xB0000000 len = 0x00001000 CREGISTER=20
102 ADC : org = 0xC0000000 len = 0x00001000 CREGISTER=23 105 RSVD23 : org = 0xC0000000 len = 0x00001000 CREGISTER=23
103 106 /* Random length 0x10000 (max len value) assigned to programmable C29-31*/
104 /* External Memory */ 107 RSVD29 : org = 0xD0000000 len = 0x00010000 CREGISTER=29
105 /* Random length of 0x10000 (max len value) assigned to all regions */ 108 RSVD30 : org = 0xE0000000 len = 0x00010000 CREGISTER=30
106 DDR : org = 0xD0000000 len = 0x00010000 CREGISTER=29 109 RSVD31 : org = 0xF0000000 len = 0x00010000 CREGISTER=31
107 MSMC : org = 0xE0000000 len = 0x00010000 CREGISTER=30
108 R5_RAM : org = 0xF0000000 len = 0x00010000 CREGISTER=31
109} 110}
110 111
111/* Specify the sections allocation into memory */ 112/* Specify the sections allocation into memory */
@@ -115,17 +116,17 @@ SECTIONS {
115 .text:_c_int00* > 0x0, PAGE 0 116 .text:_c_int00* > 0x0, PAGE 0
116 117
117 .text > PRU_IMEM, PAGE 0 118 .text > PRU_IMEM, PAGE 0
118 .stack > PRU_DMEM_0_1, PAGE 1 119 .stack > PRU0_DMEM_0, PAGE 1
119 .bss > PRU_DMEM_0_1, PAGE 1 120 .bss > PRU0_DMEM_0, PAGE 1
120 .cio > PRU_DMEM_0_1, PAGE 1 121 .cio > PRU0_DMEM_0, PAGE 1
121 .data > PRU_DMEM_0_1, PAGE 1 122 .data > PRU0_DMEM_0, PAGE 1
122 .switch > PRU_DMEM_0_1, PAGE 1 123 .switch > PRU0_DMEM_0, PAGE 1
123 .sysmem > PRU_DMEM_0_1, PAGE 1 124 .sysmem > PRU0_DMEM_0, PAGE 1
124 .cinit > PRU_DMEM_0_1, PAGE 1 125 .cinit > PRU0_DMEM_0, PAGE 1
125 .rodata > PRU_DMEM_0_1, PAGE 1 126 .rodata > PRU0_DMEM_0, PAGE 1
126 .rofardata > PRU_DMEM_0_1, PAGE 1 127 .rofardata > PRU0_DMEM_0, PAGE 1
127 .farbss > PRU_DMEM_0_1, PAGE 1 128 .farbss > PRU0_DMEM_0, PAGE 1
128 .fardata > PRU_DMEM_0_1, PAGE 1 129 .fardata > PRU0_DMEM_0, PAGE 1
129 130
130 .resource_table > PRU_DMEM_0_1, PAGE 1 131 .resource_table > PRU0_DMEM_0, PAGE 1
131} 132}
diff --git a/labs/Getting_Started_Labs/c_code/solution/am65x/AM65x_PRU0.cmd b/labs/Getting_Started_Labs/c_code/solution/am65x/AM65x_PRU0.cmd
index fed8ee4..45f8722 100644
--- a/labs/Getting_Started_Labs/c_code/solution/am65x/AM65x_PRU0.cmd
+++ b/labs/Getting_Started_Labs/c_code/solution/am65x/AM65x_PRU0.cmd
@@ -4,7 +4,7 @@
4 * Example Linker command file for linking programs built with the C compiler 4 * Example Linker command file for linking programs built with the C compiler
5 * on AM65x PRU0 cores 5 * on AM65x PRU0 cores
6 * 6 *
7 * Copyright (C) 2017-2018 Texas Instruments Incorporated - http://www.ti.com/ 7 * Copyright (C) 2017-2020 Texas Instruments Incorporated - http://www.ti.com/
8 * 8 *
9 * Redistribution and use in source and binary forms, with or without 9 * Redistribution and use in source and binary forms, with or without
10 * modification, are permitted provided that the following conditions 10 * modification, are permitted provided that the following conditions
@@ -41,25 +41,28 @@
41MEMORY 41MEMORY
42{ 42{
43 PAGE 0: 43 PAGE 0:
44 /* 16kB PRU Instruction RAM */ 44 /* 16 KB PRU Instruction RAM */
45 PRU_IMEM : org = 0x00000000 len = 0x00004000 45 PRU_IMEM : org = 0x00000000 len = 0x00004000
46 46
47 PAGE 1: 47 PAGE 1:
48 /* Data RAMs */ 48 /* Data RAMs */
49 /* 8kB PRU Data RAM 0_1; use only the first page for PRU0 and reserve 49 /* 8 KB PRU Data RAM 0; use only the first 4 KB for PRU0 and reserve
50 * the second page for RTU0 */ 50 * the second 4 KB for RTU0 and Tx_PRU0 */
51 PRU_DMEM_0_1 : org = 0x00000000 len = 0x00001000 CREGISTER=24 51 PRU0_DMEM_0 : org = 0x00000000 len = 0x00001000 CREGISTER=24
52 /* 8kB PRU Data RAM 1_0; use only the first page for PRU1 and reserve 52 /* 8 KB PRU Data RAM 1; reserved completely for Slice1 cores - PRU1,
53 * the second page for RTU1 */ 53 * RTU1 and Tx_PRU1; do not use for any Slice0 cores */
54 PRU_DMEM_1_0 : org = 0x00002000 len = 0x00001000 CREGISTER=25 54 PRU0_DMEM_1 : org = 0x00002000 len = 0x00001000 CREGISTER=25
55 /* NOTE: Customized to reserve the second 4K of ICSS Data RAMs 0 and 1 so 55 /* NOTE: Custom split of the second 4 KB of ICSS Data RAMs 0 and 1
56 as not to conflict with corresponding RTU core usage */ 56 * split equally between the corresponding RTU and Tx_PRU cores in
57 RTU_DMEM_0_1 : org = 0x00001000 len = 0x00001000 57 * each slice */
58 RTU_DMEM_1_0 : org = 0x00003000 len = 0x00001000 58 RTU0_DMEM_0 : org = 0x00001000 len = 0x00000800
59 TX_PRU0_DMEM_0 : org = 0x00001800 len = 0x00000800
60 RTU0_DMEM_1 : org = 0x00003000 len = 0x00000800
61 TX_PRU0_DMEM_1 : org = 0x00003800 len = 0x00000800
59 62
60 PAGE 2: 63 PAGE 2:
61 /* C28 needs to be programmed to point to SHAREDMEM, default is 0 */ 64 /* C28 needs to be programmed to point to SHAREDMEM, default is 0 */
62 /* 64kB PRU Shared RAM */ 65 /* 64 KB PRU Shared RAM */
63 PRU_SHAREDMEM : org = 0x00010000 len = 0x00010000 CREGISTER=28 66 PRU_SHAREDMEM : org = 0x00010000 len = 0x00010000 CREGISTER=28
64 67
65 /* Internal Peripherals */ 68 /* Internal Peripherals */
@@ -68,17 +71,17 @@ MEMORY
68 * Register #6 that starts at 0x200 offset within INTC */ 71 * Register #6 that starts at 0x200 offset within INTC */
69 PRU_INTC : org = 0x00020000 len = 0x00001504 CREGISTER=0 72 PRU_INTC : org = 0x00020000 len = 0x00001504 CREGISTER=0
70 PRU_IEP1 : org = 0x0002F000 len = 0x00000100 CREGISTER=1 73 PRU_IEP1 : org = 0x0002F000 len = 0x00000100 CREGISTER=1
71 PRU_IEP1_EXT : org = 0x0002F100 len = 0x0000021C CREGISTER=2 74 PRU_IEP1_0x100 : org = 0x0002F100 len = 0x0000021C CREGISTER=2
72 PRU_ECAP : org = 0x00030000 len = 0x00000060 CREGISTER=3 75 PRU_ECAP : org = 0x00030000 len = 0x00000060 CREGISTER=3
73 PRU_CFG : org = 0x00026000 len = 0x00000100 CREGISTER=4 76 PRU_CFG : org = 0x00026000 len = 0x00000100 CREGISTER=4
74 PRU_CFG_EXT : org = 0x00026100 len = 0x00000098 CREGISTER=5 77 PRU_CFG_0x100 : org = 0x00026100 len = 0x00000098 CREGISTER=5
75 /* XXX: This value is part of INTC space, and is therefore commented 78 /* XXX: This value is part of INTC space, and is therefore commented
76 * out as it conflicts with PRU_INTC size above. Using this requires 79 * out as it conflicts with PRU_INTC size above. Using this requires
77 * splitting up the pruIntc structure and CT_INTC variable from 80 * splitting up the pruIntc structure and CT_INTC variable from
78 * pru_intc.h */ 81 * pru_intc.h */
79 /*PRU_INTC_EXT : org = 0x00040200 len = 0x00001304 CREGISTER=6*/ 82 /*PRU_INTC_0x200: org = 0x00020200 len = 0x00001304 CREGISTER=6*/
80 PRU_UART : org = 0x00028000 len = 0x00000038 CREGISTER=7 83 PRU_UART : org = 0x00028000 len = 0x00000038 CREGISTER=7
81 PRU_IEP0_EXT : org = 0x0002E100 len = 0x0000021C CREGISTER=8 84 PRU_IEP0_0x100 : org = 0x0002E100 len = 0x0000021C CREGISTER=8
82 MII_G_RT : org = 0x00033000 len = 0x00000C18 CREGISTER=9 85 MII_G_RT : org = 0x00033000 len = 0x00000C18 CREGISTER=9
83 TM_CFG_PRU0 : org = 0x0002A000 len = 0x0000004C CREGISTER=10 86 TM_CFG_PRU0 : org = 0x0002A000 len = 0x0000004C CREGISTER=10
84 PRU0_CTRL : org = 0x00022000 len = 0x00000088 CREGISTER=11 87 PRU0_CTRL : org = 0x00022000 len = 0x00000088 CREGISTER=11
@@ -89,23 +92,21 @@ MEMORY
89 MII_MDIO : org = 0x00032400 len = 0x00000090 CREGISTER=21 92 MII_MDIO : org = 0x00032400 len = 0x00000090 CREGISTER=21
90 PRU_RTU_RAT0 : org = 0x00008000 len = 0x00000854 CREGISTER=22 93 PRU_RTU_RAT0 : org = 0x00008000 len = 0x00000854 CREGISTER=22
91 PRU_IEP0 : org = 0x0002E000 len = 0x00000100 CREGISTER=26 94 PRU_IEP0 : org = 0x0002E000 len = 0x00000100 CREGISTER=26
92 MII_RT_CFG : org = 0x00032000 len = 0x0000024C CREGISTER=27 95 MII_RT : org = 0x00032000 len = 0x0000024C CREGISTER=27
93 96
94 /* External Regions */ 97 /* External Regions */
95 /* FIXME: Random length of 0x1000 assigned to the below regions */ 98 /* Random length 0x1000 assigned to the below regions */
96 TIMER_MANAGER : org = 0x60000000 len = 0x00001000 CREGISTER=15 99 RSVD15 : org = 0x60000000 len = 0x00001000 CREGISTER=15
97 RING_ACCELERATOR: org = 0x70000000 len = 0x00001000 CREGISTER=16 100 RSVD16 : org = 0x70000000 len = 0x00001000 CREGISTER=16
98 INTERRUPT_AGGREGATOR: org = 0x80000000 len = 0x00001000 CREGISTER=17 101 RSVD17 : org = 0x80000000 len = 0x00001000 CREGISTER=17
99 GPMC : org = 0x90000000 len = 0x00001000 CREGISTER=18 102 RSVD18 : org = 0x90000000 len = 0x00001000 CREGISTER=18
100 PCIE : org = 0xA0000000 len = 0x00001000 CREGISTER=19 103 RSVD19 : org = 0xA0000000 len = 0x00001000 CREGISTER=19
101 UDMA_P : org = 0xB0000000 len = 0x00001000 CREGISTER=20 104 RSVD20 : org = 0xB0000000 len = 0x00001000 CREGISTER=20
102 ADC : org = 0xC0000000 len = 0x00001000 CREGISTER=23 105 RSVD23 : org = 0xC0000000 len = 0x00001000 CREGISTER=23
103 106 /* Random length 0x10000 (max len value) assigned to programmable C29-31*/
104 /* External Memory */ 107 RSVD29 : org = 0xD0000000 len = 0x00010000 CREGISTER=29
105 /* Random length of 0x10000 (max len value) assigned to all regions */ 108 RSVD30 : org = 0xE0000000 len = 0x00010000 CREGISTER=30
106 DDR : org = 0xD0000000 len = 0x00010000 CREGISTER=29 109 RSVD31 : org = 0xF0000000 len = 0x00010000 CREGISTER=31
107 MSMC : org = 0xE0000000 len = 0x00010000 CREGISTER=30
108 R5_RAM : org = 0xF0000000 len = 0x00010000 CREGISTER=31
109} 110}
110 111
111/* Specify the sections allocation into memory */ 112/* Specify the sections allocation into memory */
@@ -115,17 +116,17 @@ SECTIONS {
115 .text:_c_int00* > 0x0, PAGE 0 116 .text:_c_int00* > 0x0, PAGE 0
116 117
117 .text > PRU_IMEM, PAGE 0 118 .text > PRU_IMEM, PAGE 0
118 .stack > PRU_DMEM_0_1, PAGE 1 119 .stack > PRU0_DMEM_0, PAGE 1
119 .bss > PRU_DMEM_0_1, PAGE 1 120 .bss > PRU0_DMEM_0, PAGE 1
120 .cio > PRU_DMEM_0_1, PAGE 1 121 .cio > PRU0_DMEM_0, PAGE 1
121 .data > PRU_DMEM_0_1, PAGE 1 122 .data > PRU0_DMEM_0, PAGE 1
122 .switch > PRU_DMEM_0_1, PAGE 1 123 .switch > PRU0_DMEM_0, PAGE 1
123 .sysmem > PRU_DMEM_0_1, PAGE 1 124 .sysmem > PRU0_DMEM_0, PAGE 1
124 .cinit > PRU_DMEM_0_1, PAGE 1 125 .cinit > PRU0_DMEM_0, PAGE 1
125 .rodata > PRU_DMEM_0_1, PAGE 1 126 .rodata > PRU0_DMEM_0, PAGE 1
126 .rofardata > PRU_DMEM_0_1, PAGE 1 127 .rofardata > PRU0_DMEM_0, PAGE 1
127 .farbss > PRU_DMEM_0_1, PAGE 1 128 .farbss > PRU0_DMEM_0, PAGE 1
128 .fardata > PRU_DMEM_0_1, PAGE 1 129 .fardata > PRU0_DMEM_0, PAGE 1
129 130
130 .resource_table > PRU_DMEM_0_1, PAGE 1 131 .resource_table > PRU0_DMEM_0, PAGE 1
131} 132}
diff --git a/labs/Getting_Started_Labs/linker_cmd/AM65x_PRU0.cmd b/labs/Getting_Started_Labs/linker_cmd/AM65x_PRU0.cmd
index 1d30745..45f8722 100644
--- a/labs/Getting_Started_Labs/linker_cmd/AM65x_PRU0.cmd
+++ b/labs/Getting_Started_Labs/linker_cmd/AM65x_PRU0.cmd
@@ -4,7 +4,7 @@
4 * Example Linker command file for linking programs built with the C compiler 4 * Example Linker command file for linking programs built with the C compiler
5 * on AM65x PRU0 cores 5 * on AM65x PRU0 cores
6 * 6 *
7 * Copyright (C) 2017-2018 Texas Instruments Incorporated - http://www.ti.com/ 7 * Copyright (C) 2017-2020 Texas Instruments Incorporated - http://www.ti.com/
8 * 8 *
9 * Redistribution and use in source and binary forms, with or without 9 * Redistribution and use in source and binary forms, with or without
10 * modification, are permitted provided that the following conditions 10 * modification, are permitted provided that the following conditions
@@ -41,25 +41,28 @@
41MEMORY 41MEMORY
42{ 42{
43 PAGE 0: 43 PAGE 0:
44 /* 16kB PRU Instruction RAM */ 44 /* 16 KB PRU Instruction RAM */
45 PRU_IMEM : org = 0x00000000 len = 0x00004000 45 PRU_IMEM : org = 0x00000000 len = 0x00004000
46 46
47 PAGE 1: 47 PAGE 1:
48 /* Data RAMs */ 48 /* Data RAMs */
49 /* 8kB PRU Data RAM 0_1; use only the first page for PRU0 and reserve 49 /* 8 KB PRU Data RAM 0; use only the first 4 KB for PRU0 and reserve
50 * the second page for RTU0 */ 50 * the second 4 KB for RTU0 and Tx_PRU0 */
51 PRU_DMEM_0_1 : org = 0x00000000 len = 0x00001000 CREGISTER=24 51 PRU0_DMEM_0 : org = 0x00000000 len = 0x00001000 CREGISTER=24
52 /* 8kB PRU Data RAM 1_0; use only the first page for PRU1 and reserve 52 /* 8 KB PRU Data RAM 1; reserved completely for Slice1 cores - PRU1,
53 * the second page for RTU1 */ 53 * RTU1 and Tx_PRU1; do not use for any Slice0 cores */
54 PRU_DMEM_1_0 : org = 0x00002000 len = 0x00001000 CREGISTER=25 54 PRU0_DMEM_1 : org = 0x00002000 len = 0x00001000 CREGISTER=25
55 /* NOTE: Customized to reserve the second 4K of ICSS Data RAMs 0 and 1 so 55 /* NOTE: Custom split of the second 4 KB of ICSS Data RAMs 0 and 1
56 as not to conflict with corresponding RTU core usage */ 56 * split equally between the corresponding RTU and Tx_PRU cores in
57 RTU_DMEM_0_1 : org = 0x00001000 len = 0x00001000 57 * each slice */
58 RTU_DMEM_1_0 : org = 0x00003000 len = 0x00001000 58 RTU0_DMEM_0 : org = 0x00001000 len = 0x00000800
59 TX_PRU0_DMEM_0 : org = 0x00001800 len = 0x00000800
60 RTU0_DMEM_1 : org = 0x00003000 len = 0x00000800
61 TX_PRU0_DMEM_1 : org = 0x00003800 len = 0x00000800
59 62
60 PAGE 2: 63 PAGE 2:
61 /* C28 needs to be programmed to point to SHAREDMEM, default is 0 */ 64 /* C28 needs to be programmed to point to SHAREDMEM, default is 0 */
62 /* 64kB PRU Shared RAM */ 65 /* 64 KB PRU Shared RAM */
63 PRU_SHAREDMEM : org = 0x00010000 len = 0x00010000 CREGISTER=28 66 PRU_SHAREDMEM : org = 0x00010000 len = 0x00010000 CREGISTER=28
64 67
65 /* Internal Peripherals */ 68 /* Internal Peripherals */
@@ -76,7 +79,7 @@ MEMORY
76 * out as it conflicts with PRU_INTC size above. Using this requires 79 * out as it conflicts with PRU_INTC size above. Using this requires
77 * splitting up the pruIntc structure and CT_INTC variable from 80 * splitting up the pruIntc structure and CT_INTC variable from
78 * pru_intc.h */ 81 * pru_intc.h */
79 /*PRU_INTC_0x200: org = 0x00040200 len = 0x00001304 CREGISTER=6*/ 82 /*PRU_INTC_0x200: org = 0x00020200 len = 0x00001304 CREGISTER=6*/
80 PRU_UART : org = 0x00028000 len = 0x00000038 CREGISTER=7 83 PRU_UART : org = 0x00028000 len = 0x00000038 CREGISTER=7
81 PRU_IEP0_0x100 : org = 0x0002E100 len = 0x0000021C CREGISTER=8 84 PRU_IEP0_0x100 : org = 0x0002E100 len = 0x0000021C CREGISTER=8
82 MII_G_RT : org = 0x00033000 len = 0x00000C18 CREGISTER=9 85 MII_G_RT : org = 0x00033000 len = 0x00000C18 CREGISTER=9
@@ -113,17 +116,17 @@ SECTIONS {
113 .text:_c_int00* > 0x0, PAGE 0 116 .text:_c_int00* > 0x0, PAGE 0
114 117
115 .text > PRU_IMEM, PAGE 0 118 .text > PRU_IMEM, PAGE 0
116 .stack > PRU_DMEM_0_1, PAGE 1 119 .stack > PRU0_DMEM_0, PAGE 1
117 .bss > PRU_DMEM_0_1, PAGE 1 120 .bss > PRU0_DMEM_0, PAGE 1
118 .cio > PRU_DMEM_0_1, PAGE 1 121 .cio > PRU0_DMEM_0, PAGE 1
119 .data > PRU_DMEM_0_1, PAGE 1 122 .data > PRU0_DMEM_0, PAGE 1
120 .switch > PRU_DMEM_0_1, PAGE 1 123 .switch > PRU0_DMEM_0, PAGE 1
121 .sysmem > PRU_DMEM_0_1, PAGE 1 124 .sysmem > PRU0_DMEM_0, PAGE 1
122 .cinit > PRU_DMEM_0_1, PAGE 1 125 .cinit > PRU0_DMEM_0, PAGE 1
123 .rodata > PRU_DMEM_0_1, PAGE 1 126 .rodata > PRU0_DMEM_0, PAGE 1
124 .rofardata > PRU_DMEM_0_1, PAGE 1 127 .rofardata > PRU0_DMEM_0, PAGE 1
125 .farbss > PRU_DMEM_0_1, PAGE 1 128 .farbss > PRU0_DMEM_0, PAGE 1
126 .fardata > PRU_DMEM_0_1, PAGE 1 129 .fardata > PRU0_DMEM_0, PAGE 1
127 130
128 .resource_table > PRU_DMEM_0_1, PAGE 1 131 .resource_table > PRU0_DMEM_0, PAGE 1
129} 132}
diff --git a/labs/Getting_Started_Labs/linker_cmd/AM65x_PRU1.cmd b/labs/Getting_Started_Labs/linker_cmd/AM65x_PRU1.cmd
index 43b8174..ef4bef5 100644
--- a/labs/Getting_Started_Labs/linker_cmd/AM65x_PRU1.cmd
+++ b/labs/Getting_Started_Labs/linker_cmd/AM65x_PRU1.cmd
@@ -4,7 +4,7 @@
4 * Example Linker command file for linking programs built with the C compiler 4 * Example Linker command file for linking programs built with the C compiler
5 * on AM65x PRU1 cores 5 * on AM65x PRU1 cores
6 * 6 *
7 * Copyright (C) 2017-2018 Texas Instruments Incorporated - http://www.ti.com/ 7 * Copyright (C) 2017-2020 Texas Instruments Incorporated - http://www.ti.com/
8 * 8 *
9 * Redistribution and use in source and binary forms, with or without 9 * Redistribution and use in source and binary forms, with or without
10 * modification, are permitted provided that the following conditions 10 * modification, are permitted provided that the following conditions
@@ -41,25 +41,28 @@
41MEMORY 41MEMORY
42{ 42{
43 PAGE 0: 43 PAGE 0:
44 /* 16kB PRU Instruction RAM */ 44 /* 16 KB PRU Instruction RAM */
45 PRU_IMEM : org = 0x00000000 len = 0x00004000 45 PRU_IMEM : org = 0x00000000 len = 0x00004000
46 46
47 PAGE 1: 47 PAGE 1:
48 /* Data RAMs */ 48 /* Data RAMs */
49 /* 8kB PRU Data RAM 0_1; use only the first page for PRU1 and reserve 49 /* 8 KB PRU Data RAM 1; use only the first 4 KB for PRU1 and reserve
50 * the second page for RTU1 */ 50 * the second 4 KB for RTU1 and Tx_PRU1 */
51 PRU_DMEM_0_1 : org = 0x00000000 len = 0x00001000 CREGISTER=24 51 PRU1_DMEM_1 : org = 0x00000000 len = 0x00001000 CREGISTER=24
52 /* 8kB PRU Data RAM 1_0; use only the first page for PRU0 and reserve 52 /* 8 KB PRU Data RAM 0; reserved completely for Slice0 cores - PRU0,
53 * the second page for RTU0 */ 53 * RTU0 and Tx_PRU0; do not use for any Slice1 cores */
54 PRU_DMEM_1_0 : org = 0x00002000 len = 0x00001000 CREGISTER=25 54 PRU1_DMEM_0 : org = 0x00002000 len = 0x00001000 CREGISTER=25
55 /* NOTE: Customized to reserve the second 4K of ICSS Data RAMs 0 and 1 so 55 /* NOTE: Custom split of the second 4 KB of ICSS Data RAMs 0 and 1
56 as not to conflict with corresponding RTU core usage */ 56 * split equally between the corresponding RTU and Tx_PRU cores in
57 RTU_DMEM_0_1 : org = 0x00001000 len = 0x00001000 57 * each slice */
58 RTU_DMEM_1_0 : org = 0x00003000 len = 0x00001000 58 RTU1_DMEM_1 : org = 0x00001000 len = 0x00000800
59 TX_PRU1_DMEM_1 : org = 0x00001800 len = 0x00000800
60 RTU1_DMEM_0 : org = 0x00003000 len = 0x00000800
61 TX_PRU1_DMEM_0 : org = 0x00003800 len = 0x00000800
59 62
60 PAGE 2: 63 PAGE 2:
61 /* C28 needs to be programmed to point to SHAREDMEM, default is 0 */ 64 /* C28 needs to be programmed to point to SHAREDMEM, default is 0 */
62 /* 64kB PRU Shared RAM */ 65 /* 64 KB PRU Shared RAM */
63 PRU_SHAREDMEM : org = 0x00010000 len = 0x00010000 CREGISTER=28 66 PRU_SHAREDMEM : org = 0x00010000 len = 0x00010000 CREGISTER=28
64 67
65 /* Internal Peripherals */ 68 /* Internal Peripherals */
@@ -76,7 +79,7 @@ MEMORY
76 * out as it conflicts with PRU_INTC size above. Using this requires 79 * out as it conflicts with PRU_INTC size above. Using this requires
77 * splitting up the pruIntc structure and CT_INTC variable from 80 * splitting up the pruIntc structure and CT_INTC variable from
78 * pru_intc.h */ 81 * pru_intc.h */
79 /*PRU_INTC_0x200: org = 0x00040200 len = 0x00001304 CREGISTER=6*/ 82 /*PRU_INTC_0x200: org = 0x00020200 len = 0x00001304 CREGISTER=6*/
80 PRU_UART : org = 0x00028000 len = 0x00000038 CREGISTER=7 83 PRU_UART : org = 0x00028000 len = 0x00000038 CREGISTER=7
81 PRU_IEP0_0x100 : org = 0x0002E100 len = 0x0000021C CREGISTER=8 84 PRU_IEP0_0x100 : org = 0x0002E100 len = 0x0000021C CREGISTER=8
82 MII_G_RT : org = 0x00033000 len = 0x00000C18 CREGISTER=9 85 MII_G_RT : org = 0x00033000 len = 0x00000C18 CREGISTER=9
@@ -89,7 +92,7 @@ MEMORY
89 MII_MDIO : org = 0x00032400 len = 0x00000090 CREGISTER=21 92 MII_MDIO : org = 0x00032400 len = 0x00000090 CREGISTER=21
90 PRU_RTU_RAT1 : org = 0x00009000 len = 0x00000854 CREGISTER=22 93 PRU_RTU_RAT1 : org = 0x00009000 len = 0x00000854 CREGISTER=22
91 PRU_IEP0 : org = 0x0002E000 len = 0x00000100 CREGISTER=26 94 PRU_IEP0 : org = 0x0002E000 len = 0x00000100 CREGISTER=26
92 MII_R : org = 0x00032000 len = 0x0000024C CREGISTER=27 95 MII_RT : org = 0x00032000 len = 0x0000024C CREGISTER=27
93 96
94 /* External Regions */ 97 /* External Regions */
95 /* Random length 0x1000 assigned to the below regions */ 98 /* Random length 0x1000 assigned to the below regions */
@@ -113,17 +116,17 @@ SECTIONS {
113 .text:_c_int00* > 0x0, PAGE 0 116 .text:_c_int00* > 0x0, PAGE 0
114 117
115 .text > PRU_IMEM, PAGE 0 118 .text > PRU_IMEM, PAGE 0
116 .stack > PRU_DMEM_0_1, PAGE 1 119 .stack > PRU1_DMEM_1, PAGE 1
117 .bss > PRU_DMEM_0_1, PAGE 1 120 .bss > PRU1_DMEM_1, PAGE 1
118 .cio > PRU_DMEM_0_1, PAGE 1 121 .cio > PRU1_DMEM_1, PAGE 1
119 .data > PRU_DMEM_0_1, PAGE 1 122 .data > PRU1_DMEM_1, PAGE 1
120 .switch > PRU_DMEM_0_1, PAGE 1 123 .switch > PRU1_DMEM_1, PAGE 1
121 .sysmem > PRU_DMEM_0_1, PAGE 1 124 .sysmem > PRU1_DMEM_1, PAGE 1
122 .cinit > PRU_DMEM_0_1, PAGE 1 125 .cinit > PRU1_DMEM_1, PAGE 1
123 .rodata > PRU_DMEM_0_1, PAGE 1 126 .rodata > PRU1_DMEM_1, PAGE 1
124 .rofardata > PRU_DMEM_0_1, PAGE 1 127 .rofardata > PRU1_DMEM_1, PAGE 1
125 .farbss > PRU_DMEM_0_1, PAGE 1 128 .farbss > PRU1_DMEM_1, PAGE 1
126 .fardata > PRU_DMEM_0_1, PAGE 1 129 .fardata > PRU1_DMEM_1, PAGE 1
127 130
128 .resource_table > PRU_DMEM_0_1, PAGE 1 131 .resource_table > PRU1_DMEM_1, PAGE 1
129} 132}
diff --git a/labs/Getting_Started_Labs/linker_cmd/AM65x_RTU0.cmd b/labs/Getting_Started_Labs/linker_cmd/AM65x_RTU0.cmd
index 1e94e98..ad6e710 100644
--- a/labs/Getting_Started_Labs/linker_cmd/AM65x_RTU0.cmd
+++ b/labs/Getting_Started_Labs/linker_cmd/AM65x_RTU0.cmd
@@ -4,7 +4,7 @@
4 * Example Linker command file for linking programs built with the C compiler 4 * Example Linker command file for linking programs built with the C compiler
5 * on AM65x RTU0 cores 5 * on AM65x RTU0 cores
6 * 6 *
7 * Copyright (C) 2017-2018 Texas Instruments Incorporated - http://www.ti.com/ 7 * Copyright (C) 2017-2020 Texas Instruments Incorporated - http://www.ti.com/
8 * 8 *
9 * Redistribution and use in source and binary forms, with or without 9 * Redistribution and use in source and binary forms, with or without
10 * modification, are permitted provided that the following conditions 10 * modification, are permitted provided that the following conditions
@@ -41,25 +41,28 @@
41MEMORY 41MEMORY
42{ 42{
43 PAGE 0: 43 PAGE 0:
44 /* 8kB RTU Instruction RAM */ 44 /* 8 KB RTU Instruction RAM */
45 RTU_IMEM : org = 0x00000000 len = 0x00002000 45 RTU_IMEM : org = 0x00000000 len = 0x00002000
46 46
47 PAGE 1: 47 PAGE 1:
48 /* Data RAMs */ 48 /* Data RAMs */
49 /* 8kB PRU Data RAM 0_1; use only the first page for PRU0 and reserve 49 /* 8 KB PRU Data RAM 0; use only the first 4 KB for PRU0 and reserve
50 * the second page for RTU0 */ 50 * the second 4 KB for RTU0 and Tx_PRU0 */
51 PRU_DMEM_0_1 : org = 0x00000000 len = 0x00001000 CREGISTER=24 51 PRU0_DMEM_0 : org = 0x00000000 len = 0x00001000 CREGISTER=24
52 /* 8kB PRU Data RAM 1_0; use only the first page for PRU1 and reserve 52 /* 8 KB PRU Data RAM 1; reserved completely for Slice1 cores - PRU1,
53 * the second page for RTU1 */ 53 * RTU1 and Tx_PRU1; do not use for any Slice0 cores */
54 PRU_DMEM_1_0 : org = 0x00002000 len = 0x00001000 CREGISTER=25 54 PRU0_DMEM_1 : org = 0x00002000 len = 0x00001000 CREGISTER=25
55 /* NOTE: Customized to use the second 4K of ICSS Data RAMs 0 and 1 so 55 /* NOTE: Custom split of the second 4 KB of ICSS Data RAMs 0 and 1
56 as not to conflict with corresponding PRU core usage */ 56 * split equally between the corresponding RTU and Tx_PRU cores in
57 RTU_DMEM_0_1 : org = 0x00001000 len = 0x00001000 57 * each slice */
58 RTU_DMEM_1_0 : org = 0x00003000 len = 0x00001000 58 RTU0_DMEM_0 : org = 0x00001000 len = 0x00000800
59 TX_PRU0_DMEM_0 : org = 0x00001800 len = 0x00000800
60 RTU0_DMEM_1 : org = 0x00003000 len = 0x00000800
61 TX_PRU0_DMEM_1 : org = 0x00003800 len = 0x00000800
59 62
60 PAGE 2: 63 PAGE 2:
61 /* C28 needs to be programmed to point to SHAREDMEM, default is 0 */ 64 /* C28 needs to be programmed to point to SHAREDMEM, default is 0 */
62 /* 64kB PRU Shared RAM */ 65 /* 64 KB PRU Shared RAM */
63 PRU_SHAREDMEM : org = 0x00010000 len = 0x00010000 CREGISTER=28 66 PRU_SHAREDMEM : org = 0x00010000 len = 0x00010000 CREGISTER=28
64 67
65 /* Internal Peripherals */ 68 /* Internal Peripherals */
@@ -76,7 +79,7 @@ MEMORY
76 * out as it conflicts with PRU_INTC size above. Using this requires 79 * out as it conflicts with PRU_INTC size above. Using this requires
77 * splitting up the pruIntc structure and CT_INTC variable from 80 * splitting up the pruIntc structure and CT_INTC variable from
78 * pru_intc.h */ 81 * pru_intc.h */
79 /*PRU_INTC_0x200: org = 0x00040200 len = 0x00001304 CREGISTER=6*/ 82 /*PRU_INTC_0x200: org = 0x00020200 len = 0x00001304 CREGISTER=6*/
80 PRU_UART : org = 0x00028000 len = 0x00000038 CREGISTER=7 83 PRU_UART : org = 0x00028000 len = 0x00000038 CREGISTER=7
81 PRU_IEP0_0x100 : org = 0x0002E100 len = 0x0000021C CREGISTER=8 84 PRU_IEP0_0x100 : org = 0x0002E100 len = 0x0000021C CREGISTER=8
82 MII_G_RT : org = 0x00033000 len = 0x00000C18 CREGISTER=9 85 MII_G_RT : org = 0x00033000 len = 0x00000C18 CREGISTER=9
@@ -113,17 +116,17 @@ SECTIONS {
113 .text:_c_int00* > 0x0, PAGE 0 116 .text:_c_int00* > 0x0, PAGE 0
114 117
115 .text > RTU_IMEM, PAGE 0 118 .text > RTU_IMEM, PAGE 0
116 .stack > RTU_DMEM_0_1, PAGE 1 119 .stack > RTU0_DMEM_0, PAGE 1
117 .bss > RTU_DMEM_0_1, PAGE 1 120 .bss > RTU0_DMEM_0, PAGE 1
118 .cio > RTU_DMEM_0_1, PAGE 1 121 .cio > RTU0_DMEM_0, PAGE 1
119 .data > RTU_DMEM_0_1, PAGE 1 122 .data > RTU0_DMEM_0, PAGE 1
120 .switch > RTU_DMEM_0_1, PAGE 1 123 .switch > RTU0_DMEM_0, PAGE 1
121 .sysmem > RTU_DMEM_0_1, PAGE 1 124 .sysmem > RTU0_DMEM_0, PAGE 1
122 .cinit > RTU_DMEM_0_1, PAGE 1 125 .cinit > RTU0_DMEM_0, PAGE 1
123 .rodata > RTU_DMEM_0_1, PAGE 1 126 .rodata > RTU0_DMEM_0, PAGE 1
124 .rofardata > RTU_DMEM_0_1, PAGE 1 127 .rofardata > RTU0_DMEM_0, PAGE 1
125 .farbss > RTU_DMEM_0_1, PAGE 1 128 .farbss > RTU0_DMEM_0, PAGE 1
126 .fardata > RTU_DMEM_0_1, PAGE 1 129 .fardata > RTU0_DMEM_0, PAGE 1
127 130
128 .resource_table > RTU_DMEM_0_1, PAGE 1 131 .resource_table > RTU0_DMEM_0, PAGE 1
129} 132}
diff --git a/labs/Getting_Started_Labs/linker_cmd/AM65x_RTU1.cmd b/labs/Getting_Started_Labs/linker_cmd/AM65x_RTU1.cmd
index 2385155..1db3dd7 100644
--- a/labs/Getting_Started_Labs/linker_cmd/AM65x_RTU1.cmd
+++ b/labs/Getting_Started_Labs/linker_cmd/AM65x_RTU1.cmd
@@ -4,7 +4,7 @@
4 * Example Linker command file for linking programs built with the C compiler 4 * Example Linker command file for linking programs built with the C compiler
5 * on AM65x RTU1 cores 5 * on AM65x RTU1 cores
6 * 6 *
7 * Copyright (C) 2017-2018 Texas Instruments Incorporated - http://www.ti.com/ 7 * Copyright (C) 2017-2020 Texas Instruments Incorporated - http://www.ti.com/
8 * 8 *
9 * Redistribution and use in source and binary forms, with or without 9 * Redistribution and use in source and binary forms, with or without
10 * modification, are permitted provided that the following conditions 10 * modification, are permitted provided that the following conditions
@@ -41,25 +41,28 @@
41MEMORY 41MEMORY
42{ 42{
43 PAGE 0: 43 PAGE 0:
44 /* 8kB RTU Instruction RAM */ 44 /* 8 KB RTU Instruction RAM */
45 RTU_IMEM : org = 0x00000000 len = 0x00002000 45 RTU_IMEM : org = 0x00000000 len = 0x00002000
46 46
47 PAGE 1: 47 PAGE 1:
48 /* Data RAMs */ 48 /* Data RAMs */
49 /* 8kB PRU Data RAM 0_1; use only the first page for PRU1 and reserve 49 /* 8 KB PRU Data RAM 1; use only the first 4 KB for PRU1 and reserve
50 * the second page for RTU1 */ 50 * the second 4 KB for RTU1 and Tx_PRU1 */
51 PRU_DMEM_0_1 : org = 0x00000000 len = 0x00001000 CREGISTER=24 51 PRU1_DMEM_1 : org = 0x00000000 len = 0x00001000 CREGISTER=24
52 /* 8kB PRU Data RAM 1_0; use only the first page for PRU0 and reserve 52 /* 8 KB PRU Data RAM 0; reserved completely for Slice0 cores - PRU0,
53 * the second page for RTU0 */ 53 * RTU0 and Tx_PRU0; do not use for any Slice1 cores */
54 PRU_DMEM_1_0 : org = 0x00002000 len = 0x00001000 CREGISTER=25 54 PRU1_DMEM_0 : org = 0x00002000 len = 0x00001000 CREGISTER=25
55 /* NOTE: Customized to use the second 4K of ICSS Data RAMs 0 and 1 so 55 /* NOTE: Custom split of the second 4 KB of ICSS Data RAMs 0 and 1
56 as not to conflict with corresponding PRU core usage */ 56 * split equally between the corresponding RTU and Tx_PRU cores in
57 RTU_DMEM_0_1 : org = 0x00001000 len = 0x00001000 57 * each slice */
58 RTU_DMEM_1_0 : org = 0x00003000 len = 0x00001000 58 RTU1_DMEM_1 : org = 0x00001000 len = 0x00000800
59 TX_PRU1_DMEM_1 : org = 0x00001800 len = 0x00000800
60 RTU1_DMEM_0 : org = 0x00003000 len = 0x00000800
61 TX_PRU1_DMEM_0 : org = 0x00003800 len = 0x00000800
59 62
60 PAGE 2: 63 PAGE 2:
61 /* C28 needs to be programmed to point to SHAREDMEM, default is 0 */ 64 /* C28 needs to be programmed to point to SHAREDMEM, default is 0 */
62 /* 64kB PRU Shared RAM */ 65 /* 64 KB PRU Shared RAM */
63 PRU_SHAREDMEM : org = 0x00010000 len = 0x00010000 CREGISTER=28 66 PRU_SHAREDMEM : org = 0x00010000 len = 0x00010000 CREGISTER=28
64 67
65 /* Internal Peripherals */ 68 /* Internal Peripherals */
@@ -76,7 +79,7 @@ MEMORY
76 * out as it conflicts with PRU_INTC size above. Using this requires 79 * out as it conflicts with PRU_INTC size above. Using this requires
77 * splitting up the pruIntc structure and CT_INTC variable from 80 * splitting up the pruIntc structure and CT_INTC variable from
78 * pru_intc.h */ 81 * pru_intc.h */
79 /*PRU_INTC_0x200: org = 0x00040200 len = 0x00001304 CREGISTER=6*/ 82 /*PRU_INTC_0x200: org = 0x00020200 len = 0x00001304 CREGISTER=6*/
80 PRU_UART : org = 0x00028000 len = 0x00000038 CREGISTER=7 83 PRU_UART : org = 0x00028000 len = 0x00000038 CREGISTER=7
81 PRU_IEP0_0x100 : org = 0x0002E100 len = 0x0000021C CREGISTER=8 84 PRU_IEP0_0x100 : org = 0x0002E100 len = 0x0000021C CREGISTER=8
82 MII_G_RT : org = 0x00033000 len = 0x00000C18 CREGISTER=9 85 MII_G_RT : org = 0x00033000 len = 0x00000C18 CREGISTER=9
@@ -113,17 +116,17 @@ SECTIONS {
113 .text:_c_int00* > 0x0, PAGE 0 116 .text:_c_int00* > 0x0, PAGE 0
114 117
115 .text > RTU_IMEM, PAGE 0 118 .text > RTU_IMEM, PAGE 0
116 .stack > RTU_DMEM_0_1, PAGE 1 119 .stack > RTU1_DMEM_1, PAGE 1
117 .bss > RTU_DMEM_0_1, PAGE 1 120 .bss > RTU1_DMEM_1, PAGE 1
118 .cio > RTU_DMEM_0_1, PAGE 1 121 .cio > RTU1_DMEM_1, PAGE 1
119 .data > RTU_DMEM_0_1, PAGE 1 122 .data > RTU1_DMEM_1, PAGE 1
120 .switch > RTU_DMEM_0_1, PAGE 1 123 .switch > RTU1_DMEM_1, PAGE 1
121 .sysmem > RTU_DMEM_0_1, PAGE 1 124 .sysmem > RTU1_DMEM_1, PAGE 1
122 .cinit > RTU_DMEM_0_1, PAGE 1 125 .cinit > RTU1_DMEM_1, PAGE 1
123 .rodata > RTU_DMEM_0_1, PAGE 1 126 .rodata > RTU1_DMEM_1, PAGE 1
124 .rofardata > RTU_DMEM_0_1, PAGE 1 127 .rofardata > RTU1_DMEM_1, PAGE 1
125 .farbss > RTU_DMEM_0_1, PAGE 1 128 .farbss > RTU1_DMEM_1, PAGE 1
126 .fardata > RTU_DMEM_0_1, PAGE 1 129 .fardata > RTU1_DMEM_1, PAGE 1
127 130
128 .resource_table > RTU_DMEM_0_1, PAGE 1 131 .resource_table > RTU1_DMEM_1, PAGE 1
129} 132}