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authorSuman Anna2018-07-02 13:05:23 -0500
committerSuman Anna2018-12-12 11:33:01 -0600
commit34c1815dc40a56ff674b8980f072f3fc43394e25 (patch)
treeaa57c41c9779dc7e7e9f4d8d6ab2849a603d31e0
parent082ebd87c8420c6b1f42acd750a6f3720f0b754b (diff)
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arm64: dts: ti: k3-am65-main: Add IPC sub-mailbox nodes for R5Fs
Add the sub-mailbox nodes that are used to communicate between MPU and the two R5F remote processors present in the MCU domain. The parent mailbox cluster nodes are enabled and the interrupts associated with the Mailbox Cluster User interrupt used by the sub-mailbox nodes are also added. The GIC_SPI interrupt to be used is dynamically allocated and managed by the System Firmware through the ti-sci-irqchip driver. The sub-mailbox nodes utilize the System Mailbox clusters 1 and 2. These sub-mailbox nodes are added to match the hard-coded mailbox configuration used within the TI IPC 3.x software package. The Cortex R5F processor sub-system is assumed to be running in Split mode, so a sub-mailbox node is used by each of the R5F cores. The sub-mailbox node from cluster 1 is used in case of Lockstep mode. Signed-off-by: Suman Anna <s-anna@ti.com>
-rw-r--r--arch/arm64/boot/dts/ti/k3-am65-main.dtsi16
1 files changed, 14 insertions, 2 deletions
diff --git a/arch/arm64/boot/dts/ti/k3-am65-main.dtsi b/arch/arm64/boot/dts/ti/k3-am65-main.dtsi
index 28436e55e403..88a82a139ca5 100644
--- a/arch/arm64/boot/dts/ti/k3-am65-main.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-am65-main.dtsi
@@ -304,7 +304,13 @@
304 #mbox-cells = <1>; 304 #mbox-cells = <1>;
305 ti,mbox-num-users = <4>; 305 ti,mbox-num-users = <4>;
306 ti,mbox-num-fifos = <16>; 306 ti,mbox-num-fifos = <16>;
307 status = "disabled"; 307 interrupt-parent = <&main_navss_intr>;
308 interrupts = <164 0 IRQ_TYPE_LEVEL_HIGH>;
309
310 mbox_mcu_r5f0_ipc3x: mbox-mcu-r5f0-ipc3x {
311 ti,mbox-tx = <1 0 0>;
312 ti,mbox-rx = <0 0 0>;
313 };
308 }; 314 };
309 315
310 mailbox0_cluster1: mailbox@31f81000 { 316 mailbox0_cluster1: mailbox@31f81000 {
@@ -313,7 +319,13 @@
313 #mbox-cells = <1>; 319 #mbox-cells = <1>;
314 ti,mbox-num-users = <4>; 320 ti,mbox-num-users = <4>;
315 ti,mbox-num-fifos = <16>; 321 ti,mbox-num-fifos = <16>;
316 status = "disabled"; 322 interrupt-parent = <&main_navss_intr>;
323 interrupts = <165 0 IRQ_TYPE_LEVEL_HIGH>;
324
325 mbox_mcu_r5f1_ipc3x: mbox-mcu-r5f1-ipc3x {
326 ti,mbox-tx = <1 0 0>;
327 ti,mbox-rx = <0 0 0>;
328 };
317 }; 329 };
318 330
319 mailbox0_cluster2: mailbox@31f82000 { 331 mailbox0_cluster2: mailbox@31f82000 {