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authorSuman Anna2019-03-02 21:34:59 -0600
committerSuman Anna2019-03-02 21:50:27 -0600
commit309814054352fbbaab8b8fbb283d9232ada316d0 (patch)
treec90dace3122a8450c8584cbe419da72cab01af6a
parent4e6bf3ca947b766653f1bd136102c1d34e9d0714 (diff)
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ARM: OMAP2+: Extend DRA7 IPU1 MMU pdata quirks to DSP MDMA MMUs
The C66-based DSPs on DRA7xx SoCs do not support a Powerdown-RET mode, and only supports a Powerdown-Grid OFF mode which requires a boot from reset. The HW_AUTO setting and a target power domain state of OFF implies that the DSPs are powered off as soon as they are idled by executing an IDLE instruction. The DSPs lose their context as a result and will be unable to resume operations from any wakeup event. The DSP power domains therefore need to be restricted to ON state for the duration a DSP processor is actively running. This is similar to the restriction required for DRA7 IPU1 processor (albeit because of a different reason). The IPU1 behavior is handled in commit 4e6bf3ca947b ("ARM: OMAP2+: Use separate IOMMU pdata to fix DRA7 IPU1 boot") which adds a .set_pwrdm_constraint ops to the OMAP IOMMU platform data to restrict the IPU1 power domain to ON state during the active period of the IPU1 remote processor. Extend the IPU1 iommu pdata quirks to the DRA7 MDMA MMUs as well to restrict the DSP power domains to ON state. The MDMA MMU module configuration will be the first and last steps in the boot and shutdown sequences of the DSP processors. The existing IPU1 IOMMU pdata variable has also been renamed appropriately to reflect the common usage between the IPU1 and the DSPs. NOTE: 1. The functional behavior is inconsistent between different DSPs on DRA74x, DRA72x and DRA71x SoCs and silicon revisions. DSP1 on DRA7 EVM rev.H (DRA752 ES2.0), AM57xx GP EVM (DRA752 ES2.0) and AM572x IDK (DRA752 ES2.0) boards is entering idle mode without any fix and are getting powered down and losing context, but none of the other boards (DRA72 EVM, DRA71 EVM, AM571x IDK) exhibit this behavior. The idling behavior is unchanged even after this patch is applied. DSP2 is not idled on any board. These behaviors are different from those observed on 4.14 kernel. 2. This patch is also needed to preserve the DSP contexts when proper clock-gating is achieved during inactive periods. DSP power domains on these platforms should not be hitting OFF at the moment (even with firmware images executing an IDLE instruction) because of the issue described in errata i879 ("DSP MStandby requires CD_EMU in SW_WKUP") affecting these SoCs, but the behavior is different between different DSPs and SoCs as explained in #1. The i879 errata fix in the following patch achieves the DSP clock-gating with HW_AUTO mode, and would result in a power domain sleep transition to OFF mode without any software context save mechanism for all the DSPs. Signed-off-by: Suman Anna <s-anna@ti.com>
-rw-r--r--arch/arm/mach-omap2/pdata-quirks.c8
1 files changed, 4 insertions, 4 deletions
diff --git a/arch/arm/mach-omap2/pdata-quirks.c b/arch/arm/mach-omap2/pdata-quirks.c
index f60faddd968c..9126961b5f5f 100644
--- a/arch/arm/mach-omap2/pdata-quirks.c
+++ b/arch/arm/mach-omap2/pdata-quirks.c
@@ -445,7 +445,7 @@ static void __init omap5_uevm_legacy_init(void)
445#endif 445#endif
446 446
447#ifdef CONFIG_SOC_DRA7XX 447#ifdef CONFIG_SOC_DRA7XX
448static struct iommu_platform_data dra7_ipu1_iommu_pdata = { 448static struct iommu_platform_data dra7_ipu1_dsp_iommu_pdata = {
449 .reset_name = "mmu_cache", 449 .reset_name = "mmu_cache",
450 .assert_reset = omap_device_assert_hardreset, 450 .assert_reset = omap_device_assert_hardreset,
451 .deassert_reset = omap_device_deassert_hardreset, 451 .deassert_reset = omap_device_deassert_hardreset,
@@ -612,13 +612,13 @@ static struct of_dev_auxdata omap_auxdata_lookup[] = {
612 OF_DEV_AUXDATA("ti,dra7-hsmmc", 0x480ad000, "480ad000.mmc", 612 OF_DEV_AUXDATA("ti,dra7-hsmmc", 0x480ad000, "480ad000.mmc",
613 &dra7_hsmmc_data_mmc3), 613 &dra7_hsmmc_data_mmc3),
614 OF_DEV_AUXDATA("ti,dra7-dsp-iommu", 0x40d01000, "40d01000.mmu", 614 OF_DEV_AUXDATA("ti,dra7-dsp-iommu", 0x40d01000, "40d01000.mmu",
615 &omap4_iommu_pdata), 615 &dra7_ipu1_dsp_iommu_pdata),
616 OF_DEV_AUXDATA("ti,dra7-dsp-iommu", 0x41501000, "41501000.mmu", 616 OF_DEV_AUXDATA("ti,dra7-dsp-iommu", 0x41501000, "41501000.mmu",
617 &omap4_iommu_pdata), 617 &dra7_ipu1_dsp_iommu_pdata),
618 OF_DEV_AUXDATA("ti,dra7-iommu", 0x55082000, "55082000.mmu", 618 OF_DEV_AUXDATA("ti,dra7-iommu", 0x55082000, "55082000.mmu",
619 &omap4_iommu_pdata), 619 &omap4_iommu_pdata),
620 OF_DEV_AUXDATA("ti,dra7-iommu", 0x58882000, "58882000.mmu", 620 OF_DEV_AUXDATA("ti,dra7-iommu", 0x58882000, "58882000.mmu",
621 &dra7_ipu1_iommu_pdata), 621 &dra7_ipu1_dsp_iommu_pdata),
622#endif 622#endif
623 /* Common auxdata */ 623 /* Common auxdata */
624 OF_DEV_AUXDATA("ti,sysc", 0, NULL, &ti_sysc_pdata), 624 OF_DEV_AUXDATA("ti,sysc", 0, NULL, &ti_sysc_pdata),