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authorSuman Anna2016-03-17 19:20:32 -0500
committerSuman Anna2019-03-02 21:50:02 -0600
commit4e6bf3ca947b766653f1bd136102c1d34e9d0714 (patch)
tree4e7bec943c8ef4eec81cf55c72414ae0d2e07712
parent8fdc9a162e8d5ad05077236b6e5852dda606a56e (diff)
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ARM: OMAP2+: Use separate IOMMU pdata to fix DRA7 IPU1 boot
The IPU1 MMU has been using common IOMMU pdata quirks defined and used by all IPU IOMMU devices on OMAP4 and beyond. Separate out the pdata for IPU1 MMU with the additional .set_pwrdm_constraint ops plugged in, so that the IPU1 power domain can be restricted to ON state during the boot and active period of the IPU1 remote processor. This eliminates the pre-conditions for the IPU1 boot issue as described in commit 8fdc9a162e8d ("iommu/omap: Fix boot issue on remoteprocs with AMMU/Unicache"). NOTE: 1. RET is not a valid target power domain state on DRA7 platforms, and IPU power domain is normally programmed for OFF. The IPU1 still fails to boot though, and an unclearable l3_noc error is thrown currently on 4.19 kernel without this fix. This behavior is same as on 4.14 LTS kernel but slightly different from previous 4.9 LTS kernel. 2. The fix is currently applied only to IPU1 on DRA7xx SoC, as the other affected IPU processors on OMAP4/OMAP5/DRA7 are in domains that are not entering RET. IPU2 on DRA7 is in CORE power domain which is only programmed for ON power state. The fix can be easily scaled if these domains do hit RET or OFF and loose context in the future. 3. The issue was not seen on current DRA7 platforms if any of the DSP remote processors were booted and using one of the GPTimers 5, 6, 7 or 8 on previous 4.9 LTS kernel. This was due to the errata fix for i874 implemented in commit 1cbabcb9807e ("ARM: DRA7: clockdomain: Implement timer workaround for errata i874") which keeps the IPU1 power domain from entering RET when the timers are active. But the timer workaround did not make any difference on 4.14/4.19 kernels, and an l3_noc error was seen still without this fix. Signed-off-by: Suman Anna <s-anna@ti.com>
-rw-r--r--arch/arm/mach-omap2/pdata-quirks.c20
1 files changed, 19 insertions, 1 deletions
diff --git a/arch/arm/mach-omap2/pdata-quirks.c b/arch/arm/mach-omap2/pdata-quirks.c
index 2fe736fa14a3..f60faddd968c 100644
--- a/arch/arm/mach-omap2/pdata-quirks.c
+++ b/arch/arm/mach-omap2/pdata-quirks.c
@@ -46,6 +46,17 @@ struct pdata_init {
46static struct of_dev_auxdata omap_auxdata_lookup[]; 46static struct of_dev_auxdata omap_auxdata_lookup[];
47static struct twl4030_gpio_platform_data twl_gpio_auxdata; 47static struct twl4030_gpio_platform_data twl_gpio_auxdata;
48 48
49#if IS_ENABLED(CONFIG_OMAP_IOMMU)
50int omap_iommu_set_pwrdm_constraint(struct platform_device *pdev, bool request,
51 u8 *pwrst);
52#else
53static inline int omap_iommu_set_pwrdm_constraint(struct platform_device *pdev,
54 bool request, u8 *pwrst)
55{
56 return 0;
57}
58#endif
59
49#ifdef CONFIG_MACH_NOKIA_N8X0 60#ifdef CONFIG_MACH_NOKIA_N8X0
50static void __init omap2420_n8x0_legacy_init(void) 61static void __init omap2420_n8x0_legacy_init(void)
51{ 62{
@@ -434,6 +445,13 @@ static void __init omap5_uevm_legacy_init(void)
434#endif 445#endif
435 446
436#ifdef CONFIG_SOC_DRA7XX 447#ifdef CONFIG_SOC_DRA7XX
448static struct iommu_platform_data dra7_ipu1_iommu_pdata = {
449 .reset_name = "mmu_cache",
450 .assert_reset = omap_device_assert_hardreset,
451 .deassert_reset = omap_device_deassert_hardreset,
452 .set_pwrdm_constraint = omap_iommu_set_pwrdm_constraint,
453};
454
437static struct omap_hsmmc_platform_data dra7_hsmmc_data_mmc1; 455static struct omap_hsmmc_platform_data dra7_hsmmc_data_mmc1;
438static struct omap_hsmmc_platform_data dra7_hsmmc_data_mmc2; 456static struct omap_hsmmc_platform_data dra7_hsmmc_data_mmc2;
439static struct omap_hsmmc_platform_data dra7_hsmmc_data_mmc3; 457static struct omap_hsmmc_platform_data dra7_hsmmc_data_mmc3;
@@ -600,7 +618,7 @@ static struct of_dev_auxdata omap_auxdata_lookup[] = {
600 OF_DEV_AUXDATA("ti,dra7-iommu", 0x55082000, "55082000.mmu", 618 OF_DEV_AUXDATA("ti,dra7-iommu", 0x55082000, "55082000.mmu",
601 &omap4_iommu_pdata), 619 &omap4_iommu_pdata),
602 OF_DEV_AUXDATA("ti,dra7-iommu", 0x58882000, "58882000.mmu", 620 OF_DEV_AUXDATA("ti,dra7-iommu", 0x58882000, "58882000.mmu",
603 &omap4_iommu_pdata), 621 &dra7_ipu1_iommu_pdata),
604#endif 622#endif
605 /* Common auxdata */ 623 /* Common auxdata */
606 OF_DEV_AUXDATA("ti,sysc", 0, NULL, &ti_sysc_pdata), 624 OF_DEV_AUXDATA("ti,sysc", 0, NULL, &ti_sysc_pdata),