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authorSuman Anna2019-06-28 12:03:41 -0500
committerSuman Anna2019-07-01 11:48:02 -0500
commit57c76b3f28042138bf92c203a3db576a66aab5cc (patch)
tree308ce5a1dd205c1474158004cdd3803a6c191580
parent26e32f353dbba8235ca36b6d0a4f931d241bbe17 (diff)
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irqchip/irq-pruss-intc: Use macros for operations on CMR and HMR
The PRUSS INTC configuration code is currently using hard-coded numbers directly for performing arithmatic operations on the Channel Map Registers (CMRs) and Host Interrupt Map Registers (HMRs). Introduce and replace these numbers with human readable macros. While at this, use the modulo operator instead of bitwise-and for the bit offset computation for the events and channels in CMR and HMR registers. Signed-off-by: Suman Anna <s-anna@ti.com>
-rw-r--r--drivers/irqchip/irq-pruss-intc.c31
1 files changed, 21 insertions, 10 deletions
diff --git a/drivers/irqchip/irq-pruss-intc.c b/drivers/irqchip/irq-pruss-intc.c
index b3c63ea3d3b5..2bd2498ac389 100644
--- a/drivers/irqchip/irq-pruss-intc.c
+++ b/drivers/irqchip/irq-pruss-intc.c
@@ -52,6 +52,16 @@
52#define PRU_INTC_HINLR(x) (0x1100 + (x) * 4) 52#define PRU_INTC_HINLR(x) (0x1100 + (x) * 4)
53#define PRU_INTC_HIER 0x1500 53#define PRU_INTC_HIER 0x1500
54 54
55/* CMR register bit-field macros */
56#define CMR_EVT_MAP_MASK 0xf
57#define CMR_EVT_MAP_BITS 8
58#define CMR_EVT_PER_REG 4
59
60/* HMR register bit-field macros */
61#define HMR_CH_MAP_MASK 0xf
62#define HMR_CH_MAP_BITS 8
63#define HMR_CH_PER_REG 4
64
55/* HIPIR register bit-fields */ 65/* HIPIR register bit-fields */
56#define INTC_HIPIR_NONE_HINT 0x80000000 66#define INTC_HIPIR_NONE_HINT 0x80000000
57 67
@@ -189,9 +199,9 @@ int pruss_intc_configure(struct pruss *pruss,
189 199
190 intc->config_map.sysev_to_ch[i] = ch; 200 intc->config_map.sysev_to_ch[i] = ch;
191 201
192 idx = i / 4; 202 idx = i / CMR_EVT_PER_REG;
193 val = pruss_intc_read_reg(intc, PRU_INTC_CMR(idx)); 203 val = pruss_intc_read_reg(intc, PRU_INTC_CMR(idx));
194 val |= ch << ((i & 3) * 8); 204 val |= ch << ((i % CMR_EVT_PER_REG) * CMR_EVT_MAP_BITS);
195 pruss_intc_write_reg(intc, PRU_INTC_CMR(idx), val); 205 pruss_intc_write_reg(intc, PRU_INTC_CMR(idx), val);
196 sysevt_mask |= BIT_ULL(i); 206 sysevt_mask |= BIT_ULL(i);
197 ch_mask |= BIT(ch); 207 ch_mask |= BIT(ch);
@@ -228,10 +238,10 @@ int pruss_intc_configure(struct pruss *pruss,
228 238
229 intc->config_map.ch_to_host[i] = host; 239 intc->config_map.ch_to_host[i] = host;
230 240
231 idx = i / 4; 241 idx = i / HMR_CH_PER_REG;
232 242
233 val = pruss_intc_read_reg(intc, PRU_INTC_HMR(idx)); 243 val = pruss_intc_read_reg(intc, PRU_INTC_HMR(idx));
234 val |= host << ((i & 3) * 8); 244 val |= host << ((i % HMR_CH_PER_REG) * HMR_CH_MAP_BITS);
235 pruss_intc_write_reg(intc, PRU_INTC_HMR(idx), val); 245 pruss_intc_write_reg(intc, PRU_INTC_HMR(idx), val);
236 246
237 ch_mask |= BIT(i); 247 ch_mask |= BIT(i);
@@ -427,14 +437,15 @@ static int pruss_intc_irq_set_affinity(struct irq_data *data,
427 } 437 }
428 438
429 /* find programmed channel */ 439 /* find programmed channel */
430 ch = pruss_intc_read_reg(intc, PRU_INTC_CMR(data->hwirq / 4)); 440 ch = pruss_intc_read_reg(intc,
431 ch >>= (data->hwirq % 4) * 8; 441 PRU_INTC_CMR(data->hwirq / CMR_EVT_PER_REG));
432 ch &= 0xf; 442 ch >>= (data->hwirq % CMR_EVT_PER_REG) * CMR_EVT_MAP_BITS;
443 ch &= CMR_EVT_MAP_MASK;
433 444
434 /* find programmed host interrupt */ 445 /* find programmed host interrupt */
435 host = pruss_intc_read_reg(intc, PRU_INTC_HMR(ch / 4)); 446 host = pruss_intc_read_reg(intc, PRU_INTC_HMR(ch / HMR_CH_MAP_BITS));
436 host >>= (ch % 4) * 8; 447 host >>= (ch % HMR_CH_PER_REG) * HMR_CH_MAP_BITS;
437 host &= 0xf; 448 host &= HMR_CH_MAP_MASK;
438 449
439 /* check programmed configuration for sanity */ 450 /* check programmed configuration for sanity */
440 if (ch != sch || host != shost) { 451 if (ch != sch || host != shost) {