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authorSuman Anna2015-05-15 11:00:35 -0500
committerSuman Anna2019-03-03 17:39:53 -0600
commit7a1b475ddb2267528ff2c2c719f5690bc8c5903b (patch)
tree6fd00e5f78b099f52fed8849ea33e7435e4e4283
parent03bd31a8c9c5a68cda840c1d29a4164c3351834a (diff)
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ARM: OMAP2+: Add iommu pdata-quirks for DRA7 DSP EDMA MMUs
The DSP processor subsystems in DRA7xx have two MMUs, one for the processor port and another for an EDMA port. Both these MMUs share a common reset line, and the reset management is done through the pdata quirks for the MMU associated with the processor port, so the DSP EDMA MMUs didn't need any pdata ops. The OMAP IOMMU driver now requires the device_enable/idle platform data ops on all the IOMMU devices to be able to enable/disable the clocks and maintain the reference count and the omap_hwmod state machine. So, add the iommu pdata quirks for the DSP EDMA MMUs. Signed-off-by: Suman Anna <s-anna@ti.com>
-rw-r--r--arch/arm/mach-omap2/pdata-quirks.c9
1 files changed, 9 insertions, 0 deletions
diff --git a/arch/arm/mach-omap2/pdata-quirks.c b/arch/arm/mach-omap2/pdata-quirks.c
index 4a5458722888..7a39919a92a8 100644
--- a/arch/arm/mach-omap2/pdata-quirks.c
+++ b/arch/arm/mach-omap2/pdata-quirks.c
@@ -458,6 +458,11 @@ static struct iommu_platform_data dra7_ipu1_dsp_iommu_pdata = {
458 .set_pwrdm_constraint = omap_iommu_set_pwrdm_constraint, 458 .set_pwrdm_constraint = omap_iommu_set_pwrdm_constraint,
459}; 459};
460 460
461static struct iommu_platform_data dra7_dsp_mmu_edma_pdata = {
462 .device_enable = omap_device_enable,
463 .device_idle = omap_device_idle,
464};
465
461static struct omap_hsmmc_platform_data dra7_hsmmc_data_mmc1; 466static struct omap_hsmmc_platform_data dra7_hsmmc_data_mmc1;
462static struct omap_hsmmc_platform_data dra7_hsmmc_data_mmc2; 467static struct omap_hsmmc_platform_data dra7_hsmmc_data_mmc2;
463static struct omap_hsmmc_platform_data dra7_hsmmc_data_mmc3; 468static struct omap_hsmmc_platform_data dra7_hsmmc_data_mmc3;
@@ -621,6 +626,10 @@ static struct of_dev_auxdata omap_auxdata_lookup[] = {
621 &dra7_ipu1_dsp_iommu_pdata), 626 &dra7_ipu1_dsp_iommu_pdata),
622 OF_DEV_AUXDATA("ti,dra7-dsp-iommu", 0x41501000, "41501000.mmu", 627 OF_DEV_AUXDATA("ti,dra7-dsp-iommu", 0x41501000, "41501000.mmu",
623 &dra7_ipu1_dsp_iommu_pdata), 628 &dra7_ipu1_dsp_iommu_pdata),
629 OF_DEV_AUXDATA("ti,dra7-dsp-iommu", 0x40d02000, "40d02000.mmu",
630 &dra7_dsp_mmu_edma_pdata),
631 OF_DEV_AUXDATA("ti,dra7-dsp-iommu", 0x41502000, "41502000.mmu",
632 &dra7_dsp_mmu_edma_pdata),
624 OF_DEV_AUXDATA("ti,dra7-iommu", 0x55082000, "55082000.mmu", 633 OF_DEV_AUXDATA("ti,dra7-iommu", 0x55082000, "55082000.mmu",
625 &omap4_iommu_pdata), 634 &omap4_iommu_pdata),
626 OF_DEV_AUXDATA("ti,dra7-iommu", 0x58882000, "58882000.mmu", 635 OF_DEV_AUXDATA("ti,dra7-iommu", 0x58882000, "58882000.mmu",