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authorSuman Anna2014-08-04 16:00:04 -0500
committerSuman Anna2019-03-04 10:02:37 -0600
commitcb2c446fc6ee47612e561eeab51e9323f86c77a1 (patch)
tree9b8fd203e6cd9ae653aa2c51eef7d2ac8c1238b4
parentc60571a64c09378089771e0c2040251017661049 (diff)
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ARM: dts: omap5-uevm: Add system timers to DSP and IPU
The BIOS System Tick timers have been added for the IPU and DSP remoteproc devices for the OMAP5 uEVM boards. The following timers (same as the timers on OMAP4 Panda boards) are chosen: IPU : GPT3 (SMP-mode) DSP : GPT5 IPU has two Cortex-M4 processors, and is currently expected to be running in SMP-mode, so only a single timer suffices to provide the BIOS tick timer. An additional timer should be added for the second processor in IPU if it were to be run in non-SMP mode. The timer value also needs to be unique from the ones used by other processors so that they can be run simultaneously. The timers are optional, but are mandatory to support device management features such as power management and watchdog support. The above are added to successfully boot and execute firmware images configured with the respective timers, images that use internal processor subsystem timers are not affected. The timers can be changed or removed as per the system integration needs, alongside equivalent changes on the firmware side. Signed-off-by: Suman Anna <s-anna@ti.com>
-rw-r--r--arch/arm/boot/dts/omap5-uevm.dts2
1 files changed, 2 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/omap5-uevm.dts b/arch/arm/boot/dts/omap5-uevm.dts
index cfe3dbff0b05..a800a49b1547 100644
--- a/arch/arm/boot/dts/omap5-uevm.dts
+++ b/arch/arm/boot/dts/omap5-uevm.dts
@@ -225,9 +225,11 @@
225&dsp { 225&dsp {
226 status = "okay"; 226 status = "okay";
227 memory-region = <&dsp_memory_region>; 227 memory-region = <&dsp_memory_region>;
228 timers = <&timer5>;
228}; 229};
229 230
230&ipu { 231&ipu {
231 status = "okay"; 232 status = "okay";
232 memory-region = <&ipu_memory_region>; 233 memory-region = <&ipu_memory_region>;
234 timers = <&timer3>;
233}; 235};