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authorSuman Anna2015-08-20 17:58:25 -0500
committerSuman Anna2019-03-02 21:51:03 -0600
commitd2fb19c469aa8799ba32b2aabb154703a0e69ed1 (patch)
tree8b47387bb4681c092e45d822620ee5463aab36e4
parent309814054352fbbaab8b8fbb283d9232ada316d0 (diff)
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ARM: OMAP2+: Add workaround for DRA7 DSP MStandby errata i879
Errata Title: i879: DSP MStandby requires CD_EMU in SW_WKUP Description: The DSP requires the internal emulation clock to be actively toggling in order to successfully enter a low power mode via execution of the IDLE instruction and PRCM MStandby/Idle handshake. This assumes that other prerequisites and software sequence are followed. Workaround: The emulation clock to the DSP is free-running anytime CCS is connected via JTAG debugger to the DSP subsystem or when the CD_EMU clock domain is set in SW_WKUP mode. The CD_EMU domain can be set in SW_WKUP mode via the CM_EMU_CLKSTCTRL [1:0]CLKTRCTRL field. Implementation: This patch implements this workaround by denying the HW_AUTO mode for the EMU clockdomain during the power-up of any DSP processor and re-enabling the HW_AUTO mode during the shutdown of the last DSP processor (actually done during the enabling and disabling of the respective DSP MDMA MMUs). Reference counting has to be used to manage the independent sequencing between the multiple DSP processors. This switching is done at runtime rather than a static clockdomain flags value to meet the target power domain state for the EMU power domain during suspend. Note that the DSP MStandby behavior is not consistent across all boards prior to this fix. Please see commit 45f871eec6c0 ("ARM: OMAP2+: Extend DRA7 IPU1 MMU pdata quirks to DSP MDMA MMUs") for details. Signed-off-by: Suman Anna <s-anna@ti.com>
-rw-r--r--arch/arm/mach-omap2/omap-iommu.c43
1 files changed, 40 insertions, 3 deletions
diff --git a/arch/arm/mach-omap2/omap-iommu.c b/arch/arm/mach-omap2/omap-iommu.c
index 2a9abe4f156d..65e7d6ec8b27 100644
--- a/arch/arm/mach-omap2/omap-iommu.c
+++ b/arch/arm/mach-omap2/omap-iommu.c
@@ -11,14 +11,43 @@
11 11
12#include "omap_hwmod.h" 12#include "omap_hwmod.h"
13#include "omap_device.h" 13#include "omap_device.h"
14#include "clockdomain.h"
14#include "powerdomain.h" 15#include "powerdomain.h"
15 16
17static void omap_iommu_dra7_emu_swsup_config(struct platform_device *pdev,
18 bool enable)
19{
20 static struct clockdomain *emu_clkdm;
21 static DEFINE_SPINLOCK(emu_lock);
22 static atomic_t count;
23 struct device_node *np = pdev->dev.of_node;
24
25 if (!of_device_is_compatible(np, "ti,dra7-dsp-iommu"))
26 return;
27
28 if (!emu_clkdm) {
29 emu_clkdm = clkdm_lookup("emu_clkdm");
30 if (WARN_ON_ONCE(!emu_clkdm))
31 return;
32 }
33
34 spin_lock(&emu_lock);
35
36 if (enable && (atomic_inc_return(&count) == 1))
37 clkdm_deny_idle(emu_clkdm);
38 else if (!enable && (atomic_dec_return(&count) == 0))
39 clkdm_allow_idle(emu_clkdm);
40
41 spin_unlock(&emu_lock);
42}
43
16int omap_iommu_set_pwrdm_constraint(struct platform_device *pdev, bool request, 44int omap_iommu_set_pwrdm_constraint(struct platform_device *pdev, bool request,
17 u8 *pwrst) 45 u8 *pwrst)
18{ 46{
19 struct powerdomain *pwrdm; 47 struct powerdomain *pwrdm;
20 struct omap_device *od; 48 struct omap_device *od;
21 u8 next_pwrst; 49 u8 next_pwrst;
50 int ret = 0;
22 51
23 od = to_omap_device(pdev); 52 od = to_omap_device(pdev);
24 if (!od) 53 if (!od)
@@ -31,13 +60,21 @@ int omap_iommu_set_pwrdm_constraint(struct platform_device *pdev, bool request,
31 if (!pwrdm) 60 if (!pwrdm)
32 return -EINVAL; 61 return -EINVAL;
33 62
34 if (request) 63 if (request) {
35 *pwrst = pwrdm_read_next_pwrst(pwrdm); 64 *pwrst = pwrdm_read_next_pwrst(pwrdm);
65 omap_iommu_dra7_emu_swsup_config(pdev, true);
66 }
36 67
37 if (*pwrst > PWRDM_POWER_RET) 68 if (*pwrst > PWRDM_POWER_RET)
38 return 0; 69 goto out;
39 70
40 next_pwrst = request ? PWRDM_POWER_ON : *pwrst; 71 next_pwrst = request ? PWRDM_POWER_ON : *pwrst;
41 72
42 return pwrdm_set_next_pwrst(pwrdm, next_pwrst); 73 ret = pwrdm_set_next_pwrst(pwrdm, next_pwrst);
74
75out:
76 if (!request)
77 omap_iommu_dra7_emu_swsup_config(pdev, false);
78
79 return ret;
43} 80}