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author | Suman Anna | 2016-03-16 14:46:47 -0500 |
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committer | Suman Anna | 2019-03-04 10:02:37 -0600 |
commit | e6d61d3c1aabf97e2b0ba1dc5df5754d22f635cc (patch) | |
tree | cfcb7787aac287b5012d3a01ae5e5b52e6643e18 /arch/arm | |
parent | cb2c446fc6ee47612e561eeab51e9323f86c77a1 (diff) | |
download | remoteproc-e6d61d3c1aabf97e2b0ba1dc5df5754d22f635cc.tar.gz remoteproc-e6d61d3c1aabf97e2b0ba1dc5df5754d22f635cc.tar.xz remoteproc-e6d61d3c1aabf97e2b0ba1dc5df5754d22f635cc.zip |
ARM: dts: dra7: Add common IPU and DSP nodes
The DRA7xx family of SOCs have two IPUs and upto two DSP
processor subsystems in general. The IPU processor subsystem
contains dual-core ARM Cortex-M4 processors, while the DSP
processor subsystem is based on the TI's standard TMS320C66x
DSP CorePac core. The IPUs are very similar to those on OMAP5.
Two IPUs and one DSP processor subsystems is the most common
configuration. The processor device DT nodes have been added
for these processor subsystems, with the internal memories
added through 'reg' and 'reg-names' properties. The IPUs only
have an L2 RAM, whereas the DSPs have L1P, L1D and L2 RAM
memories.
NOTE:
1. The nodes do not have any mailboxes, timers or CMA regions
assigned, they should be added in the respective board dts
files.
2. The nodes haven been disabled by default and the enabling
of these nodes is also left to the respective board dts
files.
Signed-off-by: Suman Anna <s-anna@ti.com>
Diffstat (limited to 'arch/arm')
-rw-r--r-- | arch/arm/boot/dts/dra7.dtsi | 30 |
1 files changed, 30 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/dra7.dtsi b/arch/arm/boot/dts/dra7.dtsi index d31f1560ced6..1b37091d5fde 100644 --- a/arch/arm/boot/dts/dra7.dtsi +++ b/arch/arm/boot/dts/dra7.dtsi | |||
@@ -1058,6 +1058,36 @@ | |||
1058 | ti,hwmods = "dmm"; | 1058 | ti,hwmods = "dmm"; |
1059 | }; | 1059 | }; |
1060 | 1060 | ||
1061 | ipu1: ipu@58820000 { | ||
1062 | compatible = "ti,dra7-ipu"; | ||
1063 | reg = <0x58820000 0x10000>; | ||
1064 | reg-names = "l2ram"; | ||
1065 | ti,hwmods = "ipu1"; | ||
1066 | iommus = <&mmu_ipu1>; | ||
1067 | status = "disabled"; | ||
1068 | }; | ||
1069 | |||
1070 | ipu2: ipu@55020000 { | ||
1071 | compatible = "ti,dra7-ipu"; | ||
1072 | reg = <0x55020000 0x10000>; | ||
1073 | reg-names = "l2ram"; | ||
1074 | ti,hwmods = "ipu2"; | ||
1075 | iommus = <&mmu_ipu2>; | ||
1076 | status = "disabled"; | ||
1077 | }; | ||
1078 | |||
1079 | dsp1: dsp@40800000 { | ||
1080 | compatible = "ti,dra7-dsp"; | ||
1081 | reg = <0x40800000 0x48000>, | ||
1082 | <0x40e00000 0x8000>, | ||
1083 | <0x40f00000 0x8000>; | ||
1084 | reg-names = "l2ram", "l1pram", "l1dram"; | ||
1085 | ti,hwmods = "dsp1"; | ||
1086 | syscon-bootreg = <&scm_conf 0x55c>; | ||
1087 | iommus = <&mmu0_dsp1>, <&mmu1_dsp1>; | ||
1088 | status = "disabled"; | ||
1089 | }; | ||
1090 | |||
1061 | i2c1: i2c@48070000 { | 1091 | i2c1: i2c@48070000 { |
1062 | compatible = "ti,omap4-i2c"; | 1092 | compatible = "ti,omap4-i2c"; |
1063 | reg = <0x48070000 0x100>; | 1093 | reg = <0x48070000 0x100>; |