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authorEdward Fewell2019-08-20 13:07:49 -0500
committerEdward Fewell2019-08-20 13:07:49 -0500
commit3c651fb3517b5523d97bdc817856954b237a5e5a (patch)
tree4d492ea30c46f76426bfc00cf1f7d3b6b9b21c8e
parent41d9fe9924ddbab0b61ea435ef61605467482e1e (diff)
downloadopenocd-develop.tar.gz
openocd-develop.tar.xz
openocd-develop.zip
Implement vector reset for CC3220SF targetsdevelop
-rw-r--r--openocd/tcl/target/ti_cc3220sf.cfg85
1 files changed, 84 insertions, 1 deletions
diff --git a/openocd/tcl/target/ti_cc3220sf.cfg b/openocd/tcl/target/ti_cc3220sf.cfg
index f7d9bfe..0aa6c6d 100644
--- a/openocd/tcl/target/ti_cc3220sf.cfg
+++ b/openocd/tcl/target/ti_cc3220sf.cfg
@@ -6,7 +6,90 @@
6 6
7source [find target/swj-dp.tcl] 7source [find target/swj-dp.tcl]
8source [find target/icepick.cfg] 8source [find target/icepick.cfg]
9source [find target/ti_cc32xx.cfg] 9
10if { [info exists CHIPNAME] } {
11 set _CHIPNAME $CHIPNAME
12} else {
13 set _CHIPNAME cc32xx
14}
15
16#
17# Main DAP
18#
19if { [info exists DAP_TAPID] } {
20 set _DAP_TAPID $DAP_TAPID
21} else {
22 if {[using_jtag]} {
23 set _DAP_TAPID 0x4BA00477
24 } else {
25 set _DAP_TAPID 0x2BA01477
26 }
27}
28
29if {[using_jtag]} {
30 jtag newtap $_CHIPNAME dap -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_DAP_TAPID -disable
31 jtag configure $_CHIPNAME.dap -event tap-enable "icepick_c_tapenable $_CHIPNAME.jrc 0"
32} else {
33 swj_newdap $_CHIPNAME dap -expected-id $_DAP_TAPID
34}
35
36#
37# ICEpick-C (JTAG route controller)
38#
39if { [info exists JRC_TAPID] } {
40 set _JRC_TAPID $JRC_TAPID
41} else {
42 set _JRC_TAPID 0x0B97C02F
43}
44
45if {[using_jtag]} {
46 jtag newtap $_CHIPNAME jrc -irlen 6 -ircapture 0x1 -irmask 0x3f -expected-id $_JRC_TAPID -ignore-version
47 jtag configure $_CHIPNAME.jrc -event setup "jtag tapenable $_CHIPNAME.dap"
48}
49
50set _TARGETNAME $_CHIPNAME.cpu
51target create $_TARGETNAME cortex_m -chain-position $_CHIPNAME.dap
52
53if { [info exists WORKAREASIZE] } {
54 set _WORKAREASIZE $WORKAREASIZE
55} else {
56 set _WORKAREASIZE 0x2000
57}
58
59$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0
10 60
11set _FLASHNAME $_CHIPNAME.flash 61set _FLASHNAME $_CHIPNAME.flash
12flash bank $_FLASHNAME cc3220sf 0 0 0 0 $_TARGETNAME 62flash bank $_FLASHNAME cc3220sf 0 0 0 0 $_TARGETNAME
63
64cortex_m reset_config vectreset
65
66proc ocd_process_reset_inner { MODE } {
67 # use DEMCR to enable halt on reset
68 mww 0xe000edfc 1
69
70 cc32xx.cpu invoke-event reset-assert-pre
71 cc32xx.cpu arp_reset assert 0
72 cc32xx.cpu invoke-event reset-assert-post
73 cc32xx.cpu invoke-event reset-deassert-pre
74 cc32xx.cpu invoke-event reset-deassert-post
75
76 cc32xx.cpu arp_halt
77 catch { cc32xx.cpu arp_waitstate halted 500 }
78
79 # echo [format "reset_inner: %s %s" [cc32xx.cpu curstate] [ocd_reg pc]]
80
81 # intialize MSP and PC from user reset vector at flash 0x01000800
82 mem2array boot 32 0x01000800 2
83
84 reg msp $boot(0)
85 reg psp $boot(0)
86 reg pc $boot(1)
87
88 # echo [format "c_int00: 0x%x" $boot(1)]
89
90 if { 0 == [string compare $MODE run ] } {
91 resume
92 }
93
94 cc32xx.cpu invoke-event reset-end
95}