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authorBrad Griffis2014-05-19 17:50:52 -0500
committerBrad Griffis2014-05-19 17:50:52 -0500
commitdcbb41407863f1c2ab8e9eb1e2d060b2a5e4266b (patch)
tree5717ed43020d2e8a1472133b31d4f49ed6bae409
parent703ff2587a6a8f10689dafaf7baaa3fdb06c4c28 (diff)
downloadam335x-dss-files-dcbb41407863f1c2ab8e9eb1e2d060b2a5e4266b.tar.gz
am335x-dss-files-dcbb41407863f1c2ab8e9eb1e2d060b2a5e4266b.tar.xz
am335x-dss-files-dcbb41407863f1c2ab8e9eb1e2d060b2a5e4266b.zip
Initial commit for am335x-boot.dss
-rw-r--r--.project11
-rw-r--r--am335x-boot.dss373
2 files changed, 373 insertions, 11 deletions
diff --git a/.project b/.project
deleted file mode 100644
index f531543..0000000
--- a/.project
+++ /dev/null
@@ -1,11 +0,0 @@
1<?xml version="1.0" encoding="UTF-8"?>
2<projectDescription>
3 <name>am335x-dss-scripts</name>
4 <comment></comment>
5 <projects>
6 </projects>
7 <buildSpec>
8 </buildSpec>
9 <natures>
10 </natures>
11</projectDescription>
diff --git a/am335x-boot.dss b/am335x-boot.dss
new file mode 100644
index 0000000..39b9eb4
--- /dev/null
+++ b/am335x-boot.dss
@@ -0,0 +1,373 @@
1function d2h(d) {return ("00000000" + (d).toString(16)).slice(-8);}
2
3var newline = "\n";
4
5function printRegisterValue(ds, name, addr)
6{
7 value = debugSessionDAP.memory.readWord(0,addr,false);
8 value_string = d2h(value);
9 file.write(name + " = 0x" + value_string + newline);
10 return value; // return the register value for interrogation
11}
12
13// Build a filename that includes date/time
14var today = new Date();
15var year4digit = today.getFullYear();
16var month2digit = ("0" + (today.getMonth()+1)).slice(-2);
17var day2digit = ("0" + today.getDate()).slice(-2);
18var hour2digit = ("0" + today.getHours()).slice(-2);
19var minutes2digit = ("0" + today.getMinutes()).slice(-2);
20var seconds2digit = ("0" + today.getSeconds()).slice(-2);
21var filename_date = '_' + year4digit + '-' + month2digit + '-' + day2digit + '_' + hour2digit + minutes2digit + seconds2digit;
22var userHomeFolder = System.getProperty("user.home");
23var filename = userHomeFolder + '/Desktop/' + 'am335x-boot-analysis' + filename_date + '.txt';
24
25file = new java.io.FileWriter(filename);
26
27debugSessionDAP = ds.openSession("*","CS_DAP_DebugSS");
28debugSessionDAP.target.connect();
29
30var reg_val;
31
32// CONTROL: device_id
33reg_val = printRegisterValue(debugSessionDAP, "CONTROL: device_id", 0x44E10600);
34if ( (reg_val & 0x0FFFFFFF) == 0xb94402e ) {file.write(" * AM335x family" + newline);}
35if ( (reg_val & 0xF0000000) == (0 << 28) ) {file.write(" * Silicon Revision 1.0" + newline);}
36if ( (reg_val & 0xF0000000) == (1 << 28) ) {file.write(" * Silicon Revision 2.0" + newline);}
37if ( (reg_val & 0xF0000000) == (2 << 28) ) {file.write(" * Silicon Revision 2.1" + newline);}
38
39// ROM: PRM_RSTST
40file.write(newline);
41reg_val = printRegisterValue(debugSessionDAP, "PRM_DEVICE: PRM_RSTST", 0x44E00F08);
42if (reg_val & 1<<0 ) {file.write(" * Bit 0 : GLOBAL_COLD_RST" + newline);}
43if (reg_val & 1<<1 ) {file.write(" * Bit 1 : GLOBAL_WARM_RST" + newline);}
44if (reg_val & 1<<4 ) {file.write(" * Bit 4 : WDT1_RST" + newline);}
45if (reg_val & 1<<5 ) {file.write(" * Bit 5 : EXTERNAL_WARM_RST" + newline);}
46
47// CONTROL: control_status
48file.write(newline);
49reg_val = printRegisterValue(debugSessionDAP, "CONTROL: control_status", 0x44E10040);
50boot_sequence = (reg_val & 0x1F);
51if ( (reg_val & 3<<22 ) == 0<<22 ) {file.write(" * SYSBOOT[15:14] = 00b (19.2 MHz)" + newline);}
52if ( (reg_val & 3<<22 ) == 1<<22 ) {file.write(" * SYSBOOT[15:14] = 01b (24 MHz)" + newline);}
53if ( (reg_val & 3<<22 ) == 2<<22 ) {file.write(" * SYSBOOT[15:14] = 10b (25 MHz)" + newline);}
54if ( (reg_val & 3<<22 ) == 3<<22 ) {file.write(" * SYSBOOT[15:14] = 11b (26 MHz)" + newline);}
55if ( (reg_val & 3<<20 ) != 0<<20 ) {file.write(" * SYSBOOT[13:12] have been set improperly!" + newline);}
56if ( (reg_val & 3<<18 ) == 0<<18 ) {file.write(" * SYSBOOT[11:10] = 00b No GPMC CS0 addr/data muxing" + newline);}
57if ( (reg_val & 3<<18 ) == 1<<18 ) {file.write(" * SYSBOOT[11:10] = 01b GPMC CS0 addr/addr/data muxing" + newline);}
58if ( (reg_val & 3<<18 ) == 2<<18 ) {file.write(" * SYSBOOT[11:10] = 10b GPMC CS0 addr/data muxing" + newline);}
59if ( (reg_val & 3<<18 ) == 3<<18 ) {file.write(" * SYSBOOT[11:10] = 11b ILLEGAL VALUE!" + newline);}
60if ( (reg_val & 1<<17 ) == 1<<17 ) {file.write(" * SYSBOOT[9] = 0 GPMC CS0 Ignore WAIT input" + newline);}
61if ( (reg_val & 1<<17 ) == 1<<17 ) {file.write(" * SYSBOOT[9] = 1 GPMC CS0 Use WAIT input" + newline);}
62if ( (reg_val & 1<<16 ) == 1<<16 ) {file.write(" * SYSBOOT[8] = 0 GPMC CS0 8-bit data bus" + newline);}
63if ( (reg_val & 1<<16 ) == 1<<16 ) {file.write(" * SYSBOOT[8] = 1 GPMC CS0 16-bit data bus" + newline);}
64if ( (reg_val & 7<<8 ) == 3<<8 ) {file.write(" * Device Type = General Purpose (GP)" + newline);}
65else {file.write(" * Device Type is NOT GP" + newline);}
66if ( (reg_val & 0xFF ) == 0x01 ) {file.write(" * SYSBOOT[8] = 1 GPMC CS0 16-bit data bus" + newline);}
67if ( (reg_val & 3<<6 ) == 0<<6 ) {file.write(" * SYSBOOT[7:6] = 00b MII (EMAC boot modes only)" + newline);}
68if ( (reg_val & 3<<6 ) == 1<<6 ) {file.write(" * SYSBOOT[7:6] = 01b RMII (EMAC boot modes only)" + newline);}
69if ( (reg_val & 3<<6 ) == 2<<6 ) {file.write(" * SYSBOOT[7:6] = 10b ILLEGAL VALUE!" + newline);}
70if ( (reg_val & 3<<6 ) == 3<<6 ) {file.write(" * SYSBOOT[7:6] = 11b RGMII no internal delay (EMAC boot modes only)" + newline);}
71if ( (reg_val & 1<<5 ) == 0<<5 ) {file.write(" * SYSBOOT[5] = 0 CLKOUT1 disabled" + newline);}
72if ( (reg_val & 1<<5 ) == 1<<5 ) {file.write(" * SYSBOOT[5] = 1 CLKOUT1 enabled" + newline);}
73if (boot_sequence == 0x00) {file.write(" * RESERVED BOOT SEQUENCE!" + newline);}
74if (boot_sequence == 0x01) {file.write(" * Boot Sequence : UART0 -> XIP w/WAIT (MUX2) -> MMC0 -> SPI0" + newline);}
75if (boot_sequence == 0x02) {file.write(" * Boot Sequence : UART0 -> SPI0 -> NAND -> NANDI2C" + newline);}
76if (boot_sequence == 0x03) {file.write(" * Boot Sequence : UART0 -> SPI0 -> XIP (MUX2) -> MMC0" + newline);}
77if (boot_sequence == 0x04) {file.write(" * Boot Sequence : UART0 -> XIP w/WAIT (MUX1) -> MMC0 -> NAND" + newline);}
78if (boot_sequence == 0x05) {file.write(" * Boot Sequence : UART0 -> XIP (MUX1) -> SPI0 -> NANDI2C" + newline);}
79if (boot_sequence == 0x06) {file.write(" * Boot Sequence : EMAC1 -> SPI0 -> NAND -> NANDI2C" + newline);}
80if (boot_sequence == 0x07) {file.write(" * Boot Sequence : EMAC1 -> MMC0 -> XIP w/WAIT (MUX2) -> NAND" + newline);}
81if (boot_sequence == 0x08) {file.write(" * Boot Sequence : EMAC1 -> MMC0 -> XIP (MUX2) -> NANDI2C" + newline);}
82if (boot_sequence == 0x09) {file.write(" * Boot Sequence : EMAC1 -> XIP w/WAIT (MUX1) -> NAND -> MMC0" + newline);}
83if (boot_sequence == 0x0A) {file.write(" * Boot Sequence : EMAC1 -> XIP (MUX1) -> SPI0 -> NANDI2C" + newline);}
84if (boot_sequence == 0x0B) {file.write(" * Boot Sequence : USB0 -> NAND -> SPI0 -> MMC0" + newline);}
85if (boot_sequence == 0x0C) {file.write(" * Boot Sequence : USB0 -> NAND -> XIP (MUX2) -> NANDI2C" + newline);}
86if (boot_sequence == 0x0D) {file.write(" * Boot Sequence : USB0 -> NAND -> XIP (MUX1) -> SPI0" + newline);}
87if (boot_sequence == 0x0E) {file.write(" * RESERVED BOOT SEQUENCE!" + newline);}
88if (boot_sequence == 0x0F) {file.write(" * Boot Sequence : UART0 -> EMAC1 -> Reserved -> Reserved" + newline);}
89if (boot_sequence == 0x10) {file.write(" * Boot Sequence : XIP (MUX1) -> UART0 -> EMAC1 -> MMC0 " + newline);}
90if (boot_sequence == 0x11) {file.write(" * Boot Sequence : XIP w/WAIT (MUX1) -> UART0 -> EMAC1 -> MMC0" + newline);}
91if (boot_sequence == 0x12) {file.write(" * Boot Sequence : NAND -> NANDI2C -> USB0 -> UART0" + newline);}
92if (boot_sequence == 0x13) {file.write(" * Boot Sequence : NAND -> NANDI2C -> MMC0 -> UART0" + newline);}
93if (boot_sequence == 0x14) {file.write(" * Boot Sequence : NAND -> NANDI2C -> SPI0 -> EMAC1" + newline);}
94if (boot_sequence == 0x15) {file.write(" * Boot Sequence : NANDI2C -> MMC0 -> EMAC1 -> UART0" + newline);}
95if (boot_sequence == 0x16) {file.write(" * Boot Sequence : SPI0 -> MMC0 -> UART0 -> EMAC1" + newline);}
96if (boot_sequence == 0x17) {file.write(" * Boot Sequence : MMC0 -> SPI0 -> UART0 -> USB0" + newline);}
97if (boot_sequence == 0x18) {file.write(" * Boot Sequence : SPI0 -> MMC0 -> USB0 -> UART0" + newline);}
98if (boot_sequence == 0x19) {file.write(" * Boot Sequence : SPI0 -> MMC0 -> EMAC1 -> UART0" + newline);}
99if (boot_sequence == 0x1A) {file.write(" * Boot Sequence : XIP (MUX2) -> UART0 -> SPI0 -> MMC0" + newline);}
100if (boot_sequence == 0x1B) {file.write(" * Boot Sequence : XIP w/WAIT (MUX2) -> UART0 -> SPI0 -> MMC0" + newline);}
101if (boot_sequence == 0x1C) {file.write(" * Boot Sequence : MMC1 -> MMC0 -> UART0 -> USB0" + newline);}
102if (boot_sequence == 0x1D) {file.write(" * RESERVED BOOT SEQUENCE!" + newline);}
103if (boot_sequence == 0x1E) {file.write(" * RESERVED BOOT SEQUENCE!" + newline);}
104if (boot_sequence == 0x1F) {file.write(" * Boot Sequence : Fast External Boot -> EMAC1 -> UART0 -> Reserved" + newline);}
105
106// ROM: Tracing Vector 1
107file.write(newline);
108reg_val = printRegisterValue(debugSessionDAP, "ROM: Current tracing vector, word 1", 0x4030CE40);
109if (reg_val & 1<<0 ) {file.write(" * Bit 0 : [General] Passed the public reset vector" + newline);}
110if (reg_val & 1<<1 ) {file.write(" * Bit 1 : [General] Entered main function" + newline);}
111if (reg_val & 1<<2 ) {file.write(" * Bit 2 : [General] Running after the cold reset" + newline);}
112if (reg_val & 1<<3 ) {file.write(" * Bit 3 : [Boot] Main booting routine entered" + newline);}
113if (reg_val & 1<<4 ) {file.write(" * Bit 4 : [Memory Boot] Memory booting started" + newline);}
114if (reg_val & 1<<5 ) {file.write(" * Bit 5 : [Peripheral Boot] Peripheral booting started" + newline);}
115if (reg_val & 1<<6 ) {file.write(" * Bit 6 : [Boot] Booting loop reached last device" + newline);}
116if (reg_val & 1<<7 ) {file.write(" * Bit 7 : [Boot] GP header found" + newline);}
117if (reg_val & 1<<8 ) {file.write(" * Bit 8 : [Boot] Reserved" + newline);}
118if (reg_val & 1<<9 ) {file.write(" * Bit 9 : [Boot] Reserved" + newline);}
119if (reg_val & 1<<10 ) {file.write(" * Bit 10 : [Peripheral Boot] Reserved" + newline);}
120if (reg_val & 1<<11 ) {file.write(" * Bit 11 : [Peripheral Boot] Reserved" + newline);}
121if (reg_val & 1<<12 ) {file.write(" * Bit 12 : [Peripheral Boot] Device initialized" + newline);}
122if (reg_val & 1<<13 ) {file.write(" * Bit 13 : [Peripheral Boot] ASIC ID sent" + newline);}
123if (reg_val & 1<<14 ) {file.write(" * Bit 14 : [Peripheral Boot] Image received" + newline);}
124if (reg_val & 1<<15 ) {file.write(" * Bit 15 : [Peripheral Boot] Peripheral booting failed" + newline);}
125if (reg_val & 1<<16 ) {file.write(" * Bit 16 : [Peripheral Boot] Booting Message not received (timeout)" + newline);}
126if (reg_val & 1<<17 ) {file.write(" * Bit 17 : [Peripheral Boot] Image size not received (timeout)" + newline);}
127if (reg_val & 1<<18 ) {file.write(" * Bit 18 : [Peripheral Boot] Image not received (timeout)" + newline);}
128if (reg_val & 1<<19 ) {file.write(" * Bit 19 : Reserved" + newline);}
129if (reg_val & 1<<20 ) {file.write(" * Bit 20 : [Configuration Header] CHSETTINGS found" + newline);}
130if (reg_val & 1<<21 ) {file.write(" * Bit 21 : [Configuration Header] CHSETTINGS executed" + newline);}
131if (reg_val & 1<<22 ) {file.write(" * Bit 22 : [Configuration Header] CHRAM executed" + newline);}
132if (reg_val & 1<<23 ) {file.write(" * Bit 23 : [Configuration Header] CHFLASH executed" + newline);}
133if (reg_val & 1<<24 ) {file.write(" * Bit 24 : [Configuration Header] CHMMCSD clocks executed" + newline);}
134if (reg_val & 1<<25 ) {file.write(" * Bit 25 : [Configuration Header] CHMMCSD bus width executed" + newline);}
135if (reg_val & 1<<26 ) {file.write(" * Bit 26 : Reserved" + newline);}
136if (reg_val & 1<<27 ) {file.write(" * Bit 27 : Reserved" + newline);}
137if (reg_val & 1<<28 ) {file.write(" * Bit 28 : Reserved" + newline);}
138if (reg_val & 1<<29 ) {file.write(" * Bit 29 : Reserved" + newline);}
139if (reg_val & 1<<30 ) {file.write(" * Bit 30 : Reserved" + newline);}
140if (reg_val & 1<<31 ) {file.write(" * Bit 31 : Reserved" + newline);}
141
142// ROM: Tracing Vector 2
143file.write(newline);
144reg_val = printRegisterValue(debugSessionDAP, "ROM: Current tracing vector, word 1", 0x4030CE44);
145if (reg_val & 1<<0 ) {file.write(" * Bit 0 : [Companion chip] Reserved" + newline);}
146if (reg_val & 1<<1 ) {file.write(" * Bit 1 : [Companion chip] Reserved" + newline);}
147if (reg_val & 1<<2 ) {file.write(" * Bit 2 : [Companion chip] Reserved" + newline);}
148if (reg_val & 1<<3 ) {file.write(" * Bit 3 : [Companion chip] Reserved" + newline);}
149if (reg_val & 1<<4 ) {file.write(" * Bit 4 : [USB] USB connect" + newline);}
150if (reg_val & 1<<5 ) {file.write(" * Bit 5 : [USB] USB configured state" + newline);}
151if (reg_val & 1<<6 ) {file.write(" * Bit 6 : [USB] USB VBUS valid" + newline);}
152if (reg_val & 1<<7 ) {file.write(" * Bit 7 : [USB] USB session valid" + newline);}
153if (reg_val & 1<<8 ) {file.write(" * Bit 8 : Reserved" + newline);}
154if (reg_val & 1<<9 ) {file.write(" * Bit 9 : Reserved" + newline);}
155if (reg_val & 1<<10 ) {file.write(" * Bit 10 : Reserved" + newline);}
156if (reg_val & 1<<11 ) {file.write(" * Bit 11 : Reserved" + newline);}
157if (reg_val & 1<<12 ) {file.write(" * Bit 12 : [Memory Boot] Memory booting trial 0" + newline);}
158if (reg_val & 1<<13 ) {file.write(" * Bit 13 : [Memory Boot] Memory booting trial 1" + newline);}
159if (reg_val & 1<<14 ) {file.write(" * Bit 14 : [Memory Boot] Memory booting trial 2" + newline);}
160if (reg_val & 1<<15 ) {file.write(" * Bit 15 : [Memory Boot] Memory booting trial 3" + newline);}
161if (reg_val & 1<<16 ) {file.write(" * Bit 16 : [Memory Boot] Execute GP image" + newline);}
162if (reg_val & 1<<17 ) {file.write(" * Bit 17 : [Peripheral Boot] Start authentication of peripheral boot image" + newline);}
163if (reg_val & 1<<18 ) {file.write(" * Bit 18 : [Memory & Peripheral Boot] Jumping to Initial SW" + newline);}
164if (reg_val & 1<<19 ) {file.write(" * Bit 19 : [Memory & Peripheral Boot] Reserved" + newline);}
165if (reg_val & 1<<20 ) {file.write(" * Bit 20 : [Memory & Peripheral Boot] Start image authentication" + newline);}
166if (reg_val & 1<<21 ) {file.write(" * Bit 21 : [Memory & Peripheral Boot] Image authentication failed" + newline);}
167if (reg_val & 1<<22 ) {file.write(" * Bit 22 : [Memory & Peripheral Boot] Analyzing SpeedUp" + newline);}
168if (reg_val & 1<<23 ) {file.write(" * Bit 23 : [Memory & Peripheral Boot] SpeedUp failed" + newline);}
169if (reg_val & 1<<24 ) {file.write(" * Bit 24 : [Memory & Peripheral Boot] Reserved" + newline);}
170if (reg_val & 1<<25 ) {file.write(" * Bit 25 : [Memory & Peripheral Boot] Reserved" + newline);}
171if (reg_val & 1<<26 ) {file.write(" * Bit 26 : [Memory & Peripheral Boot] Reserved" + newline);}
172if (reg_val & 1<<27 ) {file.write(" * Bit 27 : [Memory & Peripheral Boot] Reserved" + newline);}
173if (reg_val & 1<<28 ) {file.write(" * Bit 28 : [Memory & Peripheral Boot] Authentication procedure failed" + newline);}
174if (reg_val & 1<<29 ) {file.write(" * Bit 29 : Reserved" + newline);}
175if (reg_val & 1<<30 ) {file.write(" * Bit 30 : Reserved" + newline);}
176if (reg_val & 1<<31 ) {file.write(" * Bit 31 : Reserved" + newline);}
177
178
179// ROM: Tracing Vector 3
180file.write(newline);
181reg_val = printRegisterValue(debugSessionDAP, "ROM: Current tracing vector, word 1", 0x4030CE48);
182if (reg_val & 1<<0 ) {file.write(" * Bit 0 : [Memory Boot] Memory booting device NULL" + newline);}
183if (reg_val & 1<<1 ) {file.write(" * Bit 1 : [Memory Boot] Memory booting device XIP" + newline);}
184if (reg_val & 1<<2 ) {file.write(" * Bit 2 : [Memory Boot] Memory booting device XIPWAIT" + newline);}
185if (reg_val & 1<<3 ) {file.write(" * Bit 3 : [Memory Boot] Memory booting device NAND" + newline);}
186if (reg_val & 1<<4 ) {file.write(" * Bit 4 : [Memory Boot] Reserved" + newline);}
187if (reg_val & 1<<5 ) {file.write(" * Bit 5 : [Memory Boot] Memory booting device MMCSD0" + newline);}
188if (reg_val & 1<<6 ) {file.write(" * Bit 6 : Reserved" + newline);}
189if (reg_val & 1<<7 ) {file.write(" * Bit 7 : [Memory Boot] Memory booting device MMCSD1" + newline);}
190if (reg_val & 1<<8 ) {file.write(" * Bit 8 : Reserved" + newline);}
191if (reg_val & 1<<9 ) {file.write(" * Bit 9 : Reserved" + newline);}
192if (reg_val & 1<<10 ) {file.write(" * Bit 10 : [Memory Boot] Reserved" + newline);}
193if (reg_val & 1<<11 ) {file.write(" * Bit 11 : Reserved" + newline);}
194if (reg_val & 1<<12 ) {file.write(" * Bit 12 : Memory booting device SPI" + newline);}
195if (reg_val & 1<<13 ) {file.write(" * Bit 13 : Reserved" + newline);}
196if (reg_val & 1<<14 ) {file.write(" * Bit 14 : Reserved" + newline);}
197if (reg_val & 1<<15 ) {file.write(" * Bit 15 : Reserved" + newline);}
198if (reg_val & 1<<16 ) {file.write(" * Bit 16 : Peripheral booting device UART0" + newline);}
199if (reg_val & 1<<17 ) {file.write(" * Bit 17 : Reserved" + newline);}
200if (reg_val & 1<<18 ) {file.write(" * Bit 18 : [Peripheral Boot] Reserved" + newline);}
201if (reg_val & 1<<19 ) {file.write(" * Bit 19 : Reserved" + newline);}
202if (reg_val & 1<<20 ) {file.write(" * Bit 20 : [Peripheral Boot] Peripheral booting device USB" + newline);}
203if (reg_val & 1<<21 ) {file.write(" * Bit 21 : [Peripheral Boot] Reserved" + newline);}
204if (reg_val & 1<<22 ) {file.write(" * Bit 22 : [Peripheral Boot] Peripheral booting device GPGMAC0" + newline);}
205if (reg_val & 1<<23 ) {file.write(" * Bit 23 : Reserved" + newline);}
206if (reg_val & 1<<24 ) {file.write(" * Bit 24 : Peripheral booting device NULL" + newline);}
207if (reg_val & 1<<25 ) {file.write(" * Bit 25 : Reserved" + newline);}
208if (reg_val & 1<<26 ) {file.write(" * Bit 26 : Reserved" + newline);}
209if (reg_val & 1<<27 ) {file.write(" * Bit 27 : Reserved" + newline);}
210if (reg_val & 1<<28 ) {file.write(" * Bit 28 : Reserved" + newline);}
211if (reg_val & 1<<29 ) {file.write(" * Bit 29 : Reserved" + newline);}
212if (reg_val & 1<<30 ) {file.write(" * Bit 30 : Reserved" + newline);}
213if (reg_val & 1<<31 ) {file.write(" * Bit 31 : Reserved" + newline);}
214
215// ROM: Copy of PRM_RSTST
216file.write(newline);
217reg_val = printRegisterValue(debugSessionDAP, "ROM: Current copy of PRM_RSTST", 0x4030CE4C);
218if (reg_val & 1<<0 ) {file.write(" * Bit 0 : GLOBAL_COLD_RST" + newline);}
219if (reg_val & 1<<1 ) {file.write(" * Bit 1 : GLOBAL_WARM_RST" + newline);}
220if (reg_val & 1<<4 ) {file.write(" * Bit 4 : WDT1_RST" + newline);}
221if (reg_val & 1<<5 ) {file.write(" * Bit 5 : EXTERNAL_WARM_RST" + newline);}
222
223// ROM: Cold Reset Tracing Vector 1
224file.write(newline);
225reg_val = printRegisterValue(debugSessionDAP, "ROM: Cold reset tracing vector, word 1", 0x4030CE50);
226if (reg_val & 1<<0 ) {file.write(" * Bit 0 : [General] Passed the public reset vector" + newline);}
227if (reg_val & 1<<1 ) {file.write(" * Bit 1 : [General] Entered main function" + newline);}
228if (reg_val & 1<<2 ) {file.write(" * Bit 2 : [General] Running after the cold reset" + newline);}
229if (reg_val & 1<<3 ) {file.write(" * Bit 3 : [Boot] Main booting routine entered" + newline);}
230if (reg_val & 1<<4 ) {file.write(" * Bit 4 : [Memory Boot] Memory booting started" + newline);}
231if (reg_val & 1<<5 ) {file.write(" * Bit 5 : [Peripheral Boot] Peripheral booting started" + newline);}
232if (reg_val & 1<<6 ) {file.write(" * Bit 6 : [Boot] Booting loop reached last device" + newline);}
233if (reg_val & 1<<7 ) {file.write(" * Bit 7 : [Boot] GP header found" + newline);}
234if (reg_val & 1<<8 ) {file.write(" * Bit 8 : [Boot] Reserved" + newline);}
235if (reg_val & 1<<9 ) {file.write(" * Bit 9 : [Boot] Reserved" + newline);}
236if (reg_val & 1<<10 ) {file.write(" * Bit 10 : [Peripheral Boot] Reserved" + newline);}
237if (reg_val & 1<<11 ) {file.write(" * Bit 11 : [Peripheral Boot] Reserved" + newline);}
238if (reg_val & 1<<12 ) {file.write(" * Bit 12 : [Peripheral Boot] Device initialized" + newline);}
239if (reg_val & 1<<13 ) {file.write(" * Bit 13 : [Peripheral Boot] ASIC ID sent" + newline);}
240if (reg_val & 1<<14 ) {file.write(" * Bit 14 : [Peripheral Boot] Image received" + newline);}
241if (reg_val & 1<<15 ) {file.write(" * Bit 15 : [Peripheral Boot] Peripheral booting failed" + newline);}
242if (reg_val & 1<<16 ) {file.write(" * Bit 16 : [Peripheral Boot] Booting Message not received (timeout)" + newline);}
243if (reg_val & 1<<17 ) {file.write(" * Bit 17 : [Peripheral Boot] Image size not received (timeout)" + newline);}
244if (reg_val & 1<<18 ) {file.write(" * Bit 18 : [Peripheral Boot] Image not received (timeout)" + newline);}
245if (reg_val & 1<<19 ) {file.write(" * Bit 19 : Reserved" + newline);}
246if (reg_val & 1<<20 ) {file.write(" * Bit 20 : [Configuration Header] CHSETTINGS found" + newline);}
247if (reg_val & 1<<21 ) {file.write(" * Bit 21 : [Configuration Header] CHSETTINGS executed" + newline);}
248if (reg_val & 1<<22 ) {file.write(" * Bit 22 : [Configuration Header] CHRAM executed" + newline);}
249if (reg_val & 1<<23 ) {file.write(" * Bit 23 : [Configuration Header] CHFLASH executed" + newline);}
250if (reg_val & 1<<24 ) {file.write(" * Bit 24 : [Configuration Header] CHMMCSD clocks executed" + newline);}
251if (reg_val & 1<<25 ) {file.write(" * Bit 25 : [Configuration Header] CHMMCSD bus width executed" + newline);}
252if (reg_val & 1<<26 ) {file.write(" * Bit 26 : Reserved" + newline);}
253if (reg_val & 1<<27 ) {file.write(" * Bit 27 : Reserved" + newline);}
254if (reg_val & 1<<28 ) {file.write(" * Bit 28 : Reserved" + newline);}
255if (reg_val & 1<<29 ) {file.write(" * Bit 29 : Reserved" + newline);}
256if (reg_val & 1<<30 ) {file.write(" * Bit 30 : Reserved" + newline);}
257if (reg_val & 1<<31 ) {file.write(" * Bit 31 : Reserved" + newline);}
258
259// ROM: Cold Reset Tracing Vector 2
260file.write(newline);
261reg_val = printRegisterValue(debugSessionDAP, "ROM: Cold reset tracing vector, word 1", 0x4030CE54);
262if (reg_val & 1<<0 ) {file.write(" * Bit 0 : [Companion chip] Reserved" + newline);}
263if (reg_val & 1<<1 ) {file.write(" * Bit 1 : [Companion chip] Reserved" + newline);}
264if (reg_val & 1<<2 ) {file.write(" * Bit 2 : [Companion chip] Reserved" + newline);}
265if (reg_val & 1<<3 ) {file.write(" * Bit 3 : [Companion chip] Reserved" + newline);}
266if (reg_val & 1<<4 ) {file.write(" * Bit 4 : [USB] USB connect" + newline);}
267if (reg_val & 1<<5 ) {file.write(" * Bit 5 : [USB] USB configured state" + newline);}
268if (reg_val & 1<<6 ) {file.write(" * Bit 6 : [USB] USB VBUS valid" + newline);}
269if (reg_val & 1<<7 ) {file.write(" * Bit 7 : [USB] USB session valid" + newline);}
270if (reg_val & 1<<8 ) {file.write(" * Bit 8 : Reserved" + newline);}
271if (reg_val & 1<<9 ) {file.write(" * Bit 9 : Reserved" + newline);}
272if (reg_val & 1<<10 ) {file.write(" * Bit 10 : Reserved" + newline);}
273if (reg_val & 1<<11 ) {file.write(" * Bit 11 : Reserved" + newline);}
274if (reg_val & 1<<12 ) {file.write(" * Bit 12 : [Memory Boot] Memory booting trial 0" + newline);}
275if (reg_val & 1<<13 ) {file.write(" * Bit 13 : [Memory Boot] Memory booting trial 1" + newline);}
276if (reg_val & 1<<14 ) {file.write(" * Bit 14 : [Memory Boot] Memory booting trial 2" + newline);}
277if (reg_val & 1<<15 ) {file.write(" * Bit 15 : [Memory Boot] Memory booting trial 3" + newline);}
278if (reg_val & 1<<16 ) {file.write(" * Bit 16 : [Memory Boot] Execute GP image" + newline);}
279if (reg_val & 1<<17 ) {file.write(" * Bit 17 : [Peripheral Boot] Start authentication of peripheral boot image" + newline);}
280if (reg_val & 1<<18 ) {file.write(" * Bit 18 : [Memory & Peripheral Boot] Jumping to Initial SW" + newline);}
281if (reg_val & 1<<19 ) {file.write(" * Bit 19 : [Memory & Peripheral Boot] Reserved" + newline);}
282if (reg_val & 1<<20 ) {file.write(" * Bit 20 : [Memory & Peripheral Boot] Start image authentication" + newline);}
283if (reg_val & 1<<21 ) {file.write(" * Bit 21 : [Memory & Peripheral Boot] Image authentication failed" + newline);}
284if (reg_val & 1<<22 ) {file.write(" * Bit 22 : [Memory & Peripheral Boot] Analyzing SpeedUp" + newline);}
285if (reg_val & 1<<23 ) {file.write(" * Bit 23 : [Memory & Peripheral Boot] SpeedUp failed" + newline);}
286if (reg_val & 1<<24 ) {file.write(" * Bit 24 : [Memory & Peripheral Boot] Reserved" + newline);}
287if (reg_val & 1<<25 ) {file.write(" * Bit 25 : [Memory & Peripheral Boot] Reserved" + newline);}
288if (reg_val & 1<<26 ) {file.write(" * Bit 26 : [Memory & Peripheral Boot] Reserved" + newline);}
289if (reg_val & 1<<27 ) {file.write(" * Bit 27 : [Memory & Peripheral Boot] Reserved" + newline);}
290if (reg_val & 1<<28 ) {file.write(" * Bit 28 : [Memory & Peripheral Boot] Authentication procedure failed" + newline);}
291if (reg_val & 1<<29 ) {file.write(" * Bit 29 : Reserved" + newline);}
292if (reg_val & 1<<30 ) {file.write(" * Bit 30 : Reserved" + newline);}
293if (reg_val & 1<<31 ) {file.write(" * Bit 31 : Reserved" + newline);}
294
295// ROM: Cold Reset Tracing Vector 3
296file.write(newline);
297reg_val = printRegisterValue(debugSessionDAP, "ROM: Cold reset tracing vector, word 1", 0x4030CE58);
298if (reg_val & 1<<0 ) {file.write(" * Bit 0 : [Memory Boot] Memory booting device NULL" + newline);}
299if (reg_val & 1<<1 ) {file.write(" * Bit 1 : [Memory Boot] Memory booting device XIP" + newline);}
300if (reg_val & 1<<2 ) {file.write(" * Bit 2 : [Memory Boot] Memory booting device XIPWAIT" + newline);}
301if (reg_val & 1<<3 ) {file.write(" * Bit 3 : [Memory Boot] Memory booting device NAND" + newline);}
302if (reg_val & 1<<4 ) {file.write(" * Bit 4 : [Memory Boot] Reserved" + newline);}
303if (reg_val & 1<<5 ) {file.write(" * Bit 5 : [Memory Boot] Memory booting device MMCSD0" + newline);}
304if (reg_val & 1<<6 ) {file.write(" * Bit 6 : Reserved" + newline);}
305if (reg_val & 1<<7 ) {file.write(" * Bit 7 : [Memory Boot] Memory booting device MMCSD1" + newline);}
306if (reg_val & 1<<8 ) {file.write(" * Bit 8 : Reserved" + newline);}
307if (reg_val & 1<<9 ) {file.write(" * Bit 9 : Reserved" + newline);}
308if (reg_val & 1<<10 ) {file.write(" * Bit 10 : [Memory Boot] Reserved" + newline);}
309if (reg_val & 1<<11 ) {file.write(" * Bit 11 : Reserved" + newline);}
310if (reg_val & 1<<12 ) {file.write(" * Bit 12 : Memory booting device SPI" + newline);}
311if (reg_val & 1<<13 ) {file.write(" * Bit 13 : Reserved" + newline);}
312if (reg_val & 1<<14 ) {file.write(" * Bit 14 : Reserved" + newline);}
313if (reg_val & 1<<15 ) {file.write(" * Bit 15 : Reserved" + newline);}
314if (reg_val & 1<<16 ) {file.write(" * Bit 16 : Peripheral booting device UART0" + newline);}
315if (reg_val & 1<<17 ) {file.write(" * Bit 17 : Reserved" + newline);}
316if (reg_val & 1<<18 ) {file.write(" * Bit 18 : [Peripheral Boot] Reserved" + newline);}
317if (reg_val & 1<<19 ) {file.write(" * Bit 19 : Reserved" + newline);}
318if (reg_val & 1<<20 ) {file.write(" * Bit 20 : [Peripheral Boot] Peripheral booting device USB" + newline);}
319if (reg_val & 1<<21 ) {file.write(" * Bit 21 : [Peripheral Boot] Reserved" + newline);}
320if (reg_val & 1<<22 ) {file.write(" * Bit 22 : [Peripheral Boot] Peripheral booting device GPGMAC0" + newline);}
321if (reg_val & 1<<23 ) {file.write(" * Bit 23 : Reserved" + newline);}
322if (reg_val & 1<<24 ) {file.write(" * Bit 24 : Peripheral booting device NULL" + newline);}
323if (reg_val & 1<<25 ) {file.write(" * Bit 25 : Reserved" + newline);}
324if (reg_val & 1<<26 ) {file.write(" * Bit 26 : Reserved" + newline);}
325if (reg_val & 1<<27 ) {file.write(" * Bit 27 : Reserved" + newline);}
326if (reg_val & 1<<28 ) {file.write(" * Bit 28 : Reserved" + newline);}
327if (reg_val & 1<<29 ) {file.write(" * Bit 29 : Reserved" + newline);}
328if (reg_val & 1<<30 ) {file.write(" * Bit 30 : Reserved" + newline);}
329if (reg_val & 1<<31 ) {file.write(" * Bit 31 : Reserved" + newline);}
330
331
332debugSessionDAP.target.disconnect();
333
334
335debugSessionA8 = ds.openSession("*","CortxA8");
336debugSessionA8.target.connect();
337
338// Get value of ARM Program Counter
339value = debugSessionA8.memory.readRegister("PC");
340value_string = d2h(value);
341file.write(newline + "Cortex A8 Program Counter = 0x" + value_string + newline);
342
343file.write(newline);
344file.write("ROM Exception Vectors" + newline);
345file.write(" * 0x4030CE04 Undefined" + newline);
346file.write(" * 0x4030CE08 SWI" + newline);
347file.write(" * 0x4030CE0C Pre-fetch abort" + newline);
348file.write(" * 0x4030CE10 Data abort" + newline);
349file.write(" * 0x4030CE14 Unused" + newline);
350file.write(" * 0x4030CE18 IRQ" + newline);
351file.write(" * 0x4030CE1C FIQ" + newline);
352
353file.write(newline);
354file.write("ROM Dead Loops" + newline);
355file.write(" * 0x00020080 Undefined exception default handler" + newline);
356file.write(" * 0x00020084 SWI exception default handler" + newline);
357file.write(" * 0x00020088 Pre-fetch abort exception default handler" + newline);
358file.write(" * 0x0002008C Data exception default handler" + newline);
359file.write(" * 0x00020090 Unused exception default handler" + newline);
360file.write(" * 0x00020094 IRQ exception default handler" + newline);
361file.write(" * 0x00020098 FIQ exception default handler" + newline);
362file.write(" * 0x0002009C Validation test PASS" + newline);
363file.write(" * 0x000200A0 Validation test FAIL" + newline);
364file.write(" * 0x000200A4 Reserved" + newline);
365file.write(" * 0x000200A8 Image not executed or returned" + newline);
366file.write(" * 0x000200AC Reserved" + newline);
367file.write(" * 0x000200B0 Reserved" + newline);
368file.write(" * 0x000200B4 Reserved" + newline);
369file.write(" * 0x000200B8 Reserved" + newline);
370file.write(" * 0x000200BC Reserved" + newline);
371
372debugSessionA8.target.disconnect();
373file.close();