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* Samsung I2S controller

Required SoC Specific Properties:

- compatible : should be one of the following.
   - samsung,s3c6410-i2s: for 8/16/24bit stereo I2S.
   - samsung,s5pv210-i2s: for 8/16/24bit multichannel(5.1) I2S with
     secondary fifo, s/w reset control and internal mux for root clk src.
   - samsung,exynos5420-i2s: for 8/16/24bit multichannel(5.1) I2S for
     playback, sterio channel capture, secondary fifo using internal
     or external dma, s/w reset control, internal mux for root clk src
     and 7.1 channel TDM support for playback. TDM (Time division multiplexing)
     is to allow transfer of multiple channel audio data on single data line.
   - samsung,exynos7-i2s: with all the available features of exynos5 i2s,
     exynos7 I2S has 7.1 channel TDM support for capture, secondary fifo
     with only external dma and more no.of root clk sampling frequencies.
   - samsung,exynos7-i2s1: I2S1 on previous samsung platforms supports
     stereo channels. exynos7 i2s1 upgraded to 5.1 multichannel with
     slightly modified bit offsets.

- reg: physical base address of the controller and length of memory mapped
- dmas: list of DMA controller phandle and DMA request line ordered pairs.
- dma-names: identifier string for each DMA request line in the dmas property.
  These strings correspond 1:1 with the ordered pairs in dmas.
- clocks: Handle to iis clock and RCLK source clk.
- clock-names:
  i2s0 uses some base clks from CMU and some are from audio subsystem internal
  clock controller. The clock names for i2s0 should be "iis", "i2s_opclk0" and
  "i2s_opclk1" as shown in the example below.
  i2s1 and i2s2 uses clocks from CMU. The clock names for i2s1 and i2s2 should
  be "iis" and "i2s_opclk0".
  "iis" is the i2s bus clock and i2s_opclk0, i2s_opclk1 are sources of the root
  clk. i2s0 has internal mux to select the source of root clk and i2s1 and i2s2
  doesn't have any such mux.
- #clock-cells: should be 1, this property must be present if the I2S device
  is a clock provider in terms of the common clock bindings, described in
- clock-output-names: from the common clock bindings, names of the CDCLK
  I2S output clocks, suggested values are "i2s_cdclk0", "i2s_cdclk1",
  "i2s_cdclk3" for the I2S0, I2S1, I2S2 devices recpectively.

There are following clocks available at the I2S device nodes:
 CLK_I2S_CDCLK    - the CDCLK (CODECLKO) gate clock,
 CLK_I2S_RCLK_PSR - the RCLK prescaler divider clock (corresponding to the
		    IISPSR register),
 CLK_I2S_RCLK_SRC - the RCLKSRC mux clock (corresponding to RCLKSRC bit in
		    IISMOD register).

Refer to the SoC datasheet for availability of the above clocks.
The CLK_I2S_RCLK_PSR and CLK_I2S_RCLK_SRC clocks are usually only available
in the IIS Multi Audio Interface (I2S0).
Note: Old DTs may not have the #clock-cells, clock-output-names properties
and then not use the I2S node as a clock supplier.

Optional SoC Specific Properties:

- samsung,idma-addr: Internal DMA register base address of the audio
  sub system(used in secondary sound source).
- pinctrl-0: Should specify pin control groups used for this controller.
- pinctrl-names: Should contain only one value - "default".


i2s0: i2s@03830000 {
	compatible = "samsung,s5pv210-i2s";
	reg = <0x03830000 0x100>;
	dmas = <&pdma0 10
		&pdma0 9
		&pdma0 8>;
	dma-names = "tx", "rx", "tx-sec";
	clocks = <&clock_audss EXYNOS_I2S_BUS>,
		<&clock_audss EXYNOS_I2S_BUS>,
		<&clock_audss EXYNOS_SCLK_I2S>;
	clock-names = "iis", "i2s_opclk0", "i2s_opclk1";
	clock-output-names = "i2s_cdclk0";
	samsung,idma-addr = <0x03000000>;
	pinctrl-names = "default";
	pinctrl-0 = <&i2s0_bus>;