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authorPratyush Yadav2021-10-13 05:13:25 -0500
committerVignesh Raghavendra2021-10-18 06:19:39 -0500
commit4c367e58bab7d3f9c470c3778441f73546f20398 (patch)
treeef75300dc782d0bb270fdcd35b8303772953ab74
parentc0a32d420103689ec29720ad203bca425778713c (diff)
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spi: cadence-quadspi: flush posted register writes before DAC access
cqspi_read_setup() and cqspi_write_setup() program the address width as the last step in the setup. This is likely to be immediately followed by a DAC region read/write. On TI K3 SoCs the DAC region is on a different endpoint from the register region. This means that the order of the two operations is not guaranteed, and they might be reordered at the interconnect level. It is possible that the DAC read/write goes through before the address width update goes through. In this situation if the previous command used a different address width the OSPI command is sent with the wrong number of address bytes, resulting in an invalid command and undefined behavior. Read back the size register to make sure the write gets flushed before accessing the DAC region. Signed-off-by: Pratyush Yadav <p.yadav@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
-rw-r--r--drivers/spi/spi-cadence-quadspi.c2
1 files changed, 2 insertions, 0 deletions
diff --git a/drivers/spi/spi-cadence-quadspi.c b/drivers/spi/spi-cadence-quadspi.c
index 06618ac74f67..53ba8502b988 100644
--- a/drivers/spi/spi-cadence-quadspi.c
+++ b/drivers/spi/spi-cadence-quadspi.c
@@ -1265,6 +1265,7 @@ static int cqspi_read_setup(struct cqspi_flash_pdata *f_pdata,
1265 reg &= ~CQSPI_REG_SIZE_ADDRESS_MASK; 1265 reg &= ~CQSPI_REG_SIZE_ADDRESS_MASK;
1266 reg |= (op->addr.nbytes - 1); 1266 reg |= (op->addr.nbytes - 1);
1267 writel(reg, reg_base + CQSPI_REG_SIZE); 1267 writel(reg, reg_base + CQSPI_REG_SIZE);
1268 readl(reg_base + CQSPI_REG_SIZE); /* Flush posted write. */
1268 return 0; 1269 return 0;
1269} 1270}
1270 1271
@@ -1405,6 +1406,7 @@ static int cqspi_write_setup(struct cqspi_flash_pdata *f_pdata,
1405 reg &= ~CQSPI_REG_SIZE_ADDRESS_MASK; 1406 reg &= ~CQSPI_REG_SIZE_ADDRESS_MASK;
1406 reg |= (op->addr.nbytes - 1); 1407 reg |= (op->addr.nbytes - 1);
1407 writel(reg, reg_base + CQSPI_REG_SIZE); 1408 writel(reg, reg_base + CQSPI_REG_SIZE);
1409 readl(reg_base + CQSPI_REG_SIZE); /* Flush posted write. */
1408 return 0; 1410 return 0;
1409} 1411}
1410 1412