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author | LCPD Auto Merger | 2021-12-22 08:17:46 -0600 |
---|---|---|
committer | LCPD Auto Merger | 2021-12-22 08:17:46 -0600 |
commit | 892cf512e34e60123e043f88bbb80b95141ebe55 (patch) | |
tree | dc1464a85ff8f11f243a1274be68ce1da1c7463c | |
parent | a79a9c993c989cdbfd87266372790ad9e635b865 (diff) | |
parent | af8d45d947327131c662f7c9804e1b24b05336f5 (diff) | |
download | ti-linux-kernel-892cf512e34e60123e043f88bbb80b95141ebe55.tar.gz ti-linux-kernel-892cf512e34e60123e043f88bbb80b95141ebe55.tar.xz ti-linux-kernel-892cf512e34e60123e043f88bbb80b95141ebe55.zip |
Merged TI feature ti_linux_base_rt into ti-rt-linux-5.10.y
TI-Feature: ti_linux_base_rt
TI-Branch: ti-linux-5.10.y
* 'ti-linux-5.10.y' of ssh://bitbucket.itg.ti.com/lcpdpub/ti-linux-kernel:
arch: arm64: ti: Add support J721S2 Common Processor Board
arm64: dts: ti: Add initial support for J721S2 System on Module
arm64: dts: ti: Add initial support for J721S2 SoC
dt-bindings: pinctrl: k3: Introduce pinmux definitions for J721S2
dt-bindings: arm: ti: Add bindings for J721s2 SoC
dt-bindings: ti-serdes-mux: Add defines for J721S2 SoC
soc: ti: k3-socinfo: Add entry for J721S2 SoC family
drivers: dma: ti: k3-psil: Add support for J721S2
dmaengine: ti: k3-udma: Add SoC dependent data for J721S2 SoC
phy: phy-can-transceiver: Make devm_gpiod_get optional
arm64: defconfig: Increase the maximum number of 8250/16550 serial ports
ti_config_fragments: v8_baseport.cfg: Increase the number of instance of UARTs
Signed-off-by: LCPD Auto Merger <lcpd_integration@list.ti.com>
-rw-r--r-- | Documentation/devicetree/bindings/arm/ti/k3.yaml | 6 | ||||
-rw-r--r-- | arch/arm64/boot/dts/ti/Makefile | 2 | ||||
-rw-r--r-- | arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts | 421 | ||||
-rw-r--r-- | arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi | 937 | ||||
-rw-r--r-- | arch/arm64/boot/dts/ti/k3-j721s2-mcu-wakeup.dtsi | 302 | ||||
-rw-r--r-- | arch/arm64/boot/dts/ti/k3-j721s2-som-p0.dtsi | 175 | ||||
-rw-r--r-- | arch/arm64/boot/dts/ti/k3-j721s2.dtsi | 189 | ||||
-rw-r--r-- | arch/arm64/configs/defconfig | 2 | ||||
-rw-r--r-- | drivers/dma/ti/Makefile | 3 | ||||
-rw-r--r-- | drivers/dma/ti/k3-psil-j721s2.c | 167 | ||||
-rw-r--r-- | drivers/dma/ti/k3-psil-priv.h | 1 | ||||
-rw-r--r-- | drivers/dma/ti/k3-psil.c | 1 | ||||
-rw-r--r-- | drivers/dma/ti/k3-udma.c | 1 | ||||
-rw-r--r-- | drivers/phy/phy-can-transceiver.c | 4 | ||||
-rw-r--r-- | drivers/soc/ti/k3-socinfo.c | 3 | ||||
-rw-r--r-- | include/dt-bindings/mux/ti-serdes.h | 22 | ||||
-rw-r--r-- | include/dt-bindings/pinctrl/k3.h | 3 | ||||
-rw-r--r-- | ti_config_fragments/v8_baseport.cfg | 4 |
18 files changed, 2237 insertions, 6 deletions
diff --git a/Documentation/devicetree/bindings/arm/ti/k3.yaml b/Documentation/devicetree/bindings/arm/ti/k3.yaml index dfd175f52b55..bdbf98fa8f2d 100644 --- a/Documentation/devicetree/bindings/arm/ti/k3.yaml +++ b/Documentation/devicetree/bindings/arm/ti/k3.yaml | |||
@@ -42,6 +42,12 @@ properties: | |||
42 | - ti,am642-sk | 42 | - ti,am642-sk |
43 | - const: ti,am642 | 43 | - const: ti,am642 |
44 | 44 | ||
45 | - description: K3 J721s2 SoC | ||
46 | items: | ||
47 | - enum: | ||
48 | - ti,j721s2-evm | ||
49 | - const: ti,j721s2 | ||
50 | |||
45 | additionalProperties: true | 51 | additionalProperties: true |
46 | 52 | ||
47 | ... | 53 | ... |
diff --git a/arch/arm64/boot/dts/ti/Makefile b/arch/arm64/boot/dts/ti/Makefile index 4aa9a7a2dea3..64f1baf0e753 100644 --- a/arch/arm64/boot/dts/ti/Makefile +++ b/arch/arm64/boot/dts/ti/Makefile | |||
@@ -30,6 +30,8 @@ dtb-$(CONFIG_ARCH_K3) += k3-j721e-sk-rpi-cam-imx219.dtbo | |||
30 | 30 | ||
31 | dtb-$(CONFIG_ARCH_K3) += k3-j7200-common-proc-board.dtb | 31 | dtb-$(CONFIG_ARCH_K3) += k3-j7200-common-proc-board.dtb |
32 | 32 | ||
33 | dtb-$(CONFIG_ARCH_K3) += k3-j721s2-common-proc-board.dtb | ||
34 | |||
33 | dtb-$(CONFIG_ARCH_K3) += k3-am642-evm.dtb | 35 | dtb-$(CONFIG_ARCH_K3) += k3-am642-evm.dtb |
34 | dtb-$(CONFIG_ARCH_K3) += k3-am642-evm-icssg1-dualemac.dtbo | 36 | dtb-$(CONFIG_ARCH_K3) += k3-am642-evm-icssg1-dualemac.dtbo |
35 | dtb-$(CONFIG_ARCH_K3) += k3-am642-evm-icssg1-dualemac-mii.dtbo | 37 | dtb-$(CONFIG_ARCH_K3) += k3-am642-evm-icssg1-dualemac-mii.dtbo |
diff --git a/arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts b/arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts new file mode 100644 index 000000000000..a5a24f9f46c5 --- /dev/null +++ b/arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts | |||
@@ -0,0 +1,421 @@ | |||
1 | // SPDX-License-Identifier: GPL-2.0 | ||
2 | /* | ||
3 | * Copyright (C) 2021 Texas Instruments Incorporated - https://www.ti.com/ | ||
4 | * | ||
5 | * Common Processor Board: https://www.ti.com/tool/J721EXCPXEVM | ||
6 | */ | ||
7 | |||
8 | /dts-v1/; | ||
9 | |||
10 | #include "k3-j721s2-som-p0.dtsi" | ||
11 | #include <dt-bindings/net/ti-dp83867.h> | ||
12 | |||
13 | / { | ||
14 | compatible = "ti,j721s2-evm", "ti,j721s2"; | ||
15 | model = "Texas Instruments J721S2 EVM"; | ||
16 | |||
17 | chosen { | ||
18 | stdout-path = "serial10:115200n8"; | ||
19 | bootargs = "console=ttyS10,115200n8 earlycon=ns16550a,mmio32,2880000"; | ||
20 | }; | ||
21 | |||
22 | evm_12v0: fixedregulator-evm12v0 { | ||
23 | /* main supply */ | ||
24 | compatible = "regulator-fixed"; | ||
25 | regulator-name = "evm_12v0"; | ||
26 | regulator-min-microvolt = <12000000>; | ||
27 | regulator-max-microvolt = <12000000>; | ||
28 | regulator-always-on; | ||
29 | regulator-boot-on; | ||
30 | }; | ||
31 | |||
32 | vsys_3v3: fixedregulator-vsys3v3 { | ||
33 | /* Output of LM5140 */ | ||
34 | compatible = "regulator-fixed"; | ||
35 | regulator-name = "vsys_3v3"; | ||
36 | regulator-min-microvolt = <3300000>; | ||
37 | regulator-max-microvolt = <3300000>; | ||
38 | vin-supply = <&evm_12v0>; | ||
39 | regulator-always-on; | ||
40 | regulator-boot-on; | ||
41 | }; | ||
42 | |||
43 | vsys_5v0: fixedregulator-vsys5v0 { | ||
44 | /* Output of LM5140 */ | ||
45 | compatible = "regulator-fixed"; | ||
46 | regulator-name = "vsys_5v0"; | ||
47 | regulator-min-microvolt = <5000000>; | ||
48 | regulator-max-microvolt = <5000000>; | ||
49 | vin-supply = <&evm_12v0>; | ||
50 | regulator-always-on; | ||
51 | regulator-boot-on; | ||
52 | }; | ||
53 | |||
54 | vdd_mmc1: fixedregulator-sd { | ||
55 | /* Output of TPS22918 */ | ||
56 | compatible = "regulator-fixed"; | ||
57 | regulator-name = "vdd_mmc1"; | ||
58 | regulator-min-microvolt = <3300000>; | ||
59 | regulator-max-microvolt = <3300000>; | ||
60 | regulator-boot-on; | ||
61 | enable-active-high; | ||
62 | vin-supply = <&vsys_3v3>; | ||
63 | gpio = <&exp2 2 GPIO_ACTIVE_HIGH>; | ||
64 | }; | ||
65 | |||
66 | vdd_sd_dv: gpio-regulator-TLV71033 { | ||
67 | /* Output of TLV71033 */ | ||
68 | compatible = "regulator-gpio"; | ||
69 | regulator-name = "tlv71033"; | ||
70 | pinctrl-names = "default"; | ||
71 | pinctrl-0 = <&vdd_sd_dv_pins_default>; | ||
72 | regulator-min-microvolt = <1800000>; | ||
73 | regulator-max-microvolt = <3300000>; | ||
74 | regulator-boot-on; | ||
75 | vin-supply = <&vsys_5v0>; | ||
76 | gpios = <&main_gpio0 8 GPIO_ACTIVE_HIGH>; | ||
77 | states = <1800000 0x0>, | ||
78 | <3300000 0x1>; | ||
79 | }; | ||
80 | |||
81 | transceiver1: can-phy1 { | ||
82 | compatible = "ti,tcan1043"; | ||
83 | #phy-cells = <0>; | ||
84 | max-bitrate = <5000000>; | ||
85 | pinctrl-names = "default"; | ||
86 | pinctrl-0 = <&mcu_mcan0_gpio_pins_default>; | ||
87 | standby-gpios = <&wkup_gpio0 69 GPIO_ACTIVE_LOW>; | ||
88 | enable-gpios = <&wkup_gpio0 0 GPIO_ACTIVE_HIGH>; | ||
89 | }; | ||
90 | |||
91 | transceiver2: can-phy2 { | ||
92 | compatible = "ti,tcan1042"; | ||
93 | #phy-cells = <0>; | ||
94 | max-bitrate = <5000000>; | ||
95 | pinctrl-names = "default"; | ||
96 | pinctrl-0 = <&mcu_mcan1_gpio_pins_default>; | ||
97 | standby-gpios = <&wkup_gpio0 2 GPIO_ACTIVE_HIGH>; | ||
98 | }; | ||
99 | |||
100 | }; | ||
101 | |||
102 | &main_pmx0 { | ||
103 | main_uart8_pins_default: main-uart8-pins-default { | ||
104 | pinctrl-single,pins = < | ||
105 | J721S2_IOPAD(0x040, PIN_INPUT, 14) /* (AC28) MCASP0_AXR0.UART8_CTSn */ | ||
106 | J721S2_IOPAD(0x044, PIN_OUTPUT, 14) /* (Y26) MCASP0_AXR1.UART8_RTSn */ | ||
107 | J721S2_IOPAD(0x0d0, PIN_INPUT, 11) /* (AF26) SPI0_CS1.UART8_RXD */ | ||
108 | J721S2_IOPAD(0x0d4, PIN_OUTPUT, 11) /* (AH27) SPI0_CLK.UART8_TXD */ | ||
109 | >; | ||
110 | }; | ||
111 | |||
112 | main_i2c3_pins_default: main-i2c3-pins-default { | ||
113 | pinctrl-single,pins = < | ||
114 | J721S2_IOPAD(0x064, PIN_INPUT_PULLUP, 13) /* (W28) MCAN0_TX.I2C3_SCL */ | ||
115 | J721S2_IOPAD(0x060, PIN_INPUT_PULLUP, 13) /* (AC27) MCASP2_AXR1.I2C3_SDA */ | ||
116 | >; | ||
117 | }; | ||
118 | |||
119 | main_mmc1_pins_default: main-mmc1-pins-default { | ||
120 | pinctrl-single,pins = < | ||
121 | J721S2_IOPAD(0x104, PIN_INPUT, 0) /* (P23) MMC1_CLK */ | ||
122 | J721S2_IOPAD(0x108, PIN_INPUT, 0) /* (N24) MMC1_CMD */ | ||
123 | J721S2_IOPAD(0x100, PIN_INPUT, 0) /* (###) MMC1_CLKLB */ | ||
124 | J721S2_IOPAD(0x0fc, PIN_INPUT, 0) /* (M23) MMC1_DAT0 */ | ||
125 | J721S2_IOPAD(0x0f8, PIN_INPUT, 0) /* (P24) MMC1_DAT1 */ | ||
126 | J721S2_IOPAD(0x0f4, PIN_INPUT, 0) /* (R24) MMC1_DAT2 */ | ||
127 | J721S2_IOPAD(0x0f0, PIN_INPUT, 0) /* (R22) MMC1_DAT3 */ | ||
128 | J721S2_IOPAD(0x0e8, PIN_INPUT, 8) /* (AE25) TIMER_IO0.MMC1_SDCD */ | ||
129 | >; | ||
130 | }; | ||
131 | |||
132 | vdd_sd_dv_pins_default: vdd-sd-dv-pins-default { | ||
133 | pinctrl-single,pins = < | ||
134 | J721S2_IOPAD(0x020, PIN_INPUT, 7) /* (AA23) MCAN15_RX.GPIO0_8 */ | ||
135 | >; | ||
136 | }; | ||
137 | }; | ||
138 | |||
139 | &wkup_pmx0 { | ||
140 | mcu_cpsw_pins_default: mcu-cpsw-pins-default { | ||
141 | pinctrl-single,pins = < | ||
142 | J721S2_WKUP_IOPAD(0x094, PIN_INPUT, 0) /* (B22) MCU_RGMII1_RD0 */ | ||
143 | J721S2_WKUP_IOPAD(0x090, PIN_INPUT, 0) /* (B21) MCU_RGMII1_RD1 */ | ||
144 | J721S2_WKUP_IOPAD(0x08c, PIN_INPUT, 0) /* (C22) MCU_RGMII1_RD2 */ | ||
145 | J721S2_WKUP_IOPAD(0x088, PIN_INPUT, 0) /* (D23) MCU_RGMII1_RD3 */ | ||
146 | J721S2_WKUP_IOPAD(0x084, PIN_INPUT, 0) /* (D22) MCU_RGMII1_RXC */ | ||
147 | J721S2_WKUP_IOPAD(0x06c, PIN_INPUT, 0) /* (E23) MCU_RGMII1_RX_CTL */ | ||
148 | J721S2_WKUP_IOPAD(0x07c, PIN_OUTPUT, 0) /* (F23) MCU_RGMII1_TD0 */ | ||
149 | J721S2_WKUP_IOPAD(0x078, PIN_OUTPUT, 0) /* (G22) MCU_RGMII1_TD1 */ | ||
150 | J721S2_WKUP_IOPAD(0x074, PIN_OUTPUT, 0) /* (E21) MCU_RGMII1_TD2 */ | ||
151 | J721S2_WKUP_IOPAD(0x070, PIN_OUTPUT, 0) /* (E22) MCU_RGMII1_TD3 */ | ||
152 | J721S2_WKUP_IOPAD(0x080, PIN_OUTPUT, 0) /* (F21) MCU_RGMII1_TXC */ | ||
153 | J721S2_WKUP_IOPAD(0x068, PIN_OUTPUT, 0) /* (F22) MCU_RGMII1_TX_CTL */ | ||
154 | >; | ||
155 | }; | ||
156 | |||
157 | mcu_mdio_pins_default: mcu-mdio-pins-default { | ||
158 | pinctrl-single,pins = < | ||
159 | J721S2_WKUP_IOPAD(0x09c, PIN_OUTPUT, 0) /* (A21) MCU_MDIO0_MDC */ | ||
160 | J721S2_WKUP_IOPAD(0x098, PIN_INPUT, 0) /* (A22) MCU_MDIO0_MDIO */ | ||
161 | >; | ||
162 | }; | ||
163 | |||
164 | mcu_mcan0_pins_default: mcu-mcan0-pins-default { | ||
165 | pinctrl-single,pins = < | ||
166 | J721S2_WKUP_IOPAD(0x0bc, PIN_INPUT, 0) /* (E28) MCU_MCAN0_RX */ | ||
167 | J721S2_WKUP_IOPAD(0x0b8, PIN_OUTPUT, 0) /* (E27) MCU_MCAN0_TX */ | ||
168 | >; | ||
169 | }; | ||
170 | |||
171 | mcu_mcan1_pins_default: mcu-mcan1-pins-default { | ||
172 | pinctrl-single,pins = < | ||
173 | J721S2_WKUP_IOPAD(0x0d4, PIN_INPUT, 0) /* (F26) WKUP_GPIO0_5.MCU_MCAN1_RX */ | ||
174 | J721S2_WKUP_IOPAD(0x0d0, PIN_OUTPUT, 0) /* (C23) WKUP_GPIO0_4.MCU_MCAN1_TX */ | ||
175 | >; | ||
176 | }; | ||
177 | |||
178 | mcu_mcan0_gpio_pins_default: mcu-mcan0-gpio-pins-default { | ||
179 | pinctrl-single,pins = < | ||
180 | J721S2_WKUP_IOPAD(0x0c0, PIN_INPUT, 7) /* (D26) WKUP_GPIO0_0 */ | ||
181 | J721S2_WKUP_IOPAD(0x0a8, PIN_INPUT, 7) /* (B25) MCU_SPI0_D1.WKUP_GPIO0_69 */ | ||
182 | >; | ||
183 | }; | ||
184 | |||
185 | mcu_mcan1_gpio_pins_default: mcu-mcan1-gpio-pins-default { | ||
186 | pinctrl-single,pins = < | ||
187 | J721S2_WKUP_IOPAD(0x0c8, PIN_INPUT, 7) /* (C28) WKUP_GPIO0_2 */ | ||
188 | >; | ||
189 | }; | ||
190 | }; | ||
191 | |||
192 | &main_gpio2 { | ||
193 | status = "disabled"; | ||
194 | }; | ||
195 | |||
196 | &main_gpio4 { | ||
197 | status = "disabled"; | ||
198 | }; | ||
199 | |||
200 | &main_gpio6 { | ||
201 | status = "disabled"; | ||
202 | }; | ||
203 | |||
204 | &wkup_gpio1 { | ||
205 | status = "disabled"; | ||
206 | }; | ||
207 | |||
208 | &wkup_uart0 { | ||
209 | status = "reserved"; | ||
210 | }; | ||
211 | |||
212 | &main_uart0 { | ||
213 | status = "disabled"; | ||
214 | }; | ||
215 | |||
216 | &main_uart1 { | ||
217 | status = "disabled"; | ||
218 | }; | ||
219 | |||
220 | &main_uart2 { | ||
221 | status = "disabled"; | ||
222 | }; | ||
223 | |||
224 | &main_uart3 { | ||
225 | status = "disabled"; | ||
226 | }; | ||
227 | |||
228 | &main_uart4 { | ||
229 | status = "disabled"; | ||
230 | }; | ||
231 | |||
232 | &main_uart5 { | ||
233 | status = "disabled"; | ||
234 | }; | ||
235 | |||
236 | &main_uart6 { | ||
237 | status = "disabled"; | ||
238 | }; | ||
239 | |||
240 | &main_uart7 { | ||
241 | status = "disabled"; | ||
242 | }; | ||
243 | |||
244 | &main_uart8 { | ||
245 | pinctrl-names = "default"; | ||
246 | pinctrl-0 = <&main_uart8_pins_default>; | ||
247 | /* Shared with TFA on this platform */ | ||
248 | power-domains = <&k3_pds 357 TI_SCI_PD_SHARED>; | ||
249 | }; | ||
250 | |||
251 | &main_uart9 { | ||
252 | status = "disabled"; | ||
253 | }; | ||
254 | |||
255 | &main_i2c0 { | ||
256 | clock-frequency = <400000>; | ||
257 | |||
258 | exp1: gpio@20 { | ||
259 | compatible = "ti,tca6416"; | ||
260 | reg = <0x20>; | ||
261 | gpio-controller; | ||
262 | #gpio-cells = <2>; | ||
263 | gpio-line-names = "PCIE_2L_MODE_SEL", "PCIE_2L_PERSTZ", "PCIE_2L_RC_RSTZ", | ||
264 | "PCIE_2L_EP_RST_EN", "PCIE_1L_MODE_SEL", "PCIE_1L_PERSTZ", | ||
265 | "PCIE_1L_RC_RSTZ", "PCIE_1L_EP_RST_EN", "PCIE_2L_PRSNT#", | ||
266 | "PCIE_1L_PRSNT#", "CDCI1_OE1/OE4", "CDCI1_OE2/OE3", "EXP_MUX1", | ||
267 | "EXP_MUX2", "EXP_MUX3", "GESI_EXP_PHY_RSTz"; | ||
268 | }; | ||
269 | |||
270 | exp2: gpio@22 { | ||
271 | compatible = "ti,tca6424"; | ||
272 | reg = <0x22>; | ||
273 | gpio-controller; | ||
274 | #gpio-cells = <2>; | ||
275 | gpio-line-names = "APPLE_AUTH_RSTZ", "MLB_RSTZ", "GPIO_USD_PWR_EN", "USBC_PWR_EN", | ||
276 | "USBC_MODE_SEL1", "USBC_MODE_SEL0", "MCAN0_EN", "MCAN0_STB#", | ||
277 | "MUX_SPAREMUX_SPARE", "MCASP/TRACE_MUX_S0", "MCASP/TRACE_MUX_S1", | ||
278 | "MLB_MUX_SEL", "MCAN_MUX_SEL", "MCASP2/SPI3_MUX_SEL", "PCIe_CLKREQn_MUX_SEL", | ||
279 | "CDCI2_RSTZ", "ENET_EXP_PWRDN", "ENET_EXP_RESETZ", "ENET_I2CMUX_SEL", | ||
280 | "ENET_EXP_SPARE2", "M2PCIE_RTSZ", "USER_INPUT1", "USER_LED1", "USER_LED2"; | ||
281 | }; | ||
282 | }; | ||
283 | |||
284 | &main_i2c1 { | ||
285 | status = "disabled"; | ||
286 | }; | ||
287 | |||
288 | &main_i2c2 { | ||
289 | status = "disabled"; | ||
290 | }; | ||
291 | |||
292 | &main_i2c3 { | ||
293 | status = "disabled"; | ||
294 | }; | ||
295 | |||
296 | &main_i2c4 { | ||
297 | status = "disabled"; | ||
298 | }; | ||
299 | |||
300 | &main_i2c5 { | ||
301 | status = "disabled"; | ||
302 | }; | ||
303 | |||
304 | &main_i2c6 { | ||
305 | status = "disabled"; | ||
306 | }; | ||
307 | |||
308 | &main_sdhci0 { | ||
309 | /* eMMC */ | ||
310 | non-removable; | ||
311 | ti,driver-strength-ohm = <50>; | ||
312 | disable-wp; | ||
313 | }; | ||
314 | |||
315 | &main_sdhci1 { | ||
316 | /* SD card */ | ||
317 | pinctrl-0 = <&main_mmc1_pins_default>; | ||
318 | pinctrl-names = "default"; | ||
319 | disable-wp; | ||
320 | vmmc-supply = <&vdd_mmc1>; | ||
321 | vqmmc-supply = <&vdd_sd_dv>; | ||
322 | }; | ||
323 | |||
324 | &mcu_cpsw { | ||
325 | pinctrl-names = "default"; | ||
326 | pinctrl-0 = <&mcu_cpsw_pins_default &mcu_mdio_pins_default>; | ||
327 | }; | ||
328 | |||
329 | &davinci_mdio { | ||
330 | phy0: ethernet-phy@0 { | ||
331 | reg = <0>; | ||
332 | ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>; | ||
333 | ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>; | ||
334 | ti,min-output-impedance; | ||
335 | }; | ||
336 | }; | ||
337 | |||
338 | &cpsw_port1 { | ||
339 | phy-mode = "rgmii-rxid"; | ||
340 | phy-handle = <&phy0>; | ||
341 | }; | ||
342 | |||
343 | &mcu_mcan0 { | ||
344 | pinctrl-names = "default"; | ||
345 | pinctrl-0 = <&mcu_mcan0_pins_default>; | ||
346 | phys = <&transceiver1>; | ||
347 | }; | ||
348 | |||
349 | &mcu_mcan1 { | ||
350 | pinctrl-names = "default"; | ||
351 | pinctrl-0 = <&mcu_mcan1_pins_default>; | ||
352 | phys = <&transceiver2>; | ||
353 | }; | ||
354 | |||
355 | &main_mcan0 { | ||
356 | status = "disabled"; | ||
357 | }; | ||
358 | |||
359 | &main_mcan1 { | ||
360 | status = "disabled"; | ||
361 | }; | ||
362 | |||
363 | &main_mcan2 { | ||
364 | status = "disabled"; | ||
365 | }; | ||
366 | |||
367 | &main_mcan3 { | ||
368 | status = "disabled"; | ||
369 | }; | ||
370 | |||
371 | &main_mcan4 { | ||
372 | status = "disabled"; | ||
373 | }; | ||
374 | |||
375 | &main_mcan5 { | ||
376 | status = "disabled"; | ||
377 | }; | ||
378 | |||
379 | &main_mcan6 { | ||
380 | status = "disabled"; | ||
381 | }; | ||
382 | |||
383 | &main_mcan7 { | ||
384 | status = "disabled"; | ||
385 | }; | ||
386 | |||
387 | &main_mcan8 { | ||
388 | status = "disabled"; | ||
389 | }; | ||
390 | |||
391 | &main_mcan9 { | ||
392 | status = "disabled"; | ||
393 | }; | ||
394 | |||
395 | &main_mcan10 { | ||
396 | status = "disabled"; | ||
397 | }; | ||
398 | |||
399 | &main_mcan11 { | ||
400 | status = "disabled"; | ||
401 | }; | ||
402 | |||
403 | &main_mcan12 { | ||
404 | status = "disabled"; | ||
405 | }; | ||
406 | |||
407 | &main_mcan13 { | ||
408 | status = "disabled"; | ||
409 | }; | ||
410 | |||
411 | &main_mcan14 { | ||
412 | status = "disabled"; | ||
413 | }; | ||
414 | |||
415 | &main_mcan15 { | ||
416 | status = "disabled"; | ||
417 | }; | ||
418 | |||
419 | &main_mcan17 { | ||
420 | status = "disabled"; | ||
421 | }; | ||
diff --git a/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi b/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi new file mode 100644 index 000000000000..b04db1d3ab61 --- /dev/null +++ b/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi | |||
@@ -0,0 +1,937 @@ | |||
1 | // SPDX-License-Identifier: GPL-2.0 | ||
2 | /* | ||
3 | * Device Tree Source for J721S2 SoC Family Main Domain peripherals | ||
4 | * | ||
5 | * Copyright (C) 2021 Texas Instruments Incorporated - https://www.ti.com/ | ||
6 | */ | ||
7 | |||
8 | &cbass_main { | ||
9 | msmc_ram: sram@70000000 { | ||
10 | compatible = "mmio-sram"; | ||
11 | reg = <0x0 0x70000000 0x0 0x400000>; | ||
12 | #address-cells = <1>; | ||
13 | #size-cells = <1>; | ||
14 | ranges = <0x0 0x0 0x70000000 0x400000>; | ||
15 | |||
16 | atf-sram@0 { | ||
17 | reg = <0x0 0x20000>; | ||
18 | }; | ||
19 | |||
20 | tifs-sram@1f0000 { | ||
21 | reg = <0x1f0000 0x10000>; | ||
22 | }; | ||
23 | |||
24 | l3cache-sram@200000 { | ||
25 | reg = <0x200000 0x200000>; | ||
26 | }; | ||
27 | }; | ||
28 | |||
29 | gic500: interrupt-controller@1800000 { | ||
30 | compatible = "arm,gic-v3"; | ||
31 | #address-cells = <2>; | ||
32 | #size-cells = <2>; | ||
33 | ranges; | ||
34 | #interrupt-cells = <3>; | ||
35 | interrupt-controller; | ||
36 | reg = <0x00 0x01800000 0x00 0x200000>, /* GICD */ | ||
37 | <0x00 0x01900000 0x00 0x100000>; /* GICR */ | ||
38 | |||
39 | /* vcpumntirq: virtual CPU interface maintenance interrupt */ | ||
40 | interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; | ||
41 | |||
42 | gic_its: msi-controller@1820000 { | ||
43 | compatible = "arm,gic-v3-its"; | ||
44 | reg = <0x00 0x01820000 0x00 0x10000>; | ||
45 | socionext,synquacer-pre-its = <0x1000000 0x400000>; | ||
46 | msi-controller; | ||
47 | #msi-cells = <1>; | ||
48 | }; | ||
49 | }; | ||
50 | |||
51 | main_gpio_intr: interrupt-controller@a00000 { | ||
52 | compatible = "ti,sci-intr"; | ||
53 | reg = <0x00 0x00a00000 0x00 0x800>; | ||
54 | ti,intr-trigger-type = <1>; | ||
55 | interrupt-controller; | ||
56 | interrupt-parent = <&gic500>; | ||
57 | #interrupt-cells = <1>; | ||
58 | ti,sci = <&sms>; | ||
59 | ti,sci-dev-id = <148>; | ||
60 | ti,interrupt-ranges = <8 360 56>; | ||
61 | }; | ||
62 | |||
63 | main_pmx0: pinctrl@11c000 { | ||
64 | compatible = "pinctrl-single"; | ||
65 | /* Proxy 0 addressing */ | ||
66 | reg = <0x0 0x11c000 0x0 0x120>; | ||
67 | #pinctrl-cells = <1>; | ||
68 | pinctrl-single,register-width = <32>; | ||
69 | pinctrl-single,function-mask = <0xffffffff>; | ||
70 | }; | ||
71 | |||
72 | main_uart0: serial@2800000 { | ||
73 | compatible = "ti,j721e-uart", "ti,am654-uart"; | ||
74 | reg = <0x00 0x02800000 0x00 0x200>; | ||
75 | interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>; | ||
76 | current-speed = <115200>; | ||
77 | clocks = <&k3_clks 146 3>; | ||
78 | clock-names = "fclk"; | ||
79 | power-domains = <&k3_pds 146 TI_SCI_PD_EXCLUSIVE>; | ||
80 | }; | ||
81 | |||
82 | main_uart1: serial@2810000 { | ||
83 | compatible = "ti,j721e-uart", "ti,am654-uart"; | ||
84 | reg = <0x00 0x02810000 0x00 0x200>; | ||
85 | interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>; | ||
86 | current-speed = <115200>; | ||
87 | clocks = <&k3_clks 350 3>; | ||
88 | clock-names = "fclk"; | ||
89 | power-domains = <&k3_pds 350 TI_SCI_PD_EXCLUSIVE>; | ||
90 | }; | ||
91 | |||
92 | main_uart2: serial@2820000 { | ||
93 | compatible = "ti,j721e-uart", "ti,am654-uart"; | ||
94 | reg = <0x00 0x02820000 0x00 0x200>; | ||
95 | interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>; | ||
96 | current-speed = <115200>; | ||
97 | clocks = <&k3_clks 351 3>; | ||
98 | clock-names = "fclk"; | ||
99 | power-domains = <&k3_pds 351 TI_SCI_PD_EXCLUSIVE>; | ||
100 | }; | ||
101 | |||
102 | main_uart3: serial@2830000 { | ||
103 | compatible = "ti,j721e-uart", "ti,am654-uart"; | ||
104 | reg = <0x00 0x02830000 0x00 0x200>; | ||
105 | interrupts = <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>; | ||
106 | current-speed = <115200>; | ||
107 | clocks = <&k3_clks 352 3>; | ||
108 | clock-names = "fclk"; | ||
109 | power-domains = <&k3_pds 352 TI_SCI_PD_EXCLUSIVE>; | ||
110 | }; | ||
111 | |||
112 | main_uart4: serial@2840000 { | ||
113 | compatible = "ti,j721e-uart", "ti,am654-uart"; | ||
114 | reg = <0x00 0x02840000 0x00 0x200>; | ||
115 | interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>; | ||
116 | current-speed = <115200>; | ||
117 | clocks = <&k3_clks 353 3>; | ||
118 | clock-names = "fclk"; | ||
119 | power-domains = <&k3_pds 353 TI_SCI_PD_EXCLUSIVE>; | ||
120 | }; | ||
121 | |||
122 | main_uart5: serial@2850000 { | ||
123 | compatible = "ti,j721e-uart", "ti,am654-uart"; | ||
124 | reg = <0x00 0x02850000 0x00 0x200>; | ||
125 | interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>; | ||
126 | current-speed = <115200>; | ||
127 | clocks = <&k3_clks 354 3>; | ||
128 | clock-names = "fclk"; | ||
129 | power-domains = <&k3_pds 354 TI_SCI_PD_EXCLUSIVE>; | ||
130 | }; | ||
131 | |||
132 | main_uart6: serial@2860000 { | ||
133 | compatible = "ti,j721e-uart", "ti,am654-uart"; | ||
134 | reg = <0x00 0x02860000 0x00 0x200>; | ||
135 | interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>; | ||
136 | current-speed = <115200>; | ||
137 | clocks = <&k3_clks 355 3>; | ||
138 | clock-names = "fclk"; | ||
139 | power-domains = <&k3_pds 355 TI_SCI_PD_EXCLUSIVE>; | ||
140 | }; | ||
141 | |||
142 | main_uart7: serial@2870000 { | ||
143 | compatible = "ti,j721e-uart", "ti,am654-uart"; | ||
144 | reg = <0x00 0x02870000 0x00 0x200>; | ||
145 | interrupts = <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>; | ||
146 | current-speed = <115200>; | ||
147 | clocks = <&k3_clks 356 3>; | ||
148 | clock-names = "fclk"; | ||
149 | power-domains = <&k3_pds 356 TI_SCI_PD_EXCLUSIVE>; | ||
150 | }; | ||
151 | |||
152 | main_uart8: serial@2880000 { | ||
153 | compatible = "ti,j721e-uart", "ti,am654-uart"; | ||
154 | reg = <0x00 0x02880000 0x00 0x200>; | ||
155 | interrupts = <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>; | ||
156 | current-speed = <115200>; | ||
157 | clocks = <&k3_clks 357 3>; | ||
158 | clock-names = "fclk"; | ||
159 | power-domains = <&k3_pds 357 TI_SCI_PD_EXCLUSIVE>; | ||
160 | }; | ||
161 | |||
162 | main_uart9: serial@2890000 { | ||
163 | compatible = "ti,j721e-uart", "ti,am654-uart"; | ||
164 | reg = <0x00 0x02890000 0x00 0x200>; | ||
165 | interrupts = <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>; | ||
166 | current-speed = <115200>; | ||
167 | clocks = <&k3_clks 358 3>; | ||
168 | clock-names = "fclk"; | ||
169 | power-domains = <&k3_pds 358 TI_SCI_PD_EXCLUSIVE>; | ||
170 | }; | ||
171 | |||
172 | main_gpio0: gpio@600000 { | ||
173 | compatible = "ti,j721e-gpio", "ti,keystone-gpio"; | ||
174 | reg = <0x00 0x00600000 0x00 0x100>; | ||
175 | gpio-controller; | ||
176 | #gpio-cells = <2>; | ||
177 | interrupt-parent = <&main_gpio_intr>; | ||
178 | interrupts = <145>, <146>, <147>, <148>, <149>; | ||
179 | interrupt-controller; | ||
180 | #interrupt-cells = <2>; | ||
181 | ti,ngpio = <66>; | ||
182 | ti,davinci-gpio-unbanked = <0>; | ||
183 | power-domains = <&k3_pds 111 TI_SCI_PD_EXCLUSIVE>; | ||
184 | clocks = <&k3_clks 111 0>; | ||
185 | clock-names = "gpio"; | ||
186 | }; | ||
187 | |||
188 | main_gpio2: gpio@610000 { | ||
189 | compatible = "ti,j721e-gpio", "ti,keystone-gpio"; | ||
190 | reg = <0x00 0x00610000 0x00 0x100>; | ||
191 | gpio-controller; | ||
192 | #gpio-cells = <2>; | ||
193 | interrupt-parent = <&main_gpio_intr>; | ||
194 | interrupts = <154>, <155>, <156>, <157>, <158>; | ||
195 | interrupt-controller; | ||
196 | #interrupt-cells = <2>; | ||
197 | ti,ngpio = <66>; | ||
198 | ti,davinci-gpio-unbanked = <0>; | ||
199 | power-domains = <&k3_pds 112 TI_SCI_PD_EXCLUSIVE>; | ||
200 | clocks = <&k3_clks 112 0>; | ||
201 | clock-names = "gpio"; | ||
202 | }; | ||
203 | |||
204 | main_gpio4: gpio@620000 { | ||
205 | compatible = "ti,j721e-gpio", "ti,keystone-gpio"; | ||
206 | reg = <0x00 0x00620000 0x00 0x100>; | ||
207 | gpio-controller; | ||
208 | #gpio-cells = <2>; | ||
209 | interrupt-parent = <&main_gpio_intr>; | ||
210 | interrupts = <163>, <164>, <165>, <166>, <167>; | ||
211 | interrupt-controller; | ||
212 | #interrupt-cells = <2>; | ||
213 | ti,ngpio = <66>; | ||
214 | ti,davinci-gpio-unbanked = <0>; | ||
215 | power-domains = <&k3_pds 113 TI_SCI_PD_EXCLUSIVE>; | ||
216 | clocks = <&k3_clks 113 0>; | ||
217 | clock-names = "gpio"; | ||
218 | }; | ||
219 | |||
220 | main_gpio6: gpio@630000 { | ||
221 | compatible = "ti,j721e-gpio", "ti,keystone-gpio"; | ||
222 | reg = <0x00 0x00630000 0x00 0x100>; | ||
223 | gpio-controller; | ||
224 | #gpio-cells = <2>; | ||
225 | interrupt-parent = <&main_gpio_intr>; | ||
226 | interrupts = <172>, <173>, <174>, <175>, <176>; | ||
227 | interrupt-controller; | ||
228 | #interrupt-cells = <2>; | ||
229 | ti,ngpio = <66>; | ||
230 | ti,davinci-gpio-unbanked = <0>; | ||
231 | power-domains = <&k3_pds 114 TI_SCI_PD_EXCLUSIVE>; | ||
232 | clocks = <&k3_clks 114 0>; | ||
233 | clock-names = "gpio"; | ||
234 | }; | ||
235 | |||
236 | main_i2c0: i2c@2000000 { | ||
237 | compatible = "ti,j721e-i2c", "ti,omap4-i2c"; | ||
238 | reg = <0x00 0x02000000 0x00 0x100>; | ||
239 | interrupts = <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>; | ||
240 | #address-cells = <1>; | ||
241 | #size-cells = <0>; | ||
242 | clocks = <&k3_clks 214 1>; | ||
243 | clock-names = "fck"; | ||
244 | power-domains = <&k3_pds 214 TI_SCI_PD_EXCLUSIVE>; | ||
245 | }; | ||
246 | |||
247 | main_i2c1: i2c@2010000 { | ||
248 | compatible = "ti,j721e-i2c", "ti,omap4-i2c"; | ||
249 | reg = <0x00 0x02010000 0x00 0x100>; | ||
250 | interrupts = <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>; | ||
251 | #address-cells = <1>; | ||
252 | #size-cells = <0>; | ||
253 | clocks = <&k3_clks 215 1>; | ||
254 | clock-names = "fck"; | ||
255 | power-domains = <&k3_pds 215 TI_SCI_PD_EXCLUSIVE>; | ||
256 | }; | ||
257 | |||
258 | main_i2c2: i2c@2020000 { | ||
259 | compatible = "ti,j721e-i2c", "ti,omap4-i2c"; | ||
260 | reg = <0x00 0x02020000 0x00 0x100>; | ||
261 | interrupts = <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>; | ||
262 | #address-cells = <1>; | ||
263 | #size-cells = <0>; | ||
264 | clocks = <&k3_clks 216 1>; | ||
265 | clock-names = "fck"; | ||
266 | power-domains = <&k3_pds 216 TI_SCI_PD_EXCLUSIVE>; | ||
267 | }; | ||
268 | |||
269 | main_i2c3: i2c@2030000 { | ||
270 | compatible = "ti,j721e-i2c", "ti,omap4-i2c"; | ||
271 | reg = <0x00 0x02030000 0x00 0x100>; | ||
272 | interrupts = <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>; | ||
273 | #address-cells = <1>; | ||
274 | #size-cells = <0>; | ||
275 | clocks = <&k3_clks 217 1>; | ||
276 | clock-names = "fck"; | ||
277 | power-domains = <&k3_pds 217 TI_SCI_PD_EXCLUSIVE>; | ||
278 | }; | ||
279 | |||
280 | main_i2c4: i2c@2040000 { | ||
281 | compatible = "ti,j721e-i2c", "ti,omap4-i2c"; | ||
282 | reg = <0x00 0x02040000 0x00 0x100>; | ||
283 | interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>; | ||
284 | #address-cells = <1>; | ||
285 | #size-cells = <0>; | ||
286 | clocks = <&k3_clks 218 1>; | ||
287 | clock-names = "fck"; | ||
288 | power-domains = <&k3_pds 218 TI_SCI_PD_EXCLUSIVE>; | ||
289 | }; | ||
290 | |||
291 | main_i2c5: i2c@2050000 { | ||
292 | compatible = "ti,j721e-i2c", "ti,omap4-i2c"; | ||
293 | reg = <0x00 0x02050000 0x00 0x100>; | ||
294 | interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>; | ||
295 | #address-cells = <1>; | ||
296 | #size-cells = <0>; | ||
297 | clocks = <&k3_clks 219 1>; | ||
298 | clock-names = "fck"; | ||
299 | power-domains = <&k3_pds 219 TI_SCI_PD_EXCLUSIVE>; | ||
300 | }; | ||
301 | |||
302 | main_i2c6: i2c@2060000 { | ||
303 | compatible = "ti,j721e-i2c", "ti,omap4-i2c"; | ||
304 | reg = <0x00 0x02060000 0x00 0x100>; | ||
305 | interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>; | ||
306 | #address-cells = <1>; | ||
307 | #size-cells = <0>; | ||
308 | clocks = <&k3_clks 220 1>; | ||
309 | clock-names = "fck"; | ||
310 | power-domains = <&k3_pds 220 TI_SCI_PD_EXCLUSIVE>; | ||
311 | }; | ||
312 | |||
313 | main_sdhci0: mmc@4f80000 { | ||
314 | compatible = "ti,j721e-sdhci-8bit"; | ||
315 | reg = <0x00 0x04f80000 0x00 0x1000>, | ||
316 | <0x00 0x04f88000 0x00 0x400>; | ||
317 | interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; | ||
318 | power-domains = <&k3_pds 98 TI_SCI_PD_EXCLUSIVE>; | ||
319 | clocks = <&k3_clks 98 7>, <&k3_clks 98 1>; | ||
320 | clock-names = "clk_ahb", "clk_xin"; | ||
321 | assigned-clocks = <&k3_clks 98 1>; | ||
322 | assigned-clock-parents = <&k3_clks 98 2>; | ||
323 | bus-width = <8>; | ||
324 | ti,otap-del-sel-legacy = <0x0>; | ||
325 | ti,otap-del-sel-mmc-hs = <0x0>; | ||
326 | ti,otap-del-sel-ddr52 = <0x6>; | ||
327 | ti,otap-del-sel-hs200 = <0x8>; | ||
328 | ti,otap-del-sel-hs400 = <0x5>; | ||
329 | ti,itap-del-sel-legacy = <0x10>; | ||
330 | ti,itap-del-sel-mmc-hs = <0xa>; | ||
331 | ti,strobe-sel = <0x77>; | ||
332 | ti,clkbuf-sel = <0x7>; | ||
333 | ti,trm-icp = <0x8>; | ||
334 | mmc-ddr-1_8v; | ||
335 | mmc-hs200-1_8v; | ||
336 | mmc-hs400-1_8v; | ||
337 | dma-coherent; | ||
338 | }; | ||
339 | |||
340 | main_sdhci1: mmc@4fb0000 { | ||
341 | compatible = "ti,j721e-sdhci-4bit"; | ||
342 | reg = <0x00 0x04fb0000 0x00 0x1000>, | ||
343 | <0x00 0x04fb8000 0x00 0x400>; | ||
344 | interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; | ||
345 | power-domains = <&k3_pds 99 TI_SCI_PD_EXCLUSIVE>; | ||
346 | clocks = <&k3_clks 99 8>, <&k3_clks 99 1>; | ||
347 | clock-names = "clk_ahb", "clk_xin"; | ||
348 | assigned-clocks = <&k3_clks 99 1>; | ||
349 | assigned-clock-parents = <&k3_clks 99 2>; | ||
350 | bus-width = <4>; | ||
351 | ti,otap-del-sel-legacy = <0x0>; | ||
352 | ti,otap-del-sel-sd-hs = <0x0>; | ||
353 | ti,otap-del-sel-sdr12 = <0xf>; | ||
354 | ti,otap-del-sel-sdr25 = <0xf>; | ||
355 | ti,otap-del-sel-sdr50 = <0xc>; | ||
356 | ti,otap-del-sel-sdr104 = <0x5>; | ||
357 | ti,otap-del-sel-ddr50 = <0xc>; | ||
358 | ti,itap-del-sel-legacy = <0x0>; | ||
359 | ti,itap-del-sel-sd-hs = <0x0>; | ||
360 | ti,itap-del-sel-sdr12 = <0x0>; | ||
361 | ti,itap-del-sel-sdr25 = <0x0>; | ||
362 | ti,clkbuf-sel = <0x7>; | ||
363 | ti,trm-icp = <0x8>; | ||
364 | dma-coherent; | ||
365 | /* Masking support for SDR104 capability */ | ||
366 | sdhci-caps-mask = <0x00000003 0x00000000>; | ||
367 | }; | ||
368 | |||
369 | main_navss: bus@30000000 { | ||
370 | compatible = "simple-mfd"; | ||
371 | #address-cells = <2>; | ||
372 | #size-cells = <2>; | ||
373 | ranges = <0x00 0x30000000 0x00 0x30000000 0x00 0x0c400000>; | ||
374 | ti,sci-dev-id = <224>; | ||
375 | dma-coherent; | ||
376 | dma-ranges; | ||
377 | |||
378 | main_navss_intr: interrupt-controller@310e0000 { | ||
379 | compatible = "ti,sci-intr"; | ||
380 | reg = <0x00 0x310e0000 0x00 0x4000>; | ||
381 | ti,intr-trigger-type = <4>; | ||
382 | interrupt-controller; | ||
383 | interrupt-parent = <&gic500>; | ||
384 | #interrupt-cells = <1>; | ||
385 | ti,sci = <&sms>; | ||
386 | ti,sci-dev-id = <227>; | ||
387 | ti,interrupt-ranges = <0 64 64>, | ||
388 | <64 448 64>, | ||
389 | <128 672 64>; | ||
390 | }; | ||
391 | |||
392 | main_udmass_inta: msi-controller@33d00000 { | ||
393 | compatible = "ti,sci-inta"; | ||
394 | reg = <0x00 0x33d00000 0x00 0x100000>; | ||
395 | interrupt-controller; | ||
396 | #interrupt-cells = <0>; | ||
397 | interrupt-parent = <&main_navss_intr>; | ||
398 | msi-controller; | ||
399 | ti,sci = <&sms>; | ||
400 | ti,sci-dev-id = <265>; | ||
401 | ti,interrupt-ranges = <0 0 256>; | ||
402 | }; | ||
403 | |||
404 | secure_proxy_main: mailbox@32c00000 { | ||
405 | compatible = "ti,am654-secure-proxy"; | ||
406 | #mbox-cells = <1>; | ||
407 | reg-names = "target_data", "rt", "scfg"; | ||
408 | reg = <0x00 0x32c00000 0x00 0x100000>, | ||
409 | <0x00 0x32400000 0x00 0x100000>, | ||
410 | <0x00 0x32800000 0x00 0x100000>; | ||
411 | interrupt-names = "rx_011"; | ||
412 | interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; | ||
413 | }; | ||
414 | |||
415 | hwspinlock: spinlock@30e00000 { | ||
416 | compatible = "ti,am654-hwspinlock"; | ||
417 | reg = <0x00 0x30e00000 0x00 0x1000>; | ||
418 | #hwlock-cells = <1>; | ||
419 | }; | ||
420 | |||
421 | mailbox0_cluster0: mailbox@31f80000 { | ||
422 | compatible = "ti,am654-mailbox"; | ||
423 | reg = <0x00 0x31f80000 0x00 0x200>; | ||
424 | #mbox-cells = <1>; | ||
425 | ti,mbox-num-users = <4>; | ||
426 | ti,mbox-num-fifos = <16>; | ||
427 | interrupt-parent = <&main_navss_intr>; | ||
428 | }; | ||
429 | |||
430 | mailbox0_cluster1: mailbox@31f81000 { | ||
431 | compatible = "ti,am654-mailbox"; | ||
432 | reg = <0x00 0x31f81000 0x00 0x200>; | ||
433 | #mbox-cells = <1>; | ||
434 | ti,mbox-num-users = <4>; | ||
435 | ti,mbox-num-fifos = <16>; | ||
436 | interrupt-parent = <&main_navss_intr>; | ||
437 | }; | ||
438 | |||
439 | mailbox0_cluster2: mailbox@31f82000 { | ||
440 | compatible = "ti,am654-mailbox"; | ||
441 | reg = <0x00 0x31f82000 0x00 0x200>; | ||
442 | #mbox-cells = <1>; | ||
443 | ti,mbox-num-users = <4>; | ||
444 | ti,mbox-num-fifos = <16>; | ||
445 | interrupt-parent = <&main_navss_intr>; | ||
446 | }; | ||
447 | |||
448 | mailbox0_cluster3: mailbox@31f83000 { | ||
449 | compatible = "ti,am654-mailbox"; | ||
450 | reg = <0x00 0x31f83000 0x00 0x200>; | ||
451 | #mbox-cells = <1>; | ||
452 | ti,mbox-num-users = <4>; | ||
453 | ti,mbox-num-fifos = <16>; | ||
454 | interrupt-parent = <&main_navss_intr>; | ||
455 | }; | ||
456 | |||
457 | mailbox0_cluster4: mailbox@31f84000 { | ||
458 | compatible = "ti,am654-mailbox"; | ||
459 | reg = <0x00 0x31f84000 0x00 0x200>; | ||
460 | #mbox-cells = <1>; | ||
461 | ti,mbox-num-users = <4>; | ||
462 | ti,mbox-num-fifos = <16>; | ||
463 | interrupt-parent = <&main_navss_intr>; | ||
464 | }; | ||
465 | |||
466 | mailbox0_cluster5: mailbox@31f85000 { | ||
467 | compatible = "ti,am654-mailbox"; | ||
468 | reg = <0x00 0x31f85000 0x00 0x200>; | ||
469 | #mbox-cells = <1>; | ||
470 | ti,mbox-num-users = <4>; | ||
471 | ti,mbox-num-fifos = <16>; | ||
472 | interrupt-parent = <&main_navss_intr>; | ||
473 | }; | ||
474 | |||
475 | mailbox0_cluster6: mailbox@31f86000 { | ||
476 | compatible = "ti,am654-mailbox"; | ||
477 | reg = <0x00 0x31f86000 0x00 0x200>; | ||
478 | #mbox-cells = <1>; | ||
479 | ti,mbox-num-users = <4>; | ||
480 | ti,mbox-num-fifos = <16>; | ||
481 | interrupt-parent = <&main_navss_intr>; | ||
482 | }; | ||
483 | |||
484 | mailbox0_cluster7: mailbox@31f87000 { | ||
485 | compatible = "ti,am654-mailbox"; | ||
486 | reg = <0x00 0x31f87000 0x00 0x200>; | ||
487 | #mbox-cells = <1>; | ||
488 | ti,mbox-num-users = <4>; | ||
489 | ti,mbox-num-fifos = <16>; | ||
490 | interrupt-parent = <&main_navss_intr>; | ||
491 | }; | ||
492 | |||
493 | mailbox0_cluster8: mailbox@31f88000 { | ||
494 | compatible = "ti,am654-mailbox"; | ||
495 | reg = <0x00 0x31f88000 0x00 0x200>; | ||
496 | #mbox-cells = <1>; | ||
497 | ti,mbox-num-users = <4>; | ||
498 | ti,mbox-num-fifos = <16>; | ||
499 | interrupt-parent = <&main_navss_intr>; | ||
500 | }; | ||
501 | |||
502 | mailbox0_cluster9: mailbox@31f89000 { | ||
503 | compatible = "ti,am654-mailbox"; | ||
504 | reg = <0x00 0x31f89000 0x00 0x200>; | ||
505 | #mbox-cells = <1>; | ||
506 | ti,mbox-num-users = <4>; | ||
507 | ti,mbox-num-fifos = <16>; | ||
508 | interrupt-parent = <&main_navss_intr>; | ||
509 | }; | ||
510 | |||
511 | mailbox0_cluster10: mailbox@31f8a000 { | ||
512 | compatible = "ti,am654-mailbox"; | ||
513 | reg = <0x00 0x31f8a000 0x00 0x200>; | ||
514 | #mbox-cells = <1>; | ||
515 | ti,mbox-num-users = <4>; | ||
516 | ti,mbox-num-fifos = <16>; | ||
517 | interrupt-parent = <&main_navss_intr>; | ||
518 | }; | ||
519 | |||
520 | mailbox0_cluster11: mailbox@31f8b000 { | ||
521 | compatible = "ti,am654-mailbox"; | ||
522 | reg = <0x00 0x31f8b000 0x00 0x200>; | ||
523 | #mbox-cells = <1>; | ||
524 | ti,mbox-num-users = <4>; | ||
525 | ti,mbox-num-fifos = <16>; | ||
526 | interrupt-parent = <&main_navss_intr>; | ||
527 | }; | ||
528 | |||
529 | mailbox1_cluster0: mailbox@31f90000 { | ||
530 | compatible = "ti,am654-mailbox"; | ||
531 | reg = <0x00 0x31f90000 0x00 0x200>; | ||
532 | #mbox-cells = <1>; | ||
533 | ti,mbox-num-users = <4>; | ||
534 | ti,mbox-num-fifos = <16>; | ||
535 | interrupt-parent = <&main_navss_intr>; | ||
536 | }; | ||
537 | |||
538 | mailbox1_cluster1: mailbox@31f91000 { | ||
539 | compatible = "ti,am654-mailbox"; | ||
540 | reg = <0x00 0x31f91000 0x00 0x200>; | ||
541 | #mbox-cells = <1>; | ||
542 | ti,mbox-num-users = <4>; | ||
543 | ti,mbox-num-fifos = <16>; | ||
544 | interrupt-parent = <&main_navss_intr>; | ||
545 | }; | ||
546 | |||
547 | mailbox1_cluster2: mailbox@31f92000 { | ||
548 | compatible = "ti,am654-mailbox"; | ||
549 | reg = <0x00 0x31f92000 0x00 0x200>; | ||
550 | #mbox-cells = <1>; | ||
551 | ti,mbox-num-users = <4>; | ||
552 | ti,mbox-num-fifos = <16>; | ||
553 | interrupt-parent = <&main_navss_intr>; | ||
554 | }; | ||
555 | |||
556 | mailbox1_cluster3: mailbox@31f93000 { | ||
557 | compatible = "ti,am654-mailbox"; | ||
558 | reg = <0x00 0x31f93000 0x00 0x200>; | ||
559 | #mbox-cells = <1>; | ||
560 | ti,mbox-num-users = <4>; | ||
561 | ti,mbox-num-fifos = <16>; | ||
562 | interrupt-parent = <&main_navss_intr>; | ||
563 | }; | ||
564 | |||
565 | mailbox1_cluster4: mailbox@31f94000 { | ||
566 | compatible = "ti,am654-mailbox"; | ||
567 | reg = <0x00 0x31f94000 0x00 0x200>; | ||
568 | #mbox-cells = <1>; | ||
569 | ti,mbox-num-users = <4>; | ||
570 | ti,mbox-num-fifos = <16>; | ||
571 | interrupt-parent = <&main_navss_intr>; | ||
572 | }; | ||
573 | |||
574 | mailbox1_cluster5: mailbox@31f95000 { | ||
575 | compatible = "ti,am654-mailbox"; | ||
576 | reg = <0x00 0x31f95000 0x00 0x200>; | ||
577 | #mbox-cells = <1>; | ||
578 | ti,mbox-num-users = <4>; | ||
579 | ti,mbox-num-fifos = <16>; | ||
580 | interrupt-parent = <&main_navss_intr>; | ||
581 | }; | ||
582 | |||
583 | mailbox1_cluster6: mailbox@31f96000 { | ||
584 | compatible = "ti,am654-mailbox"; | ||
585 | reg = <0x00 0x31f96000 0x00 0x200>; | ||
586 | #mbox-cells = <1>; | ||
587 | ti,mbox-num-users = <4>; | ||
588 | ti,mbox-num-fifos = <16>; | ||
589 | interrupt-parent = <&main_navss_intr>; | ||
590 | }; | ||
591 | |||
592 | mailbox1_cluster7: mailbox@31f97000 { | ||
593 | compatible = "ti,am654-mailbox"; | ||
594 | reg = <0x00 0x31f97000 0x00 0x200>; | ||
595 | #mbox-cells = <1>; | ||
596 | ti,mbox-num-users = <4>; | ||
597 | ti,mbox-num-fifos = <16>; | ||
598 | interrupt-parent = <&main_navss_intr>; | ||
599 | }; | ||
600 | |||
601 | mailbox1_cluster8: mailbox@31f98000 { | ||
602 | compatible = "ti,am654-mailbox"; | ||
603 | reg = <0x00 0x31f98000 0x00 0x200>; | ||
604 | #mbox-cells = <1>; | ||
605 | ti,mbox-num-users = <4>; | ||
606 | ti,mbox-num-fifos = <16>; | ||
607 | interrupt-parent = <&main_navss_intr>; | ||
608 | }; | ||
609 | |||
610 | mailbox1_cluster9: mailbox@31f99000 { | ||
611 | compatible = "ti,am654-mailbox"; | ||
612 | reg = <0x00 0x31f99000 0x00 0x200>; | ||
613 | #mbox-cells = <1>; | ||
614 | ti,mbox-num-users = <4>; | ||
615 | ti,mbox-num-fifos = <16>; | ||
616 | interrupt-parent = <&main_navss_intr>; | ||
617 | }; | ||
618 | |||
619 | mailbox1_cluster10: mailbox@31f9a000 { | ||
620 | compatible = "ti,am654-mailbox"; | ||
621 | reg = <0x00 0x31f9a000 0x00 0x200>; | ||
622 | #mbox-cells = <1>; | ||
623 | ti,mbox-num-users = <4>; | ||
624 | ti,mbox-num-fifos = <16>; | ||
625 | interrupt-parent = <&main_navss_intr>; | ||
626 | }; | ||
627 | |||
628 | mailbox1_cluster11: mailbox@31f9b000 { | ||
629 | compatible = "ti,am654-mailbox"; | ||
630 | reg = <0x00 0x31f9b000 0x00 0x200>; | ||
631 | #mbox-cells = <1>; | ||
632 | ti,mbox-num-users = <4>; | ||
633 | ti,mbox-num-fifos = <16>; | ||
634 | interrupt-parent = <&main_navss_intr>; | ||
635 | }; | ||
636 | |||
637 | main_ringacc: ringacc@3c000000 { | ||
638 | compatible = "ti,am654-navss-ringacc"; | ||
639 | reg = <0x0 0x3c000000 0x0 0x400000>, | ||
640 | <0x0 0x38000000 0x0 0x400000>, | ||
641 | <0x0 0x31120000 0x0 0x100>, | ||
642 | <0x0 0x33000000 0x0 0x40000>; | ||
643 | reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target"; | ||
644 | ti,num-rings = <1024>; | ||
645 | ti,sci-rm-range-gp-rings = <0x1>; | ||
646 | ti,sci = <&sms>; | ||
647 | ti,sci-dev-id = <259>; | ||
648 | msi-parent = <&main_udmass_inta>; | ||
649 | }; | ||
650 | |||
651 | main_udmap: dma-controller@31150000 { | ||
652 | compatible = "ti,j721e-navss-main-udmap"; | ||
653 | reg = <0x0 0x31150000 0x0 0x100>, | ||
654 | <0x0 0x34000000 0x0 0x80000>, | ||
655 | <0x0 0x35000000 0x0 0x200000>; | ||
656 | reg-names = "gcfg", "rchanrt", "tchanrt"; | ||
657 | msi-parent = <&main_udmass_inta>; | ||
658 | #dma-cells = <1>; | ||
659 | |||
660 | ti,sci = <&sms>; | ||
661 | ti,sci-dev-id = <263>; | ||
662 | ti,ringacc = <&main_ringacc>; | ||
663 | |||
664 | ti,sci-rm-range-tchan = <0x0d>, /* TX_CHAN */ | ||
665 | <0x0f>, /* TX_HCHAN */ | ||
666 | <0x10>; /* TX_UHCHAN */ | ||
667 | ti,sci-rm-range-rchan = <0x0a>, /* RX_CHAN */ | ||
668 | <0x0b>, /* RX_HCHAN */ | ||
669 | <0x0c>; /* RX_UHCHAN */ | ||
670 | ti,sci-rm-range-rflow = <0x00>; /* GP RFLOW */ | ||
671 | }; | ||
672 | |||
673 | cpts@310d0000 { | ||
674 | compatible = "ti,j721e-cpts"; | ||
675 | reg = <0x0 0x310d0000 0x0 0x400>; | ||
676 | reg-names = "cpts"; | ||
677 | clocks = <&k3_clks 226 5>; | ||
678 | clock-names = "cpts"; | ||
679 | interrupts-extended = <&main_navss_intr 391>; | ||
680 | interrupt-names = "cpts"; | ||
681 | ti,cpts-periodic-outputs = <6>; | ||
682 | ti,cpts-ext-ts-inputs = <8>; | ||
683 | }; | ||
684 | }; | ||
685 | |||
686 | main_mcan0: can@2701000 { | ||
687 | compatible = "bosch,m_can"; | ||
688 | reg = <0x00 0x02701000 0x00 0x200>, | ||
689 | <0x00 0x02708000 0x00 0x8000>; | ||
690 | reg-names = "m_can", "message_ram"; | ||
691 | power-domains = <&k3_pds 182 TI_SCI_PD_EXCLUSIVE>; | ||
692 | clocks = <&k3_clks 182 0>, <&k3_clks 182 1>; | ||
693 | clock-names = "hclk", "cclk"; | ||
694 | interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>, | ||
695 | <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>; | ||
696 | interrupt-names = "int0", "int1"; | ||
697 | bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; | ||
698 | }; | ||
699 | |||
700 | main_mcan1: can@2711000 { | ||
701 | compatible = "bosch,m_can"; | ||
702 | reg = <0x00 0x02711000 0x00 0x200>, | ||
703 | <0x00 0x02718000 0x00 0x8000>; | ||
704 | reg-names = "m_can", "message_ram"; | ||
705 | power-domains = <&k3_pds 183 TI_SCI_PD_EXCLUSIVE>; | ||
706 | clocks = <&k3_clks 183 0>, <&k3_clks 183 1>; | ||
707 | clock-names = "hclk", "cclk"; | ||
708 | interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>, | ||
709 | <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>; | ||
710 | interrupt-names = "int0", "int1"; | ||
711 | bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; | ||
712 | }; | ||
713 | |||
714 | main_mcan2: can@2721000 { | ||
715 | compatible = "bosch,m_can"; | ||
716 | reg = <0x00 0x02721000 0x00 0x200>, | ||
717 | <0x00 0x02728000 0x00 0x8000>; | ||
718 | reg-names = "m_can", "message_ram"; | ||
719 | power-domains = <&k3_pds 184 TI_SCI_PD_EXCLUSIVE>; | ||
720 | clocks = <&k3_clks 184 0>, <&k3_clks 184 1>; | ||
721 | clock-names = "hclk", "cclk"; | ||
722 | interrupts = <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, | ||
723 | <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>; | ||
724 | interrupt-names = "int0", "int1"; | ||
725 | bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; | ||
726 | }; | ||
727 | |||
728 | main_mcan3: can@2731000 { | ||
729 | compatible = "bosch,m_can"; | ||
730 | reg = <0x00 0x02731000 0x00 0x200>, | ||
731 | <0x00 0x02738000 0x00 0x8000>; | ||
732 | reg-names = "m_can", "message_ram"; | ||
733 | power-domains = <&k3_pds 185 TI_SCI_PD_EXCLUSIVE>; | ||
734 | clocks = <&k3_clks 185 0>, <&k3_clks 185 1>; | ||
735 | clock-names = "hclk", "cclk"; | ||
736 | interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>, | ||
737 | <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>; | ||
738 | interrupt-names = "int0", "int1"; | ||
739 | bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; | ||
740 | }; | ||
741 | |||
742 | main_mcan4: can@2741000 { | ||
743 | compatible = "bosch,m_can"; | ||
744 | reg = <0x00 0x02741000 0x00 0x200>, | ||
745 | <0x00 0x02748000 0x00 0x8000>; | ||
746 | reg-names = "m_can", "message_ram"; | ||
747 | power-domains = <&k3_pds 186 TI_SCI_PD_EXCLUSIVE>; | ||
748 | clocks = <&k3_clks 186 0>, <&k3_clks 186 1>; | ||
749 | clock-names = "hclk", "cclk"; | ||
750 | interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>, | ||
751 | <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>; | ||
752 | interrupt-names = "int0", "int1"; | ||
753 | bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; | ||
754 | }; | ||
755 | |||
756 | main_mcan5: can@2751000 { | ||
757 | compatible = "bosch,m_can"; | ||
758 | reg = <0x00 0x02751000 0x00 0x200>, | ||
759 | <0x00 0x02758000 0x00 0x8000>; | ||
760 | reg-names = "m_can", "message_ram"; | ||
761 | power-domains = <&k3_pds 187 TI_SCI_PD_EXCLUSIVE>; | ||
762 | clocks = <&k3_clks 187 0>, <&k3_clks 187 1>; | ||
763 | clock-names = "hclk", "cclk"; | ||
764 | interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>, | ||
765 | <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>; | ||
766 | interrupt-names = "int0", "int1"; | ||
767 | bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; | ||
768 | }; | ||
769 | |||
770 | main_mcan6: can@2761000 { | ||
771 | compatible = "bosch,m_can"; | ||
772 | reg = <0x00 0x02761000 0x00 0x200>, | ||
773 | <0x00 0x02768000 0x00 0x8000>; | ||
774 | reg-names = "m_can", "message_ram"; | ||
775 | power-domains = <&k3_pds 188 TI_SCI_PD_EXCLUSIVE>; | ||
776 | clocks = <&k3_clks 188 0>, <&k3_clks 188 1>; | ||
777 | clock-names = "hclk", "cclk"; | ||
778 | interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, | ||
779 | <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>; | ||
780 | interrupt-names = "int0", "int1"; | ||
781 | bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; | ||
782 | }; | ||
783 | |||
784 | main_mcan7: can@2771000 { | ||
785 | compatible = "bosch,m_can"; | ||
786 | reg = <0x00 0x02771000 0x00 0x200>, | ||
787 | <0x00 0x02778000 0x00 0x8000>; | ||
788 | reg-names = "m_can", "message_ram"; | ||
789 | power-domains = <&k3_pds 189 TI_SCI_PD_EXCLUSIVE>; | ||
790 | clocks = <&k3_clks 189 0>, <&k3_clks 189 1>; | ||
791 | clock-names = "hclk", "cclk"; | ||
792 | interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>, | ||
793 | <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>; | ||
794 | interrupt-names = "int0", "int1"; | ||
795 | bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; | ||
796 | }; | ||
797 | |||
798 | main_mcan8: can@2781000 { | ||
799 | compatible = "bosch,m_can"; | ||
800 | reg = <0x00 0x02781000 0x00 0x200>, | ||
801 | <0x00 0x02788000 0x00 0x8000>; | ||
802 | reg-names = "m_can", "message_ram"; | ||
803 | power-domains = <&k3_pds 190 TI_SCI_PD_EXCLUSIVE>; | ||
804 | clocks = <&k3_clks 190 0>, <&k3_clks 190 1>; | ||
805 | clock-names = "hclk", "cclk"; | ||
806 | interrupts = <GIC_SPI 576 IRQ_TYPE_LEVEL_HIGH>, | ||
807 | <GIC_SPI 577 IRQ_TYPE_LEVEL_HIGH>; | ||
808 | interrupt-names = "int0", "int1"; | ||
809 | bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; | ||
810 | }; | ||
811 | |||
812 | main_mcan9: can@2791000 { | ||
813 | compatible = "bosch,m_can"; | ||
814 | reg = <0x00 0x02791000 0x00 0x200>, | ||
815 | <0x00 0x02798000 0x00 0x8000>; | ||
816 | reg-names = "m_can", "message_ram"; | ||
817 | power-domains = <&k3_pds 191 TI_SCI_PD_EXCLUSIVE>; | ||
818 | clocks = <&k3_clks 191 0>, <&k3_clks 191 1>; | ||
819 | clock-names = "hclk", "cclk"; | ||
820 | interrupts = <GIC_SPI 579 IRQ_TYPE_LEVEL_HIGH>, | ||
821 | <GIC_SPI 580 IRQ_TYPE_LEVEL_HIGH>; | ||
822 | interrupt-names = "int0", "int1"; | ||
823 | bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; | ||
824 | }; | ||
825 | |||
826 | main_mcan10: can@27a1000 { | ||
827 | compatible = "bosch,m_can"; | ||
828 | reg = <0x00 0x027a1000 0x00 0x200>, | ||
829 | <0x00 0x027a8000 0x00 0x8000>; | ||
830 | reg-names = "m_can", "message_ram"; | ||
831 | power-domains = <&k3_pds 192 TI_SCI_PD_EXCLUSIVE>; | ||
832 | clocks = <&k3_clks 192 0>, <&k3_clks 192 1>; | ||
833 | clock-names = "hclk", "cclk"; | ||
834 | interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>, | ||
835 | <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>; | ||
836 | interrupt-names = "int0", "int1"; | ||
837 | bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; | ||
838 | }; | ||
839 | |||
840 | main_mcan11: can@27b1000 { | ||
841 | compatible = "bosch,m_can"; | ||
842 | reg = <0x00 0x027b1000 0x00 0x200>, | ||
843 | <0x00 0x027b8000 0x00 0x8000>; | ||
844 | reg-names = "m_can", "message_ram"; | ||
845 | power-domains = <&k3_pds 193 TI_SCI_PD_EXCLUSIVE>; | ||
846 | clocks = <&k3_clks 193 0>, <&k3_clks 193 1>; | ||
847 | clock-names = "hclk", "cclk"; | ||
848 | interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>, | ||
849 | <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>; | ||
850 | interrupt-names = "int0", "int1"; | ||
851 | bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; | ||
852 | }; | ||
853 | |||
854 | main_mcan12: can@27c1000 { | ||
855 | compatible = "bosch,m_can"; | ||
856 | reg = <0x00 0x027c1000 0x00 0x200>, | ||
857 | <0x00 0x027c8000 0x00 0x8000>; | ||
858 | reg-names = "m_can", "message_ram"; | ||
859 | power-domains = <&k3_pds 194 TI_SCI_PD_EXCLUSIVE>; | ||
860 | clocks = <&k3_clks 194 0>, <&k3_clks 194 1>; | ||
861 | clock-names = "hclk", "cclk"; | ||
862 | interrupts = <GIC_SPI 588 IRQ_TYPE_LEVEL_HIGH>, | ||
863 | <GIC_SPI 589 IRQ_TYPE_LEVEL_HIGH>; | ||
864 | interrupt-names = "int0", "int1"; | ||
865 | bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; | ||
866 | }; | ||
867 | |||
868 | main_mcan13: can@27d1000 { | ||
869 | compatible = "bosch,m_can"; | ||
870 | reg = <0x00 0x027d1000 0x00 0x200>, | ||
871 | <0x00 0x027d8000 0x00 0x8000>; | ||
872 | reg-names = "m_can", "message_ram"; | ||
873 | power-domains = <&k3_pds 195 TI_SCI_PD_EXCLUSIVE>; | ||
874 | clocks = <&k3_clks 195 0>, <&k3_clks 195 1>; | ||
875 | clock-names = "hclk", "cclk"; | ||
876 | interrupts = <GIC_SPI 591 IRQ_TYPE_LEVEL_HIGH>, | ||
877 | <GIC_SPI 592 IRQ_TYPE_LEVEL_HIGH>; | ||
878 | interrupt-names = "int0", "int1"; | ||
879 | bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; | ||
880 | }; | ||
881 | |||
882 | main_mcan14: can@2681000 { | ||
883 | compatible = "bosch,m_can"; | ||
884 | reg = <0x00 0x02681000 0x00 0x200>, | ||
885 | <0x00 0x02688000 0x00 0x8000>; | ||
886 | reg-names = "m_can", "message_ram"; | ||
887 | power-domains = <&k3_pds 197 TI_SCI_PD_EXCLUSIVE>; | ||
888 | clocks = <&k3_clks 197 0>, <&k3_clks 197 1>; | ||
889 | clock-names = "hclk", "cclk"; | ||
890 | interrupts = <GIC_SPI 594 IRQ_TYPE_LEVEL_HIGH>, | ||
891 | <GIC_SPI 595 IRQ_TYPE_LEVEL_HIGH>; | ||
892 | interrupt-names = "int0", "int1"; | ||
893 | bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; | ||
894 | }; | ||
895 | |||
896 | main_mcan15: can@2691000 { | ||
897 | compatible = "bosch,m_can"; | ||
898 | reg = <0x00 0x02691000 0x00 0x200>, | ||
899 | <0x00 0x02698000 0x00 0x8000>; | ||
900 | reg-names = "m_can", "message_ram"; | ||
901 | power-domains = <&k3_pds 199 TI_SCI_PD_EXCLUSIVE>; | ||
902 | clocks = <&k3_clks 199 0>, <&k3_clks 199 1>; | ||
903 | clock-names = "hclk", "cclk"; | ||
904 | interrupts = <GIC_SPI 597 IRQ_TYPE_LEVEL_HIGH>, | ||
905 | <GIC_SPI 598 IRQ_TYPE_LEVEL_HIGH>; | ||
906 | interrupt-names = "int0", "int1"; | ||
907 | bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; | ||
908 | }; | ||
909 | |||
910 | main_mcan16: can@26a1000 { | ||
911 | compatible = "bosch,m_can"; | ||
912 | reg = <0x00 0x026a1000 0x00 0x200>, | ||
913 | <0x00 0x026a8000 0x00 0x8000>; | ||
914 | reg-names = "m_can", "message_ram"; | ||
915 | power-domains = <&k3_pds 201 TI_SCI_PD_EXCLUSIVE>; | ||
916 | clocks = <&k3_clks 201 0>, <&k3_clks 201 1>; | ||
917 | clock-names = "hclk", "cclk"; | ||
918 | interrupts = <GIC_SPI 784 IRQ_TYPE_LEVEL_HIGH>, | ||
919 | <GIC_SPI 785 IRQ_TYPE_LEVEL_HIGH>; | ||
920 | interrupt-names = "int0", "int1"; | ||
921 | bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; | ||
922 | }; | ||
923 | |||
924 | main_mcan17: can@26b1000 { | ||
925 | compatible = "bosch,m_can"; | ||
926 | reg = <0x00 0x026b1000 0x00 0x200>, | ||
927 | <0x00 0x026b8000 0x00 0x8000>; | ||
928 | reg-names = "m_can", "message_ram"; | ||
929 | power-domains = <&k3_pds 206 TI_SCI_PD_EXCLUSIVE>; | ||
930 | clocks = <&k3_clks 206 0>, <&k3_clks 206 1>; | ||
931 | clock-names = "hclk", "cclk"; | ||
932 | interrupts = <GIC_SPI 787 IRQ_TYPE_LEVEL_HIGH>, | ||
933 | <GIC_SPI 788 IRQ_TYPE_LEVEL_HIGH>; | ||
934 | interrupt-names = "int0", "int1"; | ||
935 | bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; | ||
936 | }; | ||
937 | }; | ||
diff --git a/arch/arm64/boot/dts/ti/k3-j721s2-mcu-wakeup.dtsi b/arch/arm64/boot/dts/ti/k3-j721s2-mcu-wakeup.dtsi new file mode 100644 index 000000000000..7521963719ff --- /dev/null +++ b/arch/arm64/boot/dts/ti/k3-j721s2-mcu-wakeup.dtsi | |||
@@ -0,0 +1,302 @@ | |||
1 | // SPDX-License-Identifier: GPL-2.0 | ||
2 | /* | ||
3 | * Device Tree Source for J721S2 SoC Family MCU/WAKEUP Domain peripherals | ||
4 | * | ||
5 | * Copyright (C) 2021 Texas Instruments Incorporated - https://www.ti.com/ | ||
6 | */ | ||
7 | |||
8 | &cbass_mcu_wakeup { | ||
9 | sms: system-controller@44083000 { | ||
10 | compatible = "ti,k2g-sci"; | ||
11 | ti,host-id = <12>; | ||
12 | |||
13 | mbox-names = "rx", "tx"; | ||
14 | |||
15 | mboxes= <&secure_proxy_main 11>, | ||
16 | <&secure_proxy_main 13>; | ||
17 | |||
18 | reg-names = "debug_messages"; | ||
19 | reg = <0x00 0x44083000 0x00 0x1000>; | ||
20 | |||
21 | k3_pds: power-controller { | ||
22 | compatible = "ti,sci-pm-domain"; | ||
23 | #power-domain-cells = <2>; | ||
24 | }; | ||
25 | |||
26 | k3_clks: clock-controller { | ||
27 | compatible = "ti,k2g-sci-clk"; | ||
28 | #clock-cells = <2>; | ||
29 | }; | ||
30 | |||
31 | k3_reset: reset-controller { | ||
32 | compatible = "ti,sci-reset"; | ||
33 | #reset-cells = <2>; | ||
34 | }; | ||
35 | }; | ||
36 | |||
37 | chipid@43000014 { | ||
38 | compatible = "ti,am654-chipid"; | ||
39 | reg = <0x00 0x43000014 0x00 0x4>; | ||
40 | }; | ||
41 | |||
42 | mcu_ram: sram@41c00000 { | ||
43 | compatible = "mmio-sram"; | ||
44 | reg = <0x00 0x41c00000 0x00 0x100000>; | ||
45 | ranges = <0x00 0x00 0x41c00000 0x100000>; | ||
46 | #address-cells = <1>; | ||
47 | #size-cells = <1>; | ||
48 | }; | ||
49 | |||
50 | wkup_pmx0: pinctrl@4301c000 { | ||
51 | compatible = "pinctrl-single"; | ||
52 | /* Proxy 0 addressing */ | ||
53 | reg = <0x00 0x4301c000 0x00 0x178>; | ||
54 | #pinctrl-cells = <1>; | ||
55 | pinctrl-single,register-width = <32>; | ||
56 | pinctrl-single,function-mask = <0xffffffff>; | ||
57 | }; | ||
58 | |||
59 | wkup_gpio_intr: interrupt-controller@42200000 { | ||
60 | compatible = "ti,sci-intr"; | ||
61 | reg = <0x00 0x42200000 0x00 0x400>; | ||
62 | ti,intr-trigger-type = <1>; | ||
63 | interrupt-controller; | ||
64 | interrupt-parent = <&gic500>; | ||
65 | #interrupt-cells = <1>; | ||
66 | ti,sci = <&sms>; | ||
67 | ti,sci-dev-id = <125>; | ||
68 | ti,interrupt-ranges = <16 928 16>; | ||
69 | }; | ||
70 | |||
71 | mcu_conf: syscon@40f00000 { | ||
72 | compatible = "syscon", "simple-mfd"; | ||
73 | reg = <0x0 0x40f00000 0x0 0x20000>; | ||
74 | #address-cells = <1>; | ||
75 | #size-cells = <1>; | ||
76 | ranges = <0x0 0x0 0x40f00000 0x20000>; | ||
77 | |||
78 | phy_gmii_sel: phy@4040 { | ||
79 | compatible = "ti,am654-phy-gmii-sel"; | ||
80 | reg = <0x4040 0x4>; | ||
81 | #phy-cells = <1>; | ||
82 | }; | ||
83 | |||
84 | }; | ||
85 | |||
86 | wkup_uart0: serial@42300000 { | ||
87 | compatible = "ti,j721e-uart", "ti,am654-uart"; | ||
88 | reg = <0x00 0x42300000 0x00 0x200>; | ||
89 | interrupts = <GIC_SPI 897 IRQ_TYPE_LEVEL_HIGH>; | ||
90 | current-speed = <115200>; | ||
91 | clocks = <&k3_clks 359 3>; | ||
92 | clock-names = "fclk"; | ||
93 | power-domains = <&k3_pds 359 TI_SCI_PD_EXCLUSIVE>; | ||
94 | }; | ||
95 | |||
96 | mcu_uart0: serial@40a00000 { | ||
97 | compatible = "ti,j721e-uart", "ti,am654-uart"; | ||
98 | reg = <0x00 0x40a00000 0x00 0x200>; | ||
99 | interrupts = <GIC_SPI 846 IRQ_TYPE_LEVEL_HIGH>; | ||
100 | current-speed = <115200>; | ||
101 | clocks = <&k3_clks 149 3>; | ||
102 | clock-names = "fclk"; | ||
103 | power-domains = <&k3_pds 149 TI_SCI_PD_EXCLUSIVE>; | ||
104 | }; | ||
105 | |||
106 | wkup_gpio0: gpio@42110000 { | ||
107 | compatible = "ti,j721e-gpio", "ti,keystone-gpio"; | ||
108 | reg = <0x00 0x42110000 0x00 0x100>; | ||
109 | gpio-controller; | ||
110 | #gpio-cells = <2>; | ||
111 | interrupt-parent = <&main_gpio_intr>; | ||
112 | interrupts = <103>, <104>, <105>, <106>, <107>, <108>; | ||
113 | interrupt-controller; | ||
114 | #interrupt-cells = <2>; | ||
115 | ti,ngpio = <89>; | ||
116 | ti,davinci-gpio-unbanked = <0>; | ||
117 | power-domains = <&k3_pds 115 TI_SCI_PD_EXCLUSIVE>; | ||
118 | clocks = <&k3_clks 115 0>; | ||
119 | clock-names = "gpio"; | ||
120 | }; | ||
121 | |||
122 | wkup_gpio1: gpio@42100000 { | ||
123 | compatible = "ti,j721e-gpio", "ti,keystone-gpio"; | ||
124 | reg = <0x00 0x42100000 0x00 0x100>; | ||
125 | gpio-controller; | ||
126 | #gpio-cells = <2>; | ||
127 | interrupt-parent = <&main_gpio_intr>; | ||
128 | interrupts = <112>, <113>, <114>, <115>, <116>, <117>; | ||
129 | interrupt-controller; | ||
130 | #interrupt-cells = <2>; | ||
131 | ti,ngpio = <89>; | ||
132 | ti,davinci-gpio-unbanked = <0>; | ||
133 | power-domains = <&k3_pds 116 TI_SCI_PD_EXCLUSIVE>; | ||
134 | clocks = <&k3_clks 116 0>; | ||
135 | clock-names = "gpio"; | ||
136 | }; | ||
137 | |||
138 | wkup_i2c0: i2c@42120000 { | ||
139 | compatible = "ti,j721e-i2c", "ti,omap4-i2c"; | ||
140 | reg = <0x00 0x42120000 0x00 0x100>; | ||
141 | interrupts = <GIC_SPI 896 IRQ_TYPE_LEVEL_HIGH>; | ||
142 | #address-cells = <1>; | ||
143 | #size-cells = <0>; | ||
144 | clocks = <&k3_clks 223 1>; | ||
145 | clock-names = "fck"; | ||
146 | power-domains = <&k3_pds 223 TI_SCI_PD_EXCLUSIVE>; | ||
147 | }; | ||
148 | |||
149 | mcu_i2c0: i2c@40b00000 { | ||
150 | compatible = "ti,j721e-i2c", "ti,omap4-i2c"; | ||
151 | reg = <0x00 0x40b00000 0x00 0x100>; | ||
152 | interrupts = <GIC_SPI 852 IRQ_TYPE_LEVEL_HIGH>; | ||
153 | #address-cells = <1>; | ||
154 | #size-cells = <0>; | ||
155 | clocks = <&k3_clks 221 1>; | ||
156 | clock-names = "fck"; | ||
157 | power-domains = <&k3_pds 221 TI_SCI_PD_EXCLUSIVE>; | ||
158 | }; | ||
159 | |||
160 | mcu_i2c1: i2c@40b10000 { | ||
161 | compatible = "ti,j721e-i2c", "ti,omap4-i2c"; | ||
162 | reg = <0x00 0x40b10000 0x00 0x100>; | ||
163 | interrupts = <GIC_SPI 853 IRQ_TYPE_LEVEL_HIGH>; | ||
164 | #address-cells = <1>; | ||
165 | #size-cells = <0>; | ||
166 | clocks = <&k3_clks 222 1>; | ||
167 | clock-names = "fck"; | ||
168 | power-domains = <&k3_pds 222 TI_SCI_PD_EXCLUSIVE>; | ||
169 | }; | ||
170 | |||
171 | mcu_mcan0: can@40528000 { | ||
172 | compatible = "bosch,m_can"; | ||
173 | reg = <0x00 0x40528000 0x00 0x200>, | ||
174 | <0x00 0x40500000 0x00 0x8000>; | ||
175 | reg-names = "m_can", "message_ram"; | ||
176 | power-domains = <&k3_pds 207 TI_SCI_PD_EXCLUSIVE>; | ||
177 | clocks = <&k3_clks 207 0>, <&k3_clks 207 1>; | ||
178 | clock-names = "hclk", "cclk"; | ||
179 | interrupts = <GIC_SPI 832 IRQ_TYPE_LEVEL_HIGH>, | ||
180 | <GIC_SPI 833 IRQ_TYPE_LEVEL_HIGH>; | ||
181 | interrupt-names = "int0", "int1"; | ||
182 | bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; | ||
183 | }; | ||
184 | |||
185 | mcu_mcan1: can@40568000 { | ||
186 | compatible = "bosch,m_can"; | ||
187 | reg = <0x00 0x40568000 0x00 0x200>, | ||
188 | <0x00 0x40540000 0x00 0x8000>; | ||
189 | reg-names = "m_can", "message_ram"; | ||
190 | power-domains = <&k3_pds 208 TI_SCI_PD_EXCLUSIVE>; | ||
191 | clocks = <&k3_clks 208 0>, <&k3_clks 208 1>; | ||
192 | clock-names = "hclk", "cclk"; | ||
193 | interrupts = <GIC_SPI 835 IRQ_TYPE_LEVEL_HIGH>, | ||
194 | <GIC_SPI 836 IRQ_TYPE_LEVEL_HIGH>; | ||
195 | interrupt-names = "int0", "int1"; | ||
196 | bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; | ||
197 | }; | ||
198 | |||
199 | mcu_navss: bus@28380000{ | ||
200 | compatible = "simple-mfd"; | ||
201 | #address-cells = <2>; | ||
202 | #size-cells = <2>; | ||
203 | ranges = <0x00 0x28380000 0x00 0x28380000 0x00 0x03880000>; | ||
204 | dma-coherent; | ||
205 | dma-ranges; | ||
206 | |||
207 | ti,sci-dev-id = <267>; | ||
208 | |||
209 | mcu_ringacc: ringacc@2b800000 { | ||
210 | compatible = "ti,am654-navss-ringacc"; | ||
211 | reg = <0x0 0x2b800000 0x0 0x400000>, | ||
212 | <0x0 0x2b000000 0x0 0x400000>, | ||
213 | <0x0 0x28590000 0x0 0x100>, | ||
214 | <0x0 0x2a500000 0x0 0x40000>; | ||
215 | reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target"; | ||
216 | ti,num-rings = <286>; | ||
217 | ti,sci-rm-range-gp-rings = <0x1>; | ||
218 | ti,sci = <&sms>; | ||
219 | ti,sci-dev-id = <272>; | ||
220 | msi-parent = <&main_udmass_inta>; | ||
221 | }; | ||
222 | |||
223 | mcu_udmap: dma-controller@285c0000 { | ||
224 | compatible = "ti,j721e-navss-mcu-udmap"; | ||
225 | reg = <0x0 0x285c0000 0x0 0x100>, | ||
226 | <0x0 0x2a800000 0x0 0x40000>, | ||
227 | <0x0 0x2aa00000 0x0 0x40000>; | ||
228 | reg-names = "gcfg", "rchanrt", "tchanrt"; | ||
229 | msi-parent = <&main_udmass_inta>; | ||
230 | #dma-cells = <1>; | ||
231 | |||
232 | ti,sci = <&sms>; | ||
233 | ti,sci-dev-id = <273>; | ||
234 | ti,ringacc = <&mcu_ringacc>; | ||
235 | ti,sci-rm-range-tchan = <0x0d>, /* TX_CHAN */ | ||
236 | <0x0f>; /* TX_HCHAN */ | ||
237 | ti,sci-rm-range-rchan = <0x0a>, /* RX_CHAN */ | ||
238 | <0x0b>; /* RX_HCHAN */ | ||
239 | ti,sci-rm-range-rflow = <0x00>; /* GP RFLOW */ | ||
240 | }; | ||
241 | }; | ||
242 | |||
243 | mcu_cpsw: ethernet@46000000 { | ||
244 | compatible = "ti,j721e-cpsw-nuss"; | ||
245 | #address-cells = <2>; | ||
246 | #size-cells = <2>; | ||
247 | reg = <0x0 0x46000000 0x0 0x200000>; | ||
248 | reg-names = "cpsw_nuss"; | ||
249 | ranges = <0x0 0x0 0x0 0x46000000 0x0 0x200000>; | ||
250 | dma-coherent; | ||
251 | clocks = <&k3_clks 29 28>; | ||
252 | clock-names = "fck"; | ||
253 | power-domains = <&k3_pds 29 TI_SCI_PD_EXCLUSIVE>; | ||
254 | |||
255 | dmas = <&mcu_udmap 0xf000>, | ||
256 | <&mcu_udmap 0xf001>, | ||
257 | <&mcu_udmap 0xf002>, | ||
258 | <&mcu_udmap 0xf003>, | ||
259 | <&mcu_udmap 0xf004>, | ||
260 | <&mcu_udmap 0xf005>, | ||
261 | <&mcu_udmap 0xf006>, | ||
262 | <&mcu_udmap 0xf007>, | ||
263 | <&mcu_udmap 0x7000>; | ||
264 | dma-names = "tx0", "tx1", "tx2", "tx3", | ||
265 | "tx4", "tx5", "tx6", "tx7", | ||
266 | "rx"; | ||
267 | |||
268 | ethernet-ports { | ||
269 | #address-cells = <1>; | ||
270 | #size-cells = <0>; | ||
271 | |||
272 | cpsw_port1: port@1 { | ||
273 | reg = <1>; | ||
274 | ti,mac-only; | ||
275 | label = "port1"; | ||
276 | ti,syscon-efuse = <&mcu_conf 0x200>; | ||
277 | phys = <&phy_gmii_sel 1>; | ||
278 | }; | ||
279 | }; | ||
280 | |||
281 | davinci_mdio: mdio@f00 { | ||
282 | compatible = "ti,cpsw-mdio","ti,davinci_mdio"; | ||
283 | reg = <0x0 0xf00 0x0 0x100>; | ||
284 | #address-cells = <1>; | ||
285 | #size-cells = <0>; | ||
286 | clocks = <&k3_clks 29 28>; | ||
287 | clock-names = "fck"; | ||
288 | bus_freq = <1000000>; | ||
289 | }; | ||
290 | |||
291 | cpts@3d000 { | ||
292 | compatible = "ti,am65-cpts"; | ||
293 | reg = <0x0 0x3d000 0x0 0x400>; | ||
294 | clocks = <&k3_clks 29 3>; | ||
295 | clock-names = "cpts"; | ||
296 | interrupts-extended = <&gic500 GIC_SPI 858 IRQ_TYPE_LEVEL_HIGH>; | ||
297 | interrupt-names = "cpts"; | ||
298 | ti,cpts-ext-ts-inputs = <4>; | ||
299 | ti,cpts-periodic-outputs = <2>; | ||
300 | }; | ||
301 | }; | ||
302 | }; | ||
diff --git a/arch/arm64/boot/dts/ti/k3-j721s2-som-p0.dtsi b/arch/arm64/boot/dts/ti/k3-j721s2-som-p0.dtsi new file mode 100644 index 000000000000..76f0ceacb6d4 --- /dev/null +++ b/arch/arm64/boot/dts/ti/k3-j721s2-som-p0.dtsi | |||
@@ -0,0 +1,175 @@ | |||
1 | // SPDX-License-Identifier: GPL-2.0 | ||
2 | /* | ||
3 | * SoM: https://www.ti.com/lit/zip/sprr439 | ||
4 | * | ||
5 | * Copyright (C) 2021 Texas Instruments Incorporated - https://www.ti.com/ | ||
6 | */ | ||
7 | |||
8 | /dts-v1/; | ||
9 | |||
10 | #include "k3-j721s2.dtsi" | ||
11 | #include <dt-bindings/gpio/gpio.h> | ||
12 | |||
13 | / { | ||
14 | memory@80000000 { | ||
15 | device_type = "memory"; | ||
16 | /* 16 GB RAM */ | ||
17 | reg = <0x00 0x80000000 0x00 0x80000000>, | ||
18 | <0x08 0x80000000 0x03 0x80000000>; | ||
19 | }; | ||
20 | |||
21 | /* Reserving memory regions still pending */ | ||
22 | reserved_memory: reserved-memory { | ||
23 | #address-cells = <2>; | ||
24 | #size-cells = <2>; | ||
25 | ranges; | ||
26 | |||
27 | secure_ddr: optee@9e800000 { | ||
28 | reg = <0x00 0x9e800000 0x00 0x01800000>; | ||
29 | alignment = <0x1000>; | ||
30 | no-map; | ||
31 | }; | ||
32 | }; | ||
33 | |||
34 | transceiver0: can-phy0 { | ||
35 | /* standby pin has been grounded by default */ | ||
36 | compatible = "ti,tcan1042"; | ||
37 | #phy-cells = <0>; | ||
38 | max-bitrate = <5000000>; | ||
39 | }; | ||
40 | }; | ||
41 | |||
42 | &main_pmx0 { | ||
43 | main_i2c0_pins_default: main-i2c0-pins-default { | ||
44 | pinctrl-single,pins = < | ||
45 | J721S2_IOPAD(0x0e0, PIN_INPUT_PULLUP, 0) /* (AH25) I2C0_SCL */ | ||
46 | J721S2_IOPAD(0x0e4, PIN_INPUT_PULLUP, 0) /* (AE24) I2C0_SDA */ | ||
47 | >; | ||
48 | }; | ||
49 | |||
50 | main_mcan16_pins_default: main-mcan16-pins-default { | ||
51 | pinctrl-single,pins = < | ||
52 | J721S2_IOPAD(0x028, PIN_INPUT, 0) /* (AB24) MCAN16_RX */ | ||
53 | J721S2_IOPAD(0x024, PIN_OUTPUT, 0) /* (Y28) MCAN16_TX */ | ||
54 | >; | ||
55 | }; | ||
56 | }; | ||
57 | |||
58 | &main_i2c0 { | ||
59 | pinctrl-names = "default"; | ||
60 | pinctrl-0 = <&main_i2c0_pins_default>; | ||
61 | clock-frequency = <400000>; | ||
62 | |||
63 | exp_som: gpio@21 { | ||
64 | compatible = "ti,tca6408"; | ||
65 | reg = <0x21>; | ||
66 | gpio-controller; | ||
67 | #gpio-cells = <2>; | ||
68 | gpio-line-names = "USB2.0_MUX_SEL", "CANUART_MUX1_SEL0", | ||
69 | "CANUART_MUX2_SEL0", "CANUART_MUX_SEL1", | ||
70 | "GPIO_RGMII1_RST", "GPIO_eDP_ENABLE", | ||
71 | "GPIO_LIN_EN", "CAN_STB"; | ||
72 | }; | ||
73 | }; | ||
74 | |||
75 | &main_mcan16 { | ||
76 | pinctrl-0 = <&main_mcan16_pins_default>; | ||
77 | pinctrl-names = "default"; | ||
78 | phys = <&transceiver0>; | ||
79 | }; | ||
80 | |||
81 | &mailbox0_cluster0 { | ||
82 | status = "disabled"; | ||
83 | }; | ||
84 | |||
85 | &mailbox0_cluster1 { | ||
86 | status = "disabled"; | ||
87 | }; | ||
88 | |||
89 | &mailbox0_cluster2 { | ||
90 | status = "disabled"; | ||
91 | }; | ||
92 | |||
93 | &mailbox0_cluster3 { | ||
94 | status = "disabled"; | ||
95 | }; | ||
96 | |||
97 | &mailbox0_cluster4 { | ||
98 | status = "disabled"; | ||
99 | }; | ||
100 | |||
101 | &mailbox0_cluster5 { | ||
102 | status = "disabled"; | ||
103 | }; | ||
104 | |||
105 | &mailbox0_cluster6 { | ||
106 | status = "disabled"; | ||
107 | }; | ||
108 | |||
109 | &mailbox0_cluster7 { | ||
110 | status = "disabled"; | ||
111 | }; | ||
112 | |||
113 | &mailbox0_cluster8 { | ||
114 | status = "disabled"; | ||
115 | }; | ||
116 | |||
117 | &mailbox0_cluster9 { | ||
118 | status = "disabled"; | ||
119 | }; | ||
120 | |||
121 | &mailbox0_cluster10 { | ||
122 | status = "disabled"; | ||
123 | }; | ||
124 | |||
125 | &mailbox0_cluster11 { | ||
126 | status = "disabled"; | ||
127 | }; | ||
128 | |||
129 | &mailbox1_cluster0 { | ||
130 | status = "disabled"; | ||
131 | }; | ||
132 | |||
133 | &mailbox1_cluster1 { | ||
134 | status = "disabled"; | ||
135 | }; | ||
136 | |||
137 | &mailbox1_cluster2 { | ||
138 | status = "disabled"; | ||
139 | }; | ||
140 | |||
141 | &mailbox1_cluster3 { | ||
142 | status = "disabled"; | ||
143 | }; | ||
144 | |||
145 | &mailbox1_cluster4 { | ||
146 | status = "disabled"; | ||
147 | }; | ||
148 | |||
149 | &mailbox1_cluster5 { | ||
150 | status = "disabled"; | ||
151 | }; | ||
152 | |||
153 | &mailbox1_cluster6 { | ||
154 | status = "disabled"; | ||
155 | }; | ||
156 | |||
157 | &mailbox1_cluster7 { | ||
158 | status = "disabled"; | ||
159 | }; | ||
160 | |||
161 | &mailbox1_cluster8 { | ||
162 | status = "disabled"; | ||
163 | }; | ||
164 | |||
165 | &mailbox1_cluster9 { | ||
166 | status = "disabled"; | ||
167 | }; | ||
168 | |||
169 | &mailbox1_cluster10 { | ||
170 | status = "disabled"; | ||
171 | }; | ||
172 | |||
173 | &mailbox1_cluster11 { | ||
174 | status = "disabled"; | ||
175 | }; | ||
diff --git a/arch/arm64/boot/dts/ti/k3-j721s2.dtsi b/arch/arm64/boot/dts/ti/k3-j721s2.dtsi new file mode 100644 index 000000000000..d9f601bebe38 --- /dev/null +++ b/arch/arm64/boot/dts/ti/k3-j721s2.dtsi | |||
@@ -0,0 +1,189 @@ | |||
1 | // SPDX-License-Identifier: GPL-2.0 | ||
2 | /* | ||
3 | * Device Tree Source for J721S2 SoC Family | ||
4 | * | ||
5 | * TRM (SPRUJ28 – NOVEMBER 2021) : http://www.ti.com/lit/pdf/spruj28 | ||
6 | * | ||
7 | * Copyright (C) 2021 Texas Instruments Incorporated - https://www.ti.com/ | ||
8 | * | ||
9 | */ | ||
10 | |||
11 | #include <dt-bindings/interrupt-controller/irq.h> | ||
12 | #include <dt-bindings/interrupt-controller/arm-gic.h> | ||
13 | #include <dt-bindings/pinctrl/k3.h> | ||
14 | #include <dt-bindings/soc/ti,sci_pm_domain.h> | ||
15 | |||
16 | / { | ||
17 | |||
18 | model = "Texas Instruments K3 J721S2 SoC"; | ||
19 | compatible = "ti,j721s2"; | ||
20 | interrupt-parent = <&gic500>; | ||
21 | #address-cells = <2>; | ||
22 | #size-cells = <2>; | ||
23 | |||
24 | aliases { | ||
25 | serial0 = &wkup_uart0; | ||
26 | serial1 = &mcu_uart0; | ||
27 | serial2 = &main_uart0; | ||
28 | serial3 = &main_uart1; | ||
29 | serial4 = &main_uart2; | ||
30 | serial5 = &main_uart3; | ||
31 | serial6 = &main_uart4; | ||
32 | serial7 = &main_uart5; | ||
33 | serial8 = &main_uart6; | ||
34 | serial9 = &main_uart7; | ||
35 | serial10 = &main_uart8; | ||
36 | serial11 = &main_uart9; | ||
37 | mmc0 = &main_sdhci0; | ||
38 | mmc1 = &main_sdhci1; | ||
39 | can0 = &main_mcan16; | ||
40 | can1 = &mcu_mcan0; | ||
41 | can2 = &mcu_mcan1; | ||
42 | can3 = &main_mcan3; | ||
43 | can4 = &main_mcan5; | ||
44 | }; | ||
45 | |||
46 | chosen { }; | ||
47 | |||
48 | cpus { | ||
49 | #address-cells = <1>; | ||
50 | #size-cells = <0>; | ||
51 | cpu-map { | ||
52 | cluster0: cluster0 { | ||
53 | core0 { | ||
54 | cpu = <&cpu0>; | ||
55 | }; | ||
56 | |||
57 | core1 { | ||
58 | cpu = <&cpu1>; | ||
59 | }; | ||
60 | }; | ||
61 | }; | ||
62 | |||
63 | cpu0: cpu@0 { | ||
64 | compatible = "arm,cortex-a72"; | ||
65 | reg = <0x000>; | ||
66 | device_type = "cpu"; | ||
67 | enable-method = "psci"; | ||
68 | i-cache-size = <0xc000>; | ||
69 | i-cache-line-size = <64>; | ||
70 | i-cache-sets = <256>; | ||
71 | d-cache-size = <0x8000>; | ||
72 | d-cache-line-size = <64>; | ||
73 | d-cache-sets = <256>; | ||
74 | next-level-cache = <&L2_0>; | ||
75 | }; | ||
76 | |||
77 | cpu1: cpu@1 { | ||
78 | compatible = "arm,cortex-a72"; | ||
79 | reg = <0x001>; | ||
80 | device_type = "cpu"; | ||
81 | enable-method = "psci"; | ||
82 | i-cache-size = <0xc000>; | ||
83 | i-cache-line-size = <64>; | ||
84 | i-cache-sets = <256>; | ||
85 | d-cache-size = <0x8000>; | ||
86 | d-cache-line-size = <64>; | ||
87 | d-cache-sets = <256>; | ||
88 | next-level-cache = <&L2_0>; | ||
89 | }; | ||
90 | }; | ||
91 | |||
92 | L2_0: l2-cache0 { | ||
93 | compatible = "cache"; | ||
94 | cache-level = <2>; | ||
95 | cache-size = <0x100000>; | ||
96 | cache-line-size = <64>; | ||
97 | cache-sets = <1024>; | ||
98 | next-level-cache = <&msmc_l3>; | ||
99 | }; | ||
100 | |||
101 | msmc_l3: l3-cache0 { | ||
102 | compatible = "cache"; | ||
103 | cache-level = <3>; | ||
104 | }; | ||
105 | |||
106 | firmware { | ||
107 | optee { | ||
108 | compatible = "linaro,optee-tz"; | ||
109 | method = "smc"; | ||
110 | }; | ||
111 | |||
112 | psci: psci { | ||
113 | compatible = "arm,psci-1.0"; | ||
114 | method = "smc"; | ||
115 | }; | ||
116 | }; | ||
117 | |||
118 | a72_timer0: timer-cl0-cpu0 { | ||
119 | compatible = "arm,armv8-timer"; | ||
120 | interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, /* cntpsirq */ | ||
121 | <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, /* cntpnsirq */ | ||
122 | <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, /* cntvirq */ | ||
123 | <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; /* cnthpirq */ | ||
124 | |||
125 | }; | ||
126 | |||
127 | pmu: pmu { | ||
128 | compatible = "arm,cortex-a72-pmu"; | ||
129 | /* Recommendation from GIC500 TRM Table A.3 */ | ||
130 | interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>; | ||
131 | }; | ||
132 | |||
133 | cbass_main: bus@100000 { | ||
134 | compatible = "simple-bus"; | ||
135 | #address-cells = <2>; | ||
136 | #size-cells = <2>; | ||
137 | ranges = <0x00 0x00100000 0x00 0x00100000 0x00 0x00020000>, /* ctrl mmr */ | ||
138 | <0x00 0x00600000 0x00 0x00600000 0x00 0x00031100>, /* GPIO */ | ||
139 | <0x00 0x01000000 0x00 0x01000000 0x00 0x0d000000>, /* Most peripherals */ | ||
140 | <0x00 0x0d800000 0x00 0x0d800000 0x00 0x00800000>, /* PCIe Core*/ | ||
141 | <0x00 0x18000000 0x00 0x18000000 0x00 0x08000000>, /* PCIe1 DAT0 */ | ||
142 | <0x00 0x64800000 0x00 0x64800000 0x00 0x0070c000>, /* C71_1 */ | ||
143 | <0x00 0x65800000 0x00 0x65800000 0x00 0x0070c000>, /* C71_2 */ | ||
144 | <0x00 0x70000000 0x00 0x70000000 0x00 0x00400000>, /* MSMC RAM */ | ||
145 | <0x00 0x30000000 0x00 0x30000000 0x00 0x0c400000>, /* MAIN NAVSS */ | ||
146 | <0x41 0x00000000 0x41 0x00000000 0x01 0x00000000>, /* PCIe1 DAT1 */ | ||
147 | <0x4e 0x20000000 0x4e 0x20000000 0x00 0x00080000>, /* GPU */ | ||
148 | |||
149 | /* MCUSS_WKUP Range */ | ||
150 | <0x00 0x28380000 0x00 0x28380000 0x00 0x03880000>, | ||
151 | <0x00 0x40200000 0x00 0x40200000 0x00 0x00998400>, | ||
152 | <0x00 0x40f00000 0x00 0x40f00000 0x00 0x00020000>, | ||
153 | <0x00 0x41000000 0x00 0x41000000 0x00 0x00020000>, | ||
154 | <0x00 0x41400000 0x00 0x41400000 0x00 0x00020000>, | ||
155 | <0x00 0x41c00000 0x00 0x41c00000 0x00 0x00100000>, | ||
156 | <0x00 0x42040000 0x00 0x42040000 0x00 0x03ac2400>, | ||
157 | <0x00 0x45100000 0x00 0x45100000 0x00 0x00c24000>, | ||
158 | <0x00 0x46000000 0x00 0x46000000 0x00 0x00200000>, | ||
159 | <0x00 0x47000000 0x00 0x47000000 0x00 0x00068400>, | ||
160 | <0x00 0x50000000 0x00 0x50000000 0x00 0x10000000>, | ||
161 | <0x05 0x00000000 0x05 0x00000000 0x01 0x00000000>, | ||
162 | <0x07 0x00000000 0x07 0x00000000 0x01 0x00000000>; | ||
163 | |||
164 | cbass_mcu_wakeup: bus@28380000 { | ||
165 | compatible = "simple-bus"; | ||
166 | #address-cells = <2>; | ||
167 | #size-cells = <2>; | ||
168 | ranges = <0x00 0x28380000 0x00 0x28380000 0x00 0x03880000>, /* MCU NAVSS*/ | ||
169 | <0x00 0x40200000 0x00 0x40200000 0x00 0x00998400>, /* First peripheral window */ | ||
170 | <0x00 0x40f00000 0x00 0x40f00000 0x00 0x00020000>, /* CTRL_MMR0 */ | ||
171 | <0x00 0x41000000 0x00 0x41000000 0x00 0x00020000>, /* MCU R5F Core0 */ | ||
172 | <0x00 0x41400000 0x00 0x41400000 0x00 0x00020000>, /* MCU R5F Core1 */ | ||
173 | <0x00 0x41c00000 0x00 0x41c00000 0x00 0x00100000>, /* MCU SRAM */ | ||
174 | <0x00 0x42040000 0x00 0x42040000 0x00 0x03ac2400>, /* WKUP peripheral window */ | ||
175 | <0x00 0x45100000 0x00 0x45100000 0x00 0x00c24000>, /* MMRs, remaining NAVSS */ | ||
176 | <0x00 0x46000000 0x00 0x46000000 0x00 0x00200000>, /* CPSW */ | ||
177 | <0x00 0x47000000 0x00 0x47000000 0x00 0x00068400>, /* OSPI register space */ | ||
178 | <0x00 0x50000000 0x00 0x50000000 0x00 0x10000000>, /* FSS OSPI0/1 data region 0 */ | ||
179 | <0x05 0x00000000 0x05 0x00000000 0x01 0x00000000>, /* FSS OSPI0 data region 3 */ | ||
180 | <0x07 0x00000000 0x07 0x00000000 0x01 0x00000000>; /* FSS OSPI1 data region 3*/ | ||
181 | |||
182 | }; | ||
183 | |||
184 | }; | ||
185 | }; | ||
186 | |||
187 | /* Now include peripherals from each bus segment */ | ||
188 | #include "k3-j721s2-main.dtsi" | ||
189 | #include "k3-j721s2-mcu-wakeup.dtsi" | ||
diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig index 74146889dd07..c3d85c9a2591 100644 --- a/arch/arm64/configs/defconfig +++ b/arch/arm64/configs/defconfig | |||
@@ -395,6 +395,8 @@ CONFIG_SERIAL_8250_SHARE_IRQ=y | |||
395 | CONFIG_SERIAL_8250_BCM2835AUX=y | 395 | CONFIG_SERIAL_8250_BCM2835AUX=y |
396 | CONFIG_SERIAL_8250_DW=y | 396 | CONFIG_SERIAL_8250_DW=y |
397 | CONFIG_SERIAL_8250_OMAP=y | 397 | CONFIG_SERIAL_8250_OMAP=y |
398 | CONFIG_SERIAL_8250_NR_UARTS=16 | ||
399 | CONFIG_SERIAL_8250_RUNTIME_UARTS=16 | ||
398 | CONFIG_SERIAL_8250_MT6577=y | 400 | CONFIG_SERIAL_8250_MT6577=y |
399 | CONFIG_SERIAL_8250_UNIPHIER=y | 401 | CONFIG_SERIAL_8250_UNIPHIER=y |
400 | CONFIG_SERIAL_OF_PLATFORM=y | 402 | CONFIG_SERIAL_OF_PLATFORM=y |
diff --git a/drivers/dma/ti/Makefile b/drivers/dma/ti/Makefile index bd496efadff7..1d4081a049b7 100644 --- a/drivers/dma/ti/Makefile +++ b/drivers/dma/ti/Makefile | |||
@@ -8,5 +8,6 @@ obj-$(CONFIG_TI_K3_PSIL) += k3-psil.o \ | |||
8 | k3-psil-am654.o \ | 8 | k3-psil-am654.o \ |
9 | k3-psil-j721e.o \ | 9 | k3-psil-j721e.o \ |
10 | k3-psil-j7200.o \ | 10 | k3-psil-j7200.o \ |
11 | k3-psil-am64.o | 11 | k3-psil-am64.o \ |
12 | k3-psil-j721s2.o | ||
12 | obj-$(CONFIG_TI_DMA_CROSSBAR) += dma-crossbar.o | 13 | obj-$(CONFIG_TI_DMA_CROSSBAR) += dma-crossbar.o |
diff --git a/drivers/dma/ti/k3-psil-j721s2.c b/drivers/dma/ti/k3-psil-j721s2.c new file mode 100644 index 000000000000..4c4172a4d271 --- /dev/null +++ b/drivers/dma/ti/k3-psil-j721s2.c | |||
@@ -0,0 +1,167 @@ | |||
1 | // SPDX-License-Identifier: GPL-2.0 | ||
2 | /* | ||
3 | * Copyright (C) 2021 Texas Instruments Incorporated - https://www.ti.com | ||
4 | */ | ||
5 | |||
6 | #include <linux/kernel.h> | ||
7 | |||
8 | #include "k3-psil-priv.h" | ||
9 | |||
10 | #define PSIL_PDMA_XY_TR(x) \ | ||
11 | { \ | ||
12 | .thread_id = x, \ | ||
13 | .ep_config = { \ | ||
14 | .ep_type = PSIL_EP_PDMA_XY, \ | ||
15 | }, \ | ||
16 | } | ||
17 | |||
18 | #define PSIL_PDMA_XY_PKT(x) \ | ||
19 | { \ | ||
20 | .thread_id = x, \ | ||
21 | .ep_config = { \ | ||
22 | .ep_type = PSIL_EP_PDMA_XY, \ | ||
23 | .pkt_mode = 1, \ | ||
24 | }, \ | ||
25 | } | ||
26 | |||
27 | #define PSIL_PDMA_MCASP(x) \ | ||
28 | { \ | ||
29 | .thread_id = x, \ | ||
30 | .ep_config = { \ | ||
31 | .ep_type = PSIL_EP_PDMA_XY, \ | ||
32 | .pdma_acc32 = 1, \ | ||
33 | .pdma_burst = 1, \ | ||
34 | }, \ | ||
35 | } | ||
36 | |||
37 | #define PSIL_ETHERNET(x) \ | ||
38 | { \ | ||
39 | .thread_id = x, \ | ||
40 | .ep_config = { \ | ||
41 | .ep_type = PSIL_EP_NATIVE, \ | ||
42 | .pkt_mode = 1, \ | ||
43 | .needs_epib = 1, \ | ||
44 | .psd_size = 16, \ | ||
45 | }, \ | ||
46 | } | ||
47 | |||
48 | #define PSIL_SA2UL(x, tx) \ | ||
49 | { \ | ||
50 | .thread_id = x, \ | ||
51 | .ep_config = { \ | ||
52 | .ep_type = PSIL_EP_NATIVE, \ | ||
53 | .pkt_mode = 1, \ | ||
54 | .needs_epib = 1, \ | ||
55 | .psd_size = 64, \ | ||
56 | .notdpkt = tx, \ | ||
57 | }, \ | ||
58 | } | ||
59 | |||
60 | /* PSI-L source thread IDs, used for RX (DMA_DEV_TO_MEM) */ | ||
61 | static struct psil_ep j721s2_src_ep_map[] = { | ||
62 | /* PDMA_MCASP - McASP0-4 */ | ||
63 | PSIL_PDMA_MCASP(0x4400), | ||
64 | PSIL_PDMA_MCASP(0x4401), | ||
65 | PSIL_PDMA_MCASP(0x4402), | ||
66 | PSIL_PDMA_MCASP(0x4403), | ||
67 | PSIL_PDMA_MCASP(0x4404), | ||
68 | /* PDMA_SPI_G0 - SPI0-3 */ | ||
69 | PSIL_PDMA_XY_PKT(0x4600), | ||
70 | PSIL_PDMA_XY_PKT(0x4601), | ||
71 | PSIL_PDMA_XY_PKT(0x4602), | ||
72 | PSIL_PDMA_XY_PKT(0x4603), | ||
73 | PSIL_PDMA_XY_PKT(0x4604), | ||
74 | PSIL_PDMA_XY_PKT(0x4605), | ||
75 | PSIL_PDMA_XY_PKT(0x4606), | ||
76 | PSIL_PDMA_XY_PKT(0x4607), | ||
77 | PSIL_PDMA_XY_PKT(0x4608), | ||
78 | PSIL_PDMA_XY_PKT(0x4609), | ||
79 | PSIL_PDMA_XY_PKT(0x460a), | ||
80 | PSIL_PDMA_XY_PKT(0x460b), | ||
81 | PSIL_PDMA_XY_PKT(0x460c), | ||
82 | PSIL_PDMA_XY_PKT(0x460d), | ||
83 | PSIL_PDMA_XY_PKT(0x460e), | ||
84 | PSIL_PDMA_XY_PKT(0x460f), | ||
85 | /* PDMA_SPI_G1 - SPI4-7 */ | ||
86 | PSIL_PDMA_XY_PKT(0x4610), | ||
87 | PSIL_PDMA_XY_PKT(0x4611), | ||
88 | PSIL_PDMA_XY_PKT(0x4612), | ||
89 | PSIL_PDMA_XY_PKT(0x4613), | ||
90 | PSIL_PDMA_XY_PKT(0x4614), | ||
91 | PSIL_PDMA_XY_PKT(0x4615), | ||
92 | PSIL_PDMA_XY_PKT(0x4616), | ||
93 | PSIL_PDMA_XY_PKT(0x4617), | ||
94 | PSIL_PDMA_XY_PKT(0x4618), | ||
95 | PSIL_PDMA_XY_PKT(0x4619), | ||
96 | PSIL_PDMA_XY_PKT(0x461a), | ||
97 | PSIL_PDMA_XY_PKT(0x461b), | ||
98 | PSIL_PDMA_XY_PKT(0x461c), | ||
99 | PSIL_PDMA_XY_PKT(0x461d), | ||
100 | PSIL_PDMA_XY_PKT(0x461e), | ||
101 | PSIL_PDMA_XY_PKT(0x461f), | ||
102 | /* PDMA_USART_G0 - UART0-1 */ | ||
103 | PSIL_PDMA_XY_PKT(0x4700), | ||
104 | PSIL_PDMA_XY_PKT(0x4701), | ||
105 | /* PDMA_USART_G1 - UART2-3 */ | ||
106 | PSIL_PDMA_XY_PKT(0x4702), | ||
107 | PSIL_PDMA_XY_PKT(0x4703), | ||
108 | /* PDMA_USART_G2 - UART4-9 */ | ||
109 | PSIL_PDMA_XY_PKT(0x4704), | ||
110 | PSIL_PDMA_XY_PKT(0x4705), | ||
111 | PSIL_PDMA_XY_PKT(0x4706), | ||
112 | PSIL_PDMA_XY_PKT(0x4707), | ||
113 | PSIL_PDMA_XY_PKT(0x4708), | ||
114 | PSIL_PDMA_XY_PKT(0x4709), | ||
115 | /* CPSW0 */ | ||
116 | PSIL_ETHERNET(0x7000), | ||
117 | /* MCU_PDMA0 (MCU_PDMA_MISC_G0) - SPI0 */ | ||
118 | PSIL_PDMA_XY_PKT(0x7100), | ||
119 | PSIL_PDMA_XY_PKT(0x7101), | ||
120 | PSIL_PDMA_XY_PKT(0x7102), | ||
121 | PSIL_PDMA_XY_PKT(0x7103), | ||
122 | /* MCU_PDMA1 (MCU_PDMA_MISC_G1) - SPI1-2 */ | ||
123 | PSIL_PDMA_XY_PKT(0x7200), | ||
124 | PSIL_PDMA_XY_PKT(0x7201), | ||
125 | PSIL_PDMA_XY_PKT(0x7202), | ||
126 | PSIL_PDMA_XY_PKT(0x7203), | ||
127 | PSIL_PDMA_XY_PKT(0x7204), | ||
128 | PSIL_PDMA_XY_PKT(0x7205), | ||
129 | PSIL_PDMA_XY_PKT(0x7206), | ||
130 | PSIL_PDMA_XY_PKT(0x7207), | ||
131 | /* MCU_PDMA2 (MCU_PDMA_MISC_G2) - UART0 */ | ||
132 | PSIL_PDMA_XY_PKT(0x7300), | ||
133 | /* MCU_PDMA_ADC - ADC0-1 */ | ||
134 | PSIL_PDMA_XY_TR(0x7400), | ||
135 | PSIL_PDMA_XY_TR(0x7401), | ||
136 | PSIL_PDMA_XY_TR(0x7402), | ||
137 | PSIL_PDMA_XY_TR(0x7403), | ||
138 | /* SA2UL */ | ||
139 | PSIL_SA2UL(0x7500, 0), | ||
140 | PSIL_SA2UL(0x7501, 0), | ||
141 | PSIL_SA2UL(0x7502, 0), | ||
142 | PSIL_SA2UL(0x7503, 0), | ||
143 | }; | ||
144 | |||
145 | /* PSI-L destination thread IDs, used for TX (DMA_MEM_TO_DEV) */ | ||
146 | static struct psil_ep j721s2_dst_ep_map[] = { | ||
147 | /* CPSW0 */ | ||
148 | PSIL_ETHERNET(0xf000), | ||
149 | PSIL_ETHERNET(0xf001), | ||
150 | PSIL_ETHERNET(0xf002), | ||
151 | PSIL_ETHERNET(0xf003), | ||
152 | PSIL_ETHERNET(0xf004), | ||
153 | PSIL_ETHERNET(0xf005), | ||
154 | PSIL_ETHERNET(0xf006), | ||
155 | PSIL_ETHERNET(0xf007), | ||
156 | /* SA2UL */ | ||
157 | PSIL_SA2UL(0xf500, 1), | ||
158 | PSIL_SA2UL(0xf501, 1), | ||
159 | }; | ||
160 | |||
161 | struct psil_ep_map j721s2_ep_map = { | ||
162 | .name = "j721s2", | ||
163 | .src = j721s2_src_ep_map, | ||
164 | .src_count = ARRAY_SIZE(j721s2_src_ep_map), | ||
165 | .dst = j721s2_dst_ep_map, | ||
166 | .dst_count = ARRAY_SIZE(j721s2_dst_ep_map), | ||
167 | }; | ||
diff --git a/drivers/dma/ti/k3-psil-priv.h b/drivers/dma/ti/k3-psil-priv.h index b74e192e3c2d..e51e179cdb56 100644 --- a/drivers/dma/ti/k3-psil-priv.h +++ b/drivers/dma/ti/k3-psil-priv.h | |||
@@ -41,5 +41,6 @@ extern struct psil_ep_map am654_ep_map; | |||
41 | extern struct psil_ep_map j721e_ep_map; | 41 | extern struct psil_ep_map j721e_ep_map; |
42 | extern struct psil_ep_map j7200_ep_map; | 42 | extern struct psil_ep_map j7200_ep_map; |
43 | extern struct psil_ep_map am64_ep_map; | 43 | extern struct psil_ep_map am64_ep_map; |
44 | extern struct psil_ep_map j721s2_ep_map; | ||
44 | 45 | ||
45 | #endif /* K3_PSIL_PRIV_H_ */ | 46 | #endif /* K3_PSIL_PRIV_H_ */ |
diff --git a/drivers/dma/ti/k3-psil.c b/drivers/dma/ti/k3-psil.c index 13ce7367d870..8867b4bd0c51 100644 --- a/drivers/dma/ti/k3-psil.c +++ b/drivers/dma/ti/k3-psil.c | |||
@@ -21,6 +21,7 @@ static const struct soc_device_attribute k3_soc_devices[] = { | |||
21 | { .family = "J721E", .data = &j721e_ep_map }, | 21 | { .family = "J721E", .data = &j721e_ep_map }, |
22 | { .family = "J7200", .data = &j7200_ep_map }, | 22 | { .family = "J7200", .data = &j7200_ep_map }, |
23 | { .family = "AM64X", .data = &am64_ep_map }, | 23 | { .family = "AM64X", .data = &am64_ep_map }, |
24 | { .family = "J721S2", .data = &j721s2_ep_map }, | ||
24 | { /* sentinel */ } | 25 | { /* sentinel */ } |
25 | }; | 26 | }; |
26 | 27 | ||
diff --git a/drivers/dma/ti/k3-udma.c b/drivers/dma/ti/k3-udma.c index ff59ba1b9505..d20572020e86 100644 --- a/drivers/dma/ti/k3-udma.c +++ b/drivers/dma/ti/k3-udma.c | |||
@@ -4375,6 +4375,7 @@ static const struct soc_device_attribute k3_soc_devices[] = { | |||
4375 | { .family = "J721E", .data = &j721e_soc_data }, | 4375 | { .family = "J721E", .data = &j721e_soc_data }, |
4376 | { .family = "J7200", .data = &j7200_soc_data }, | 4376 | { .family = "J7200", .data = &j7200_soc_data }, |
4377 | { .family = "AM64X", .data = &am64_soc_data }, | 4377 | { .family = "AM64X", .data = &am64_soc_data }, |
4378 | { .family = "J721S2", .data = &j721e_soc_data}, | ||
4378 | { /* sentinel */ } | 4379 | { /* sentinel */ } |
4379 | }; | 4380 | }; |
4380 | 4381 | ||
diff --git a/drivers/phy/phy-can-transceiver.c b/drivers/phy/phy-can-transceiver.c index c2cb93b4df71..6f3fe37dee0e 100644 --- a/drivers/phy/phy-can-transceiver.c +++ b/drivers/phy/phy-can-transceiver.c | |||
@@ -110,14 +110,14 @@ static int can_transceiver_phy_probe(struct platform_device *pdev) | |||
110 | can_transceiver_phy->generic_phy = phy; | 110 | can_transceiver_phy->generic_phy = phy; |
111 | 111 | ||
112 | if (drvdata->flags & CAN_TRANSCEIVER_STB_PRESENT) { | 112 | if (drvdata->flags & CAN_TRANSCEIVER_STB_PRESENT) { |
113 | standby_gpio = devm_gpiod_get(dev, "standby", GPIOD_OUT_HIGH); | 113 | standby_gpio = devm_gpiod_get_optional(dev, "standby", GPIOD_OUT_HIGH); |
114 | if (IS_ERR(standby_gpio)) | 114 | if (IS_ERR(standby_gpio)) |
115 | return PTR_ERR(standby_gpio); | 115 | return PTR_ERR(standby_gpio); |
116 | can_transceiver_phy->standby_gpio = standby_gpio; | 116 | can_transceiver_phy->standby_gpio = standby_gpio; |
117 | } | 117 | } |
118 | 118 | ||
119 | if (drvdata->flags & CAN_TRANSCEIVER_EN_PRESENT) { | 119 | if (drvdata->flags & CAN_TRANSCEIVER_EN_PRESENT) { |
120 | enable_gpio = devm_gpiod_get(dev, "enable", GPIOD_OUT_LOW); | 120 | enable_gpio = devm_gpiod_get_optional(dev, "enable", GPIOD_OUT_LOW); |
121 | if (IS_ERR(enable_gpio)) | 121 | if (IS_ERR(enable_gpio)) |
122 | return PTR_ERR(enable_gpio); | 122 | return PTR_ERR(enable_gpio); |
123 | can_transceiver_phy->enable_gpio = enable_gpio; | 123 | can_transceiver_phy->enable_gpio = enable_gpio; |
diff --git a/drivers/soc/ti/k3-socinfo.c b/drivers/soc/ti/k3-socinfo.c index fd91129de6e5..b6b2150aca4e 100644 --- a/drivers/soc/ti/k3-socinfo.c +++ b/drivers/soc/ti/k3-socinfo.c | |||
@@ -40,7 +40,8 @@ static const struct k3_soc_id { | |||
40 | { 0xBB5A, "AM65X" }, | 40 | { 0xBB5A, "AM65X" }, |
41 | { 0xBB64, "J721E" }, | 41 | { 0xBB64, "J721E" }, |
42 | { 0xBB6D, "J7200" }, | 42 | { 0xBB6D, "J7200" }, |
43 | { 0xBB38, "AM64X" } | 43 | { 0xBB38, "AM64X" }, |
44 | { 0xBB75, "J721S2"}, | ||
44 | }; | 45 | }; |
45 | 46 | ||
46 | static int | 47 | static int |
diff --git a/include/dt-bindings/mux/ti-serdes.h b/include/dt-bindings/mux/ti-serdes.h index d417b9268b16..d3116c52ab72 100644 --- a/include/dt-bindings/mux/ti-serdes.h +++ b/include/dt-bindings/mux/ti-serdes.h | |||
@@ -95,4 +95,26 @@ | |||
95 | #define AM64_SERDES0_LANE0_PCIE0 0x0 | 95 | #define AM64_SERDES0_LANE0_PCIE0 0x0 |
96 | #define AM64_SERDES0_LANE0_USB 0x1 | 96 | #define AM64_SERDES0_LANE0_USB 0x1 |
97 | 97 | ||
98 | /* J721S2 */ | ||
99 | |||
100 | #define J721S2_SERDES0_LANE0_EDP_LANE0 0x0 | ||
101 | #define J721S2_SERDES0_LANE0_PCIE1_LANE0 0x1 | ||
102 | #define J721S2_SERDES0_LANE0_IP3_UNUSED 0x2 | ||
103 | #define J721S2_SERDES0_LANE0_IP4_UNUSED 0x3 | ||
104 | |||
105 | #define J721S2_SERDES0_LANE1_EDP_LANE1 0x0 | ||
106 | #define J721S2_SERDES0_LANE1_PCIE1_LANE1 0x1 | ||
107 | #define J721S2_SERDES0_LANE1_USB 0x2 | ||
108 | #define J721S2_SERDES0_LANE1_IP4_UNUSED 0x3 | ||
109 | |||
110 | #define J721S2_SERDES0_LANE2_EDP_LANE2 0x0 | ||
111 | #define J721S2_SERDES0_LANE2_PCIE1_LANE2 0x1 | ||
112 | #define J721S2_SERDES0_LANE2_IP3_UNUSED 0x2 | ||
113 | #define J721S2_SERDES0_LANE2_IP4_UNUSED 0x3 | ||
114 | |||
115 | #define J721S2_SERDES0_LANE3_EDP_LANE3 0x0 | ||
116 | #define J721S2_SERDES0_LANE3_PCIE1_LANE3 0x1 | ||
117 | #define J721S2_SERDES0_LANE3_USB 0x2 | ||
118 | #define J721S2_SERDES0_LANE3_IP4_UNUSED 0x3 | ||
119 | |||
98 | #endif /* _DT_BINDINGS_MUX_TI_SERDES */ | 120 | #endif /* _DT_BINDINGS_MUX_TI_SERDES */ |
diff --git a/include/dt-bindings/pinctrl/k3.h b/include/dt-bindings/pinctrl/k3.h index e085f102b283..63e038e36ca3 100644 --- a/include/dt-bindings/pinctrl/k3.h +++ b/include/dt-bindings/pinctrl/k3.h | |||
@@ -38,4 +38,7 @@ | |||
38 | #define AM64X_IOPAD(pa, val, muxmode) (((pa) & 0x1fff)) ((val) | (muxmode)) | 38 | #define AM64X_IOPAD(pa, val, muxmode) (((pa) & 0x1fff)) ((val) | (muxmode)) |
39 | #define AM64X_MCU_IOPAD(pa, val, muxmode) (((pa) & 0x1fff)) ((val) | (muxmode)) | 39 | #define AM64X_MCU_IOPAD(pa, val, muxmode) (((pa) & 0x1fff)) ((val) | (muxmode)) |
40 | 40 | ||
41 | #define J721S2_IOPAD(pa, val, muxmode) (((pa) & 0x1fff)) ((val) | (muxmode)) | ||
42 | #define J721S2_WKUP_IOPAD(pa, val, muxmode) (((pa) & 0x1fff)) ((val) | (muxmode)) | ||
43 | |||
41 | #endif | 44 | #endif |
diff --git a/ti_config_fragments/v8_baseport.cfg b/ti_config_fragments/v8_baseport.cfg index 053d30a209ec..412a6275b1a9 100644 --- a/ti_config_fragments/v8_baseport.cfg +++ b/ti_config_fragments/v8_baseport.cfg | |||
@@ -10,8 +10,8 @@ CONFIG_ARM64_VA_BITS=48 | |||
10 | 10 | ||
11 | # Serial | 11 | # Serial |
12 | CONFIG_SERIAL_8250_OMAP=y | 12 | CONFIG_SERIAL_8250_OMAP=y |
13 | CONFIG_SERIAL_8250_NR_UARTS=10 | 13 | CONFIG_SERIAL_8250_NR_UARTS=16 |
14 | CONFIG_SERIAL_8250_RUNTIME_UARTS=10 | 14 | CONFIG_SERIAL_8250_RUNTIME_UARTS=16 |
15 | 15 | ||
16 | # K3 Power config options | 16 | # K3 Power config options |
17 | CONFIG_MAILBOX=y | 17 | CONFIG_MAILBOX=y |