dmaengine: ti: k3-udma: Fix teardown for cyclic RX with PDMA

When receiving data in cyclic mode from PDMA peripherals, where reload
count is set to infinite, any TR in the set can potentially be the last
one of the overall transfer. In such cases, the EOP flag needs to be set
in each TR and PDMA's Static TR "Z" parameter should be set, matching
the size of the TR.

This is required for the teardown to function properly and cleanup the
internal state memory. This only affects platforms using BCDMA and not
those using UDMA-P, which could set EOP flag in the teardown TR
automatically.

Signed-off-by: Jai Luthra <j-luthra@ti.com>
Reviewed-by: Kamlesh Gurudasani <kamlesh@ti.com>

1 files changed, 35 insertions, 23 deletions

diff --git a/drivers/dma/ti/k3-udma.c b/drivers/dma/ti/k3-udma.c
index 468e5b86eecb..bd590a8ff55d 100644
--- a/drivers/dma/ti/k3-udma.c
+++ b/drivers/dma/ti/k3-udma.c
@@ -1016,14 +1016,9 @@ static int udma_stop(struct udma_chan *uc)
                 if (!uc->cyclic && !uc->desc)
                         udma_push_to_ring(uc, -1);
 
-                /* FIXME: Doing a forced teardown for McASP PDMA to prevent channel corruption */
-                if (uc->cyclic && uc->config.ep_type == PSIL_EP_PDMA_XY &&
-                    uc->config.enable_acc32 && uc->config.enable_burst)
-                        udma_rchanrt_write(uc, UDMA_CHAN_RT_PEER_RT_EN_REG, 0);
-                else
-                        udma_rchanrt_write(uc, UDMA_CHAN_RT_PEER_RT_EN_REG,
-                                           UDMA_PEER_RT_EN_ENABLE |
-                                           UDMA_PEER_RT_EN_TEARDOWN);
+                udma_rchanrt_write(uc, UDMA_CHAN_RT_PEER_RT_EN_REG,
+                                   UDMA_PEER_RT_EN_ENABLE |
+                                   UDMA_PEER_RT_EN_TEARDOWN);
                 break;
         case DMA_MEM_TO_DEV:
                 udma_tchanrt_write(uc, UDMA_CHAN_RT_PEER_RT_EN_REG,
@@ -3200,27 +3195,39 @@ static int udma_configure_statictr(struct udma_chan *uc, struct udma_desc *d,
 
         d->static_tr.elcnt = elcnt;
 
-        /*
-         * PDMA must to close the packet when the channel is in packet mode.
-         * For TR mode when the channel is not cyclic we also need PDMA to close
-         * the packet otherwise the transfer will stall because PDMA holds on
-         * the data it has received from the peripheral.
-         */
         if (uc->config.pkt_mode || !uc->cyclic) {
+                /*
+                 * PDMA must close the packet when the channel is in packet mode.
+                 * For TR mode when the channel is not cyclic we also need PDMA
+                 * to close the packet otherwise the transfer will stall because
+                 * PDMA holds on the data it has received from the peripheral.
+                 */
                 unsigned int div = dev_width * elcnt;
 
                 if (uc->cyclic)
                         d->static_tr.bstcnt = d->residue / d->sglen / div;
                 else
                         d->static_tr.bstcnt = d->residue / div;
+        } else if (uc->ud->match_data->type == DMA_TYPE_BCDMA &&
+                   uc->config.dir == DMA_DEV_TO_MEM && !uc->config.pkt_mode &&
+                   uc->cyclic) {
+                /*
+                 * For cyclic TR mode PDMA must close the packet after every TR
+                 * transfer, as we have to set EOP in each TR to prevent short
+                 * packet errors seen on channel teardown.
+                 */
+                struct cppi5_tr_type1_t *tr_req = d->hwdesc[0].tr_req_base;
 
-                if (uc->config.dir == DMA_DEV_TO_MEM &&
-                    d->static_tr.bstcnt > uc->ud->match_data->statictr_z_mask)
-                        return -EINVAL;
+                d->static_tr.bstcnt =
+                        (tr_req->icnt0 * tr_req->icnt1) / dev_width;
         } else {
                 d->static_tr.bstcnt = 0;
         }
 
+        if (uc->config.dir == DMA_DEV_TO_MEM &&
+            d->static_tr.bstcnt > uc->ud->match_data->statictr_z_mask)
+                return -EINVAL;
+
         return 0;
 }
 
@@ -3465,8 +3472,9 @@ udma_prep_slave_sg(struct dma_chan *chan, struct scatterlist *sgl,
         /* static TR for remote PDMA */
         if (udma_configure_statictr(uc, d, dev_width, burst)) {
                 dev_err(uc->ud->dev,
-                        "%s: StaticTR Z is limited to maximum 4095 (%u)\n",
-                        __func__, d->static_tr.bstcnt);
+                        "%s: StaticTR Z is limited to maximum %u (%u)\n",
+                        __func__, uc->ud->match_data->statictr_z_mask,
+                        d->static_tr.bstcnt);
 
                 udma_free_hwdesc(uc, d);
                 kfree(d);
@@ -3541,8 +3549,11 @@ udma_prep_dma_cyclic_tr(struct udma_chan *uc, dma_addr_t buf_addr,
 
                 if (!(flags & DMA_PREP_INTERRUPT))
                         cppi5_tr_csf_set(&tr_req[tr_idx].flags,
-                                         CPPI5_TR_CSF_SUPR_EVT);
-
+                                         CPPI5_TR_CSF_SUPR_EVT |
+                                                 CPPI5_TR_CSF_EOP);
+                else
+                        cppi5_tr_csf_set(&tr_req[tr_idx].flags,
+                                         CPPI5_TR_CSF_EOP);
                 period_addr += period_len;
         }
 
@@ -3670,8 +3681,9 @@ udma_prep_dma_cyclic(struct dma_chan *chan, dma_addr_t buf_addr, size_t buf_len,
         /* static TR for remote PDMA */
         if (udma_configure_statictr(uc, d, dev_width, burst)) {
                 dev_err(uc->ud->dev,
-                        "%s: StaticTR Z is limited to maximum 4095 (%u)\n",
-                        __func__, d->static_tr.bstcnt);
+                        "%s: StaticTR Z is limited to maximum %u (%u)\n",
+                        __func__, uc->ud->match_data->statictr_z_mask,
+                        d->static_tr.bstcnt);
 
                 udma_free_hwdesc(uc, d);
                 kfree(d);