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authorJai Luthra2024-05-30 06:31:05 -0500
committerUdit Kumar2024-05-31 05:52:54 -0500
commitf08ebde41b3053f02de99e994a2b49dfcb494085 (patch)
treed44b9e76efa15f3677fcf745990e225534dc89ee
parent929fa0c11b912fc594eaada342579cf56fef4d1c (diff)
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ASoC: ti: davinci-mcasp: Set min period size using FIFO config
The minimum period size was enforced to 64 as older devices integrating McASP with EDMA used an internal FIFO of 64 samples. With UDMA based platforms this internal McASP FIFO is optional, as the DMA engine internally does some buffering which is already accounted for when registering the platform. So we should read the actual FIFO configuration (txnumevt/rxnumevt) instead of hardcoding frames.min to 64. Signed-off-by: Jai Luthra <j-luthra@ti.com>
-rw-r--r--sound/soc/ti/davinci-mcasp.c9
1 files changed, 7 insertions, 2 deletions
diff --git a/sound/soc/ti/davinci-mcasp.c b/sound/soc/ti/davinci-mcasp.c
index 7e7d665a5504..9090f3d3d981 100644
--- a/sound/soc/ti/davinci-mcasp.c
+++ b/sound/soc/ti/davinci-mcasp.c
@@ -72,6 +72,7 @@ struct davinci_mcasp_context {
72struct davinci_mcasp_ruledata { 72struct davinci_mcasp_ruledata {
73 struct davinci_mcasp *mcasp; 73 struct davinci_mcasp *mcasp;
74 int serializers; 74 int serializers;
75 u8 numevt;
75}; 76};
76 77
77struct davinci_mcasp { 78struct davinci_mcasp {
@@ -1472,12 +1473,13 @@ static int davinci_mcasp_hw_rule_format(struct snd_pcm_hw_params *params,
1472static int davinci_mcasp_hw_rule_min_periodsize( 1473static int davinci_mcasp_hw_rule_min_periodsize(
1473 struct snd_pcm_hw_params *params, struct snd_pcm_hw_rule *rule) 1474 struct snd_pcm_hw_params *params, struct snd_pcm_hw_rule *rule)
1474{ 1475{
1476 struct davinci_mcasp_ruledata *rd = rule->private;
1475 struct snd_interval *period_size = hw_param_interval(params, 1477 struct snd_interval *period_size = hw_param_interval(params,
1476 SNDRV_PCM_HW_PARAM_PERIOD_SIZE); 1478 SNDRV_PCM_HW_PARAM_PERIOD_SIZE);
1477 struct snd_interval frames; 1479 struct snd_interval frames;
1478 1480
1479 snd_interval_any(&frames); 1481 snd_interval_any(&frames);
1480 frames.min = 64; 1482 frames.min = rd->numevt;
1481 frames.integer = 1; 1483 frames.integer = 1;
1482 1484
1483 return snd_interval_refine(period_size, &frames); 1485 return snd_interval_refine(period_size, &frames);
@@ -1518,6 +1520,9 @@ static int davinci_mcasp_startup(struct snd_pcm_substream *substream,
1518 if (mcasp->serial_dir[i] == dir) 1520 if (mcasp->serial_dir[i] == dir)
1519 max_channels++; 1521 max_channels++;
1520 } 1522 }
1523 ruledata->numevt = (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) ?
1524 mcasp->txnumevt :
1525 mcasp->rxnumevt;
1521 ruledata->serializers = max_channels; 1526 ruledata->serializers = max_channels;
1522 ruledata->mcasp = mcasp; 1527 ruledata->mcasp = mcasp;
1523 max_channels *= tdm_slots; 1528 max_channels *= tdm_slots;
@@ -1593,7 +1598,7 @@ static int davinci_mcasp_startup(struct snd_pcm_substream *substream,
1593 1598
1594 snd_pcm_hw_rule_add(substream->runtime, 0, 1599 snd_pcm_hw_rule_add(substream->runtime, 0,
1595 SNDRV_PCM_HW_PARAM_PERIOD_SIZE, 1600 SNDRV_PCM_HW_PARAM_PERIOD_SIZE,
1596 davinci_mcasp_hw_rule_min_periodsize, NULL, 1601 davinci_mcasp_hw_rule_min_periodsize, ruledata,
1597 SNDRV_PCM_HW_PARAM_PERIOD_SIZE, -1); 1602 SNDRV_PCM_HW_PARAM_PERIOD_SIZE, -1);
1598 1603
1599 return 0; 1604 return 0;