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authorDaniel Mack2013-06-24 09:31:30 -0500
committerMark Brown2013-06-25 04:32:08 -0500
commit2352d4bf43b105ec2da5f43211db4a4c9bf34d4e (patch)
tree71c6740303824f89611a11a918dd9ce16144213a /Documentation/devicetree/bindings/sound/adi,adau1701.txt
parentde9fc724daaf5ceaf0af6ef23b2b3b1d933273e3 (diff)
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ASoC: adau1701: allow configuration of PLL mode pins
The ADAU1701 has 2 hardware pins to configure the PLL mode in accordance to the MCLK-to-LRCLK ratio. These pins have to be stable before the chip is released from reset, and a full reset cycle, including a new firmware download is needed whenever they change. This patch adds GPIO properties to the DT bindings of the Codec, and implements makes the set_sysclk memorize the configured sysclk. Because the run-time parameters are unknown at probe time, the first firmware download is postponed to the first hw_params call, when the driver can determine the mclk/lrclk divider. Subsequent downloads are only issued when the divider configuration changes. Signed-off-by: Daniel Mack <zonque@gmail.com> Acked-by: Lars-Peter Clausen <lars@metafoo.de> Signed-off-by: Mark Brown <broonie@linaro.org>
Diffstat (limited to 'Documentation/devicetree/bindings/sound/adi,adau1701.txt')
-rw-r--r--Documentation/devicetree/bindings/sound/adi,adau1701.txt6
1 files changed, 6 insertions, 0 deletions
diff --git a/Documentation/devicetree/bindings/sound/adi,adau1701.txt b/Documentation/devicetree/bindings/sound/adi,adau1701.txt
index 3afeda77b5b9..a9fbed1be40e 100644
--- a/Documentation/devicetree/bindings/sound/adi,adau1701.txt
+++ b/Documentation/devicetree/bindings/sound/adi,adau1701.txt
@@ -11,6 +11,11 @@ Optional properties:
11 - reset-gpio: A GPIO spec to define which pin is connected to the 11 - reset-gpio: A GPIO spec to define which pin is connected to the
12 chip's !RESET pin. If specified, the driver will 12 chip's !RESET pin. If specified, the driver will
13 assert a hardware reset at probe time. 13 assert a hardware reset at probe time.
14 - adi,pll-mode-gpios: An array of two GPIO specs to describe the GPIOs
15 the ADAU's PLL config pins are connected to.
16 The state of the pins are set according to the
17 configured clock divider on ASoC side before the
18 firmware is loaded.
14 19
15Examples: 20Examples:
16 21
@@ -19,5 +24,6 @@ Examples:
19 compatible = "adi,adau1701"; 24 compatible = "adi,adau1701";
20 reg = <0x34>; 25 reg = <0x34>;
21 reset-gpio = <&gpio 23 0>; 26 reset-gpio = <&gpio 23 0>;
27 adi,pll-mode-gpios = <&gpio 24 0 &gpio 25 0>;
22 }; 28 };
23 }; 29 };