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authorPascal Huerst2015-04-20 04:12:03 -0500
committerMark Brown2015-04-27 09:37:32 -0500
commit64fcc1fd323835a9185baafa50d2087603c4051c (patch)
tree391ca0c5c617a0eda992827fa4c6ab3a4946f700 /Documentation/devicetree/bindings/sound/adi,adau1701.txt
parentb787f68c36d49bb1d9236f403813641efa74a031 (diff)
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ASoC: adau1701: add regulator consumer support
The adau1701 has two power domains, DVDD and AVDD. Enable them both as long as the codec is in use. Signed-off-by: Pascal Huerst <pascal.huerst@gmail.com> Acked-by: Lars-Peter Clausen <lars@metafoo.de> Signed-off-by: Mark Brown <broonie@kernel.org>
Diffstat (limited to 'Documentation/devicetree/bindings/sound/adi,adau1701.txt')
-rw-r--r--Documentation/devicetree/bindings/sound/adi,adau1701.txt4
1 files changed, 4 insertions, 0 deletions
diff --git a/Documentation/devicetree/bindings/sound/adi,adau1701.txt b/Documentation/devicetree/bindings/sound/adi,adau1701.txt
index 547a49b56a62..0d1128ce2ea7 100644
--- a/Documentation/devicetree/bindings/sound/adi,adau1701.txt
+++ b/Documentation/devicetree/bindings/sound/adi,adau1701.txt
@@ -20,6 +20,8 @@ Optional properties:
20 pin configurations as described in the datasheet, 20 pin configurations as described in the datasheet,
21 table 53. Note that the value of this property has 21 table 53. Note that the value of this property has
22 to be prefixed with '/bits/ 8'. 22 to be prefixed with '/bits/ 8'.
23 - avdd-supply: Power supply for AVDD, providing 3.3V
24 - dvdd-supply: Power supply for DVDD, providing 3.3V
23 25
24Examples: 26Examples:
25 27
@@ -28,6 +30,8 @@ Examples:
28 compatible = "adi,adau1701"; 30 compatible = "adi,adau1701";
29 reg = <0x34>; 31 reg = <0x34>;
30 reset-gpio = <&gpio 23 0>; 32 reset-gpio = <&gpio 23 0>;
33 avdd-supply = <&vdd_3v3_reg>;
34 dvdd-supply = <&vdd_3v3_reg>;
31 adi,pll-mode-gpios = <&gpio 24 0 &gpio 25 0>; 35 adi,pll-mode-gpios = <&gpio 24 0 &gpio 25 0>;
32 adi,pin-config = /bits/ 8 <0x4 0x7 0x5 0x5 0x4 0x4 36 adi,pin-config = /bits/ 8 <0x4 0x7 0x5 0x5 0x4 0x4
33 0x4 0x4 0x4 0x4 0x4 0x4>; 37 0x4 0x4 0x4 0x4 0x4 0x4>;