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author | Daniel Mack | 2012-12-10 03:30:04 -0600 |
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committer | Mark Brown | 2012-12-24 09:53:28 -0600 |
commit | fd23fb9f6bfd43a6e62b2646d18d5ca3edc3ebe3 (patch) | |
tree | a1033cbc88a3ccba164e8d0f6c7469f9efd6713a /Documentation/devicetree/bindings/sound/cs4271.txt | |
parent | 133d2e6188de86df3ed84cd42ac66e9c5d328c04 (diff) | |
download | ti-linux-kernel-fd23fb9f6bfd43a6e62b2646d18d5ca3edc3ebe3.tar.gz ti-linux-kernel-fd23fb9f6bfd43a6e62b2646d18d5ca3edc3ebe3.tar.xz ti-linux-kernel-fd23fb9f6bfd43a6e62b2646d18d5ca3edc3ebe3.zip |
ALSA: ASoC: cs4271: add optional soft reset workaround
The CS4271 requires its LRCLK and MCLK to be stable before its RESET
line is de-asserted. That also means that clocks cannot be changed
without putting the chip back into hardware reset, which also requires
a complete re-initialization of all registers.
One (undocumented) workaround is to assert and de-assert the PDN bit
in the MODE2 register.
This patch adds a new flag to both the DT bindings as well as to the
platform data to enable that workaround.
Signed-off-by: Daniel Mack <zonque@gmail.com>
Acked-by: Alexander Sverdlin <subaparts@yandex.ru>
Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
Diffstat (limited to 'Documentation/devicetree/bindings/sound/cs4271.txt')
-rw-r--r-- | Documentation/devicetree/bindings/sound/cs4271.txt | 12 |
1 files changed, 12 insertions, 0 deletions
diff --git a/Documentation/devicetree/bindings/sound/cs4271.txt b/Documentation/devicetree/bindings/sound/cs4271.txt index a850fb9c88ea..e2cd1d7539e5 100644 --- a/Documentation/devicetree/bindings/sound/cs4271.txt +++ b/Documentation/devicetree/bindings/sound/cs4271.txt | |||
@@ -20,6 +20,18 @@ Optional properties: | |||
20 | !RESET pin | 20 | !RESET pin |
21 | - cirrus,amuteb-eq-bmutec: When given, the Codec's AMUTEB=BMUTEC flag | 21 | - cirrus,amuteb-eq-bmutec: When given, the Codec's AMUTEB=BMUTEC flag |
22 | is enabled. | 22 | is enabled. |
23 | - cirrus,enable-soft-reset: | ||
24 | The CS4271 requires its LRCLK and MCLK to be stable before its RESET | ||
25 | line is de-asserted. That also means that clocks cannot be changed | ||
26 | without putting the chip back into hardware reset, which also requires | ||
27 | a complete re-initialization of all registers. | ||
28 | |||
29 | One (undocumented) workaround is to assert and de-assert the PDN bit | ||
30 | in the MODE2 register. This workaround can be enabled with this DT | ||
31 | property. | ||
32 | |||
33 | Note that this is not needed in case the clocks are stable | ||
34 | throughout the entire runtime of the codec. | ||
23 | 35 | ||
24 | Examples: | 36 | Examples: |
25 | 37 | ||