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authorPeter Ujfalusi2012-08-21 09:33:56 -0500
committerMark Brown2012-08-22 14:18:00 -0500
commitb8101048f0f3cd281ed4c4901e38ae2bcfb32030 (patch)
treeb42327857aab66c57b8b86d01da2302f3d89f5e1 /Documentation/devicetree/bindings/sound/omap-mcbsp.txt
parent11dd586421b3091007e6f084a9211f3baa66f9fc (diff)
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ASoC: omap-mcbsp: Device tree binding documentation update
To reflect the final devicetree node structure of McBSPs. The initial OMAP McBSP DT structure was not able to describe the IP (and it's versions) correctly. The main issue was the sidetone block of McBSP2/3 on OMAP3. With this change in the DT description the OS can get the needed information about the IP. The sidetone is still not supported when the Linux kernel is booted with DT since we still depend on hwmod to fill the resources. Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com> Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
Diffstat (limited to 'Documentation/devicetree/bindings/sound/omap-mcbsp.txt')
-rw-r--r--Documentation/devicetree/bindings/sound/omap-mcbsp.txt28
1 files changed, 10 insertions, 18 deletions
diff --git a/Documentation/devicetree/bindings/sound/omap-mcbsp.txt b/Documentation/devicetree/bindings/sound/omap-mcbsp.txt
index 447cb131e909..17cce4490456 100644
--- a/Documentation/devicetree/bindings/sound/omap-mcbsp.txt
+++ b/Documentation/devicetree/bindings/sound/omap-mcbsp.txt
@@ -8,38 +8,30 @@ Required properties:
8- reg: Register location and size, for OMAP4+ as an array: 8- reg: Register location and size, for OMAP4+ as an array:
9 <MPU access base address, size>, 9 <MPU access base address, size>,
10 <L3 interconnect address, size>; 10 <L3 interconnect address, size>;
11- reg-names: Array of strings associated with the address space
11- interrupts: Interrupt numbers for the McBSP port, as an array in case the 12- interrupts: Interrupt numbers for the McBSP port, as an array in case the
12 McBSP IP have more interrupt lines: 13 McBSP IP have more interrupt lines:
13 <OCP compliant irq>, 14 <OCP compliant irq>,
14 <TX irq>, 15 <TX irq>,
15 <RX irq>; 16 <RX irq>;
17- interrupt-names: Array of strings associated with the interrupt numbers
16- interrupt-parent: The parent interrupt controller 18- interrupt-parent: The parent interrupt controller
17- ti,buffer-size: Size of the FIFO on the port (OMAP2430 and newer SoC) 19- ti,buffer-size: Size of the FIFO on the port (OMAP2430 and newer SoC)
18- ti,hwmods: Name of the hwmod associated to the McBSP port 20- ti,hwmods: Name of the hwmod associated to the McBSP port
19 21
20Sidetone support for OMAP3 McBSP2 and 3 ports:
21- sidetone { }: Within this section the following parameters are required:
22- reg: Register location and size for the ST block
23- interrupts: The interrupt number for the ST block
24- interrupt-parent: The parent interrupt controller for the ST block
25
26Example: 22Example:
27 23
28mcbsp2: mcbsp@49022000 { 24mcbsp2: mcbsp@49022000 {
29 compatible = "ti,omap3-mcbsp"; 25 compatible = "ti,omap3-mcbsp";
30 #address-cells = <1>; 26 reg = <0x49022000 0xff>,
31 #size-cells = <1>; 27 <0x49028000 0xff>;
32 reg = <0x49022000 0xff>; 28 reg-names = "mpu", "sidetone";
33 interrupts = <0 17 0x4>, /* OCP compliant interrup */ 29 interrupts = <0 17 0x4>, /* OCP compliant interrupt */
34 <0 62 0x4>, /* TX interrup */ 30 <0 62 0x4>, /* TX interrupt */
35 <0 63 0x4>; /* RX interrup */ 31 <0 63 0x4>, /* RX interrupt */
32 <0 4 0x4>; /* Sidetone */
33 interrupt-names = "common", "tx", "rx", "sidetone";
36 interrupt-parent = <&intc>; 34 interrupt-parent = <&intc>;
37 ti,buffer-size = <1280>; 35 ti,buffer-size = <1280>;
38 ti,hwmods = "mcbsp2"; 36 ti,hwmods = "mcbsp2";
39
40 sidetone {
41 reg = <0x49028000 0xff>;
42 interrupts = <0 4 0x4>;
43 interrupt-parent = <&intc>;
44 };
45}; 37};