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author | Bhupesh Sharma | 2015-10-23 14:31:53 -0500 |
---|---|---|
committer | Arnd Bergmann | 2015-10-23 15:24:45 -0500 |
commit | a2cce7a9f1b8cc3d4edce106fb971529f1d4d9ce (patch) | |
tree | 23c05167281d7fffa589b31c7fcaca770b2f49b4 /Documentation/devicetree | |
parent | cc56a128a5c0875196c7518cf8147e16384b2329 (diff) | |
download | ti-linux-kernel-a2cce7a9f1b8cc3d4edce106fb971529f1d4d9ce.tar.gz ti-linux-kernel-a2cce7a9f1b8cc3d4edce106fb971529f1d4d9ce.tar.xz ti-linux-kernel-a2cce7a9f1b8cc3d4edce106fb971529f1d4d9ce.zip |
Documentation/dts: Move FSL board-specific bindings out of /powerpc
Since the same board components can be used across ARM and PPC board families,
this patch moves the FSL board-specific bindings out of bindings/powerpci.
While at it, this patch also adds the bindings for QIXIS FPGA controller
found on FSL LS2080A boards. These boards have an on-board FPGA/CPLD
connected to the IFC controller.
Signed-off-by: Bhupesh Sharma <bhupesh.sharma@freescale.com>
Signed-off-by: Jaiprakash Singh <b44839@freescale.com>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Diffstat (limited to 'Documentation/devicetree')
-rw-r--r-- | Documentation/devicetree/bindings/board/fsl-board.txt (renamed from Documentation/devicetree/bindings/powerpc/fsl/board.txt) | 14 |
1 files changed, 12 insertions, 2 deletions
diff --git a/Documentation/devicetree/bindings/powerpc/fsl/board.txt b/Documentation/devicetree/bindings/board/fsl-board.txt index cff38bdbc0e4..fb7b03ec2071 100644 --- a/Documentation/devicetree/bindings/powerpc/fsl/board.txt +++ b/Documentation/devicetree/bindings/board/fsl-board.txt | |||
@@ -21,11 +21,14 @@ Example: | |||
21 | 21 | ||
22 | This is the memory-mapped registers for on board FPGA. | 22 | This is the memory-mapped registers for on board FPGA. |
23 | 23 | ||
24 | Required properities: | 24 | Required properties: |
25 | - compatible: should be a board-specific string followed by a string | 25 | - compatible: should be a board-specific string followed by a string |
26 | indicating the type of FPGA. Example: | 26 | indicating the type of FPGA. Example: |
27 | "fsl,<board>-fpga", "fsl,fpga-pixis" | 27 | "fsl,<board>-fpga", "fsl,fpga-pixis", or |
28 | "fsl,<board>-fpga", "fsl,fpga-qixis" | ||
28 | - reg: should contain the address and the length of the FPGA register set. | 29 | - reg: should contain the address and the length of the FPGA register set. |
30 | |||
31 | Optional properties: | ||
29 | - interrupt-parent: should specify phandle for the interrupt controller. | 32 | - interrupt-parent: should specify phandle for the interrupt controller. |
30 | - interrupts: should specify event (wakeup) IRQ. | 33 | - interrupts: should specify event (wakeup) IRQ. |
31 | 34 | ||
@@ -38,6 +41,13 @@ Example (P1022DS): | |||
38 | interrupts = <8 8 0 0>; | 41 | interrupts = <8 8 0 0>; |
39 | }; | 42 | }; |
40 | 43 | ||
44 | Example (LS2080A-RDB): | ||
45 | |||
46 | cpld@3,0 { | ||
47 | compatible = "fsl,ls2080ardb-fpga", "fsl,fpga-qixis"; | ||
48 | reg = <0x3 0 0x10000>; | ||
49 | }; | ||
50 | |||
41 | * Freescale BCSR GPIO banks | 51 | * Freescale BCSR GPIO banks |
42 | 52 | ||
43 | Some BCSR registers act as simple GPIO controllers, each such | 53 | Some BCSR registers act as simple GPIO controllers, each such |