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author | Judith Mendez | 2023-10-31 15:45:55 -0500 |
---|---|---|
committer | Guillaume La Roque | 2023-12-06 14:03:40 -0600 |
commit | 55c84684fa5a207069d41dad6d7c5c603d166269 (patch) | |
tree | 64271858d4f29f417a039331bcaf02f00226dced /arch/arm64/boot/dts/ti/k3-am62p5-sk-mcan.dtso | |
parent | 206895b5df23680885ca653365d77ad042e6ecdc (diff) | |
download | ti-linux-kernel-55c84684fa5a207069d41dad6d7c5c603d166269.tar.gz ti-linux-kernel-55c84684fa5a207069d41dad6d7c5c603d166269.tar.xz ti-linux-kernel-55c84684fa5a207069d41dad6d7c5c603d166269.zip |
TI: arm64: dts: ti: Add MCAN overlay for AM62P-SK
On AM62P-SK there are 2x MCAN in MAIN domain and 2x MCAN in
MCU domain.
AM62P-SK does not carry on-board CAN transceivers, so MCAN does
not work 'out of the box', external CAN transceivers need to be
connected to test each CAN. Instead of changing DTB permanently
use an overlay to enable 4x MCAN on AM62P-SK.
Signed-off-by: Judith Mendez <jm@ti.com>
Reviewed-by: Bryan Brattlof <bb@ti.com>
(cherry picked from commit 531117b60a51cd46d2eb9cf6139cadcbd48367c1)
Signed-off-by: Guillaume La Roque <glaroque@baylibre.com>
Diffstat (limited to 'arch/arm64/boot/dts/ti/k3-am62p5-sk-mcan.dtso')
-rw-r--r-- | arch/arm64/boot/dts/ti/k3-am62p5-sk-mcan.dtso | 122 |
1 files changed, 122 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/ti/k3-am62p5-sk-mcan.dtso b/arch/arm64/boot/dts/ti/k3-am62p5-sk-mcan.dtso new file mode 100644 index 000000000000..9a3d8256e2a9 --- /dev/null +++ b/arch/arm64/boot/dts/ti/k3-am62p5-sk-mcan.dtso | |||
@@ -0,0 +1,122 @@ | |||
1 | // SPDX-License-Identifier: GPL-2.0 | ||
2 | /** | ||
3 | * DT overlay for enabling MCAN for AM62P-SK | ||
4 | * | ||
5 | * Copyright (C) 2023 Texas Instruments Incorporated - https://www.ti.com/ | ||
6 | */ | ||
7 | |||
8 | /dts-v1/; | ||
9 | /plugin/; | ||
10 | |||
11 | #include <dt-bindings/gpio/gpio.h> | ||
12 | #include "k3-pinctrl.h" | ||
13 | |||
14 | &{/} { | ||
15 | transceiver1: can-phy0 { | ||
16 | compatible = "ti,tcan1042"; | ||
17 | #phy-cells = <0>; | ||
18 | max-bitrate = <5000000>; | ||
19 | }; | ||
20 | |||
21 | transceiver2: can-phy1 { | ||
22 | compatible = "ti,tcan1042"; | ||
23 | #phy-cells = <0>; | ||
24 | max-bitrate = <5000000>; | ||
25 | }; | ||
26 | |||
27 | transceiver3: can-phy2 { | ||
28 | compatible = "ti,tcan1042"; | ||
29 | #phy-cells = <0>; | ||
30 | max-bitrate = <5000000>; | ||
31 | }; | ||
32 | |||
33 | transceiver4: can-phy3 { | ||
34 | compatible = "ti,tcan1042"; | ||
35 | #phy-cells = <0>; | ||
36 | max-bitrate = <5000000>; | ||
37 | }; | ||
38 | }; | ||
39 | |||
40 | &main_pmx0 { | ||
41 | main_mcan0_pins_default: main-mcan0-pins-default { | ||
42 | pinctrl-single,pins = < | ||
43 | AM62PX_IOPAD(0x01dc, PIN_INPUT, 0) /* (F20) MCAN0_RX */ | ||
44 | AM62PX_IOPAD(0x01d8, PIN_OUTPUT, 0) /* (B23) MCAN0_TX */ | ||
45 | >; | ||
46 | }; | ||
47 | |||
48 | main_mcan1_pins_default: main-mcan1-pins-default { | ||
49 | pinctrl-single,pins = < | ||
50 | AM62PX_IOPAD(0x00b4, PIN_INPUT, 5) /* (U25) GPMC0_CSn3.MCAN1_RX */ | ||
51 | AM62PX_IOPAD(0x00b0, PIN_OUTPUT, 5) /* (T22) GPMC0_CSn2.MCAN1_TX */ | ||
52 | >; | ||
53 | }; | ||
54 | }; | ||
55 | |||
56 | &mcu_pmx0 { | ||
57 | mcu_mcan0_pins_default: mcu-mcan0-pins-default { | ||
58 | pinctrl-single,pins = < | ||
59 | AM62PX_MCU_IOPAD(0x0038, PIN_INPUT, 0) /* (D6) MCU_MCAN0_RX */ | ||
60 | AM62PX_MCU_IOPAD(0x0034, PIN_OUTPUT, 0) /* (E8) MCU_MCAN0_TX */ | ||
61 | >; | ||
62 | }; | ||
63 | |||
64 | mcu_mcan1_pins_default: mcu-mcan1-pins-default { | ||
65 | pinctrl-single,pins = < | ||
66 | AM62PX_MCU_IOPAD(0x0040, PIN_INPUT, 0) /* (E7) MCU_MCAN1_RX */ | ||
67 | AM62PX_MCU_IOPAD(0x003c, PIN_OUTPUT, 0) /* (F8) MCU_MCAN1_TX */ | ||
68 | >; | ||
69 | }; | ||
70 | }; | ||
71 | |||
72 | &main_i2c2{ | ||
73 | /* | ||
74 | * main_i2c2 is using (U25) and (T22) | ||
75 | * so disable to use main_mcan1 | ||
76 | */ | ||
77 | status = "disabled"; | ||
78 | }; | ||
79 | |||
80 | &main_i2c1 { | ||
81 | /* | ||
82 | * Unset GPIO SoC_I2C2_MCAN_SEL to | ||
83 | * route MCAN1 signals to MCAN1 HDR | ||
84 | */ | ||
85 | gpio@23 { | ||
86 | p20-hog { | ||
87 | /* P20 - SoC_I2C2_MCAN_SEL */ | ||
88 | gpio-hog; | ||
89 | gpios = <16 GPIO_ACTIVE_HIGH>; | ||
90 | output-low; | ||
91 | line-name = "SoC_I2C2_MCAN_SEL"; | ||
92 | }; | ||
93 | }; | ||
94 | }; | ||
95 | |||
96 | &main_mcan0 { | ||
97 | status = "okay"; | ||
98 | pinctrl-names = "default"; | ||
99 | pinctrl-0 = <&main_mcan0_pins_default>; | ||
100 | phys = <&transceiver1>; | ||
101 | }; | ||
102 | |||
103 | &main_mcan1 { | ||
104 | status = "okay"; | ||
105 | pinctrl-names = "default"; | ||
106 | pinctrl-0 = <&main_mcan1_pins_default>; | ||
107 | phys = <&transceiver2>; | ||
108 | }; | ||
109 | |||
110 | &mcu_mcan0 { | ||
111 | status = "okay"; | ||
112 | pinctrl-names = "default"; | ||
113 | pinctrl-0 = <&mcu_mcan0_pins_default>; | ||
114 | phys = <&transceiver3>; | ||
115 | }; | ||
116 | |||
117 | &mcu_mcan1 { | ||
118 | status = "okay"; | ||
119 | pinctrl-names = "default"; | ||
120 | pinctrl-0 = <&mcu_mcan1_pins_default>; | ||
121 | phys = <&transceiver4>; | ||
122 | }; | ||