spi: cadence-quadspi: flush posted register writes before DAC access

cqspi_read_setup() and cqspi_write_setup() program the address width as
the last step in the setup. This is likely to be immediately followed by
a DAC region read/write. On TI K3 SoCs the DAC region is on a different
endpoint from the register region. This means that the order of the two
operations is not guaranteed, and they might be reordered at the
interconnect level. It is possible that the DAC read/write goes through
before the address width update goes through. In this situation if the
previous command used a different address width the OSPI command is sent
with the wrong number of address bytes, resulting in an invalid command
and undefined behavior.

Read back the size register to make sure the write gets flushed before
accessing the DAC region.

Signed-off-by: Pratyush Yadav <p.yadav@ti.com>
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>

1 files changed, 2 insertions, 0 deletions

diff --git a/drivers/spi/spi-cadence-quadspi.c b/drivers/spi/spi-cadence-quadspi.c
index 06618ac74f67..53ba8502b988 100644
--- a/drivers/spi/spi-cadence-quadspi.c
+++ b/drivers/spi/spi-cadence-quadspi.c
@@ -1265,6 +1265,7 @@ static int cqspi_read_setup(struct cqspi_flash_pdata *f_pdata,
         reg &= ~CQSPI_REG_SIZE_ADDRESS_MASK;
         reg |= (op->addr.nbytes - 1);
         writel(reg, reg_base + CQSPI_REG_SIZE);
+        readl(reg_base + CQSPI_REG_SIZE); /* Flush posted write. */
         return 0;
 }
 
@@ -1405,6 +1406,7 @@ static int cqspi_write_setup(struct cqspi_flash_pdata *f_pdata,
         reg &= ~CQSPI_REG_SIZE_ADDRESS_MASK;
         reg |= (op->addr.nbytes - 1);
         writel(reg, reg_base + CQSPI_REG_SIZE);
+        readl(reg_base + CQSPI_REG_SIZE); /* Flush posted write. */
         return 0;
 }