aboutsummaryrefslogtreecommitdiffstats
diff options
context:
space:
mode:
-rw-r--r--arch/arm64/boot/dts/ti/k3-j721e-main.dtsi202
-rw-r--r--arch/arm64/boot/dts/ti/k3-j721e-mcu-wakeup.dtsi71
-rw-r--r--arch/arm64/boot/dts/ti/k3-j721e.dtsi177
3 files changed, 450 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi b/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi
new file mode 100644
index 000000000000..d42912044a5d
--- /dev/null
+++ b/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi
@@ -0,0 +1,202 @@
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Device Tree Source for J721E SoC Family Main Domain peripherals
4 *
5 * Copyright (C) 2016-2019 Texas Instruments Incorporated - http://www.ti.com/
6 */
7
8&cbass_main {
9 msmc_ram: sram@70000000 {
10 compatible = "mmio-sram";
11 reg = <0x0 0x70000000 0x0 0x800000>;
12 #address-cells = <1>;
13 #size-cells = <1>;
14 ranges = <0x0 0x0 0x70000000 0x800000>;
15
16 atf-sram@0 {
17 reg = <0x0 0x20000>;
18 };
19 };
20
21 gic500: interrupt-controller@1800000 {
22 compatible = "arm,gic-v3";
23 #address-cells = <2>;
24 #size-cells = <2>;
25 ranges;
26 #interrupt-cells = <3>;
27 interrupt-controller;
28 reg = <0x00 0x01800000 0x00 0x10000>, /* GICD */
29 <0x00 0x01900000 0x00 0x100000>; /* GICR */
30
31 /* vcpumntirq: virtual CPU interface maintenance interrupt */
32 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
33
34 gic_its: gic-its@18200000 {
35 compatible = "arm,gic-v3-its";
36 reg = <0x00 0x01820000 0x00 0x10000>;
37 socionext,synquacer-pre-its = <0x1000000 0x400000>;
38 msi-controller;
39 #msi-cells = <1>;
40 };
41 };
42
43 smmu0: smmu@36600000 {
44 compatible = "arm,smmu-v3";
45 reg = <0x0 0x36600000 0x0 0x100000>;
46 interrupt-parent = <&gic500>;
47 interrupts = <GIC_SPI 772 IRQ_TYPE_EDGE_RISING>,
48 <GIC_SPI 768 IRQ_TYPE_EDGE_RISING>;
49 interrupt-names = "eventq", "gerror";
50 #iommu-cells = <1>;
51 };
52
53 secure_proxy_main: mailbox@32c00000 {
54 compatible = "ti,am654-secure-proxy";
55 #mbox-cells = <1>;
56 reg-names = "target_data", "rt", "scfg";
57 reg = <0x00 0x32c00000 0x00 0x100000>,
58 <0x00 0x32400000 0x00 0x100000>,
59 <0x00 0x32800000 0x00 0x100000>;
60 interrupt-names = "rx_011";
61 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
62 };
63
64 main_pmx0: pinmux@11c000 {
65 compatible = "pinctrl-single";
66 /* Proxy 0 addressing */
67 reg = <0x0 0x11c000 0x0 0x2b4>;
68 #pinctrl-cells = <1>;
69 pinctrl-single,register-width = <32>;
70 pinctrl-single,function-mask = <0xffffffff>;
71 };
72
73 main_uart0: serial@2800000 {
74 compatible = "ti,j721e-uart", "ti,am654-uart";
75 reg = <0x00 0x02800000 0x00 0x100>;
76 reg-shift = <2>;
77 reg-io-width = <4>;
78 interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>;
79 clock-frequency = <48000000>;
80 current-speed = <115200>;
81 power-domains = <&k3_pds 146>;
82 clocks = <&k3_clks 146 0>;
83 clock-names = "fclk";
84 };
85
86 main_uart1: serial@2810000 {
87 compatible = "ti,j721e-uart", "ti,am654-uart";
88 reg = <0x00 0x02810000 0x00 0x100>;
89 reg-shift = <2>;
90 reg-io-width = <4>;
91 interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>;
92 clock-frequency = <48000000>;
93 current-speed = <115200>;
94 power-domains = <&k3_pds 278>;
95 clocks = <&k3_clks 278 0>;
96 clock-names = "fclk";
97 };
98
99 main_uart2: serial@2820000 {
100 compatible = "ti,j721e-uart", "ti,am654-uart";
101 reg = <0x00 0x02820000 0x00 0x100>;
102 reg-shift = <2>;
103 reg-io-width = <4>;
104 interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>;
105 clock-frequency = <48000000>;
106 current-speed = <115200>;
107 power-domains = <&k3_pds 279>;
108 clocks = <&k3_clks 279 0>;
109 clock-names = "fclk";
110 };
111
112 main_uart3: serial@2830000 {
113 compatible = "ti,j721e-uart", "ti,am654-uart";
114 reg = <0x00 0x02830000 0x00 0x100>;
115 reg-shift = <2>;
116 reg-io-width = <4>;
117 interrupts = <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>;
118 clock-frequency = <48000000>;
119 current-speed = <115200>;
120 power-domains = <&k3_pds 280>;
121 clocks = <&k3_clks 280 0>;
122 clock-names = "fclk";
123 };
124
125 main_uart4: serial@2840000 {
126 compatible = "ti,j721e-uart", "ti,am654-uart";
127 reg = <0x00 0x02840000 0x00 0x100>;
128 reg-shift = <2>;
129 reg-io-width = <4>;
130 interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>;
131 clock-frequency = <48000000>;
132 current-speed = <115200>;
133 power-domains = <&k3_pds 281>;
134 clocks = <&k3_clks 281 0>;
135 clock-names = "fclk";
136 };
137
138 main_uart5: serial@2850000 {
139 compatible = "ti,j721e-uart", "ti,am654-uart";
140 reg = <0x00 0x02850000 0x00 0x100>;
141 reg-shift = <2>;
142 reg-io-width = <4>;
143 interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>;
144 clock-frequency = <48000000>;
145 current-speed = <115200>;
146 power-domains = <&k3_pds 282>;
147 clocks = <&k3_clks 282 0>;
148 clock-names = "fclk";
149 };
150
151 main_uart6: serial@2860000 {
152 compatible = "ti,j721e-uart", "ti,am654-uart";
153 reg = <0x00 0x02860000 0x00 0x100>;
154 reg-shift = <2>;
155 reg-io-width = <4>;
156 interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>;
157 clock-frequency = <48000000>;
158 current-speed = <115200>;
159 power-domains = <&k3_pds 283>;
160 clocks = <&k3_clks 283 0>;
161 clock-names = "fclk";
162 };
163
164 main_uart7: serial@2870000 {
165 compatible = "ti,j721e-uart", "ti,am654-uart";
166 reg = <0x00 0x02870000 0x00 0x100>;
167 reg-shift = <2>;
168 reg-io-width = <4>;
169 interrupts = <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>;
170 clock-frequency = <48000000>;
171 current-speed = <115200>;
172 power-domains = <&k3_pds 284>;
173 clocks = <&k3_clks 284 0>;
174 clock-names = "fclk";
175 };
176
177 main_uart8: serial@2880000 {
178 compatible = "ti,j721e-uart", "ti,am654-uart";
179 reg = <0x00 0x02880000 0x00 0x100>;
180 reg-shift = <2>;
181 reg-io-width = <4>;
182 interrupts = <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>;
183 clock-frequency = <48000000>;
184 current-speed = <115200>;
185 power-domains = <&k3_pds 285>;
186 clocks = <&k3_clks 285 0>;
187 clock-names = "fclk";
188 };
189
190 main_uart9: serial@2890000 {
191 compatible = "ti,j721e-uart", "ti,am654-uart";
192 reg = <0x00 0x02890000 0x00 0x100>;
193 reg-shift = <2>;
194 reg-io-width = <4>;
195 interrupts = <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>;
196 clock-frequency = <48000000>;
197 current-speed = <115200>;
198 power-domains = <&k3_pds 286>;
199 clocks = <&k3_clks 286 0>;
200 clock-names = "fclk";
201 };
202};
diff --git a/arch/arm64/boot/dts/ti/k3-j721e-mcu-wakeup.dtsi b/arch/arm64/boot/dts/ti/k3-j721e-mcu-wakeup.dtsi
new file mode 100644
index 000000000000..ff4674b97e53
--- /dev/null
+++ b/arch/arm64/boot/dts/ti/k3-j721e-mcu-wakeup.dtsi
@@ -0,0 +1,71 @@
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Device Tree Source for J721E SoC Family MCU/WAKEUP Domain peripherals
4 *
5 * Copyright (C) 2016-2019 Texas Instruments Incorporated - http://www.ti.com/
6 */
7
8&cbass_mcu_wakeup {
9 dmsc: dmsc@44083000 {
10 compatible = "ti,k2g-sci";
11 ti,host-id = <12>;
12
13 mbox-names = "rx", "tx";
14
15 mboxes= <&secure_proxy_main 11>,
16 <&secure_proxy_main 13>;
17
18 reg-names = "debug_messages";
19 reg = <0x00 0x44083000 0x0 0x1000>;
20
21 k3_pds: power-controller {
22 compatible = "ti,sci-pm-domain";
23 #power-domain-cells = <1>;
24 };
25
26 k3_clks: clocks {
27 compatible = "ti,k2g-sci-clk";
28 #clock-cells = <2>;
29 };
30
31 k3_reset: reset-controller {
32 compatible = "ti,sci-reset";
33 #reset-cells = <2>;
34 };
35 };
36
37 wkup_pmx0: pinmux@4301c000 {
38 compatible = "pinctrl-single";
39 /* Proxy 0 addressing */
40 reg = <0x00 0x4301c000 0x00 0x178>;
41 #pinctrl-cells = <1>;
42 pinctrl-single,register-width = <32>;
43 pinctrl-single,function-mask = <0xffffffff>;
44 };
45
46 wkup_uart0: serial@42300000 {
47 compatible = "ti,j721e-uart", "ti,am654-uart";
48 reg = <0x00 0x42300000 0x00 0x100>;
49 reg-shift = <2>;
50 reg-io-width = <4>;
51 interrupts = <GIC_SPI 897 IRQ_TYPE_LEVEL_HIGH>;
52 clock-frequency = <48000000>;
53 current-speed = <115200>;
54 power-domains = <&k3_pds 287>;
55 clocks = <&k3_clks 287 0>;
56 clock-names = "fclk";
57 };
58
59 mcu_uart0: serial@40a00000 {
60 compatible = "ti,j721e-uart", "ti,am654-uart";
61 reg = <0x00 0x40a00000 0x00 0x100>;
62 reg-shift = <2>;
63 reg-io-width = <4>;
64 interrupts = <GIC_SPI 846 IRQ_TYPE_LEVEL_HIGH>;
65 clock-frequency = <96000000>;
66 current-speed = <115200>;
67 power-domains = <&k3_pds 149>;
68 clocks = <&k3_clks 149 0>;
69 clock-names = "fclk";
70 };
71};
diff --git a/arch/arm64/boot/dts/ti/k3-j721e.dtsi b/arch/arm64/boot/dts/ti/k3-j721e.dtsi
new file mode 100644
index 000000000000..f8dd74b17bfb
--- /dev/null
+++ b/arch/arm64/boot/dts/ti/k3-j721e.dtsi
@@ -0,0 +1,177 @@
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Device Tree Source for J721E SoC Family
4 *
5 * Copyright (C) 2016-2019 Texas Instruments Incorporated - http://www.ti.com/
6 */
7
8#include <dt-bindings/interrupt-controller/irq.h>
9#include <dt-bindings/interrupt-controller/arm-gic.h>
10#include <dt-bindings/pinctrl/k3.h>
11
12/ {
13 model = "Texas Instruments K3 J721E SoC";
14 compatible = "ti,j721e";
15 interrupt-parent = <&gic500>;
16 #address-cells = <2>;
17 #size-cells = <2>;
18
19 aliases {
20 serial0 = &wkup_uart0;
21 serial1 = &mcu_uart0;
22 serial2 = &main_uart0;
23 serial3 = &main_uart1;
24 serial4 = &main_uart2;
25 serial5 = &main_uart3;
26 serial6 = &main_uart4;
27 serial7 = &main_uart5;
28 serial8 = &main_uart6;
29 serial9 = &main_uart7;
30 serial10 = &main_uart8;
31 serial11 = &main_uart9;
32 };
33
34 chosen { };
35
36 cpus {
37 #address-cells = <1>;
38 #size-cells = <0>;
39 cpu-map {
40 cluster0: cluster0 {
41 core0 {
42 cpu = <&cpu0>;
43 };
44
45 core1 {
46 cpu = <&cpu1>;
47 };
48 };
49
50 };
51
52 cpu0: cpu@0 {
53 compatible = "arm,cortex-a72";
54 reg = <0x000>;
55 device_type = "cpu";
56 enable-method = "psci";
57 i-cache-size = <0xC000>;
58 i-cache-line-size = <64>;
59 i-cache-sets = <256>;
60 d-cache-size = <0x8000>;
61 d-cache-line-size = <64>;
62 d-cache-sets = <128>;
63 next-level-cache = <&L2_0>;
64 };
65
66 cpu1: cpu@1 {
67 compatible = "arm,cortex-a72";
68 reg = <0x001>;
69 device_type = "cpu";
70 enable-method = "psci";
71 i-cache-size = <0xC000>;
72 i-cache-line-size = <64>;
73 i-cache-sets = <256>;
74 d-cache-size = <0x8000>;
75 d-cache-line-size = <64>;
76 d-cache-sets = <128>;
77 next-level-cache = <&L2_0>;
78 };
79 };
80
81 L2_0: l2-cache0 {
82 compatible = "cache";
83 cache-level = <2>;
84 cache-size = <0x100000>;
85 cache-line-size = <64>;
86 cache-sets = <2048>;
87 next-level-cache = <&msmc_l3>;
88 };
89
90 msmc_l3: l3-cache0 {
91 compatible = "cache";
92 cache-level = <3>;
93 };
94
95 firmware {
96 optee {
97 compatible = "linaro,optee-tz";
98 method = "smc";
99 };
100
101 psci: psci {
102 compatible = "arm,psci-1.0";
103 method = "smc";
104 };
105 };
106
107 a72_timer0: timer-cl0-cpu0 {
108 compatible = "arm,armv8-timer";
109 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, /* cntpsirq */
110 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, /* cntpnsirq */
111 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, /* cntvirq */
112 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; /* cnthpirq */
113 };
114
115 pmu: pmu {
116 compatible = "arm,armv8-pmuv3";
117 /* Recommendation from GIC500 TRM Table A.3 */
118 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
119 };
120
121 cbass_main: interconnect@100000 {
122 compatible = "simple-bus";
123 #address-cells = <2>;
124 #size-cells = <2>;
125 ranges = <0x00 0x00100000 0x00 0x00100000 0x00 0x00020000>, /* ctrl mmr */
126 <0x00 0x00600000 0x00 0x00600000 0x00 0x00031100>, /* GPIO */
127 <0x00 0x00900000 0x00 0x00900000 0x00 0x00012000>, /* serdes */
128 <0x00 0x00A40000 0x00 0x00A40000 0x00 0x00000800>, /* timesync router */
129 <0x00 0x01000000 0x00 0x01000000 0x00 0x0af02400>, /* Most peripherals */
130 <0x00 0x30800000 0x00 0x30800000 0x00 0x0bc00000>, /* MAIN NAVSS */
131 <0x00 0x0d000000 0x00 0x0d000000 0x00 0x01000000>, /* PCIe Core*/
132 <0x00 0x10000000 0x00 0x10000000 0x00 0x10000000>, /* PCIe DAT */
133 <0x00 0x64800000 0x00 0x64800000 0x00 0x00800000>, /* C71 */
134 <0x4d 0x80800000 0x4d 0x80800000 0x00 0x00800000>, /* C66_0 */
135 <0x4d 0x81800000 0x4d 0x81800000 0x00 0x00800000>, /* C66_1 */
136 <0x4e 0x20000000 0x4e 0x20000000 0x00 0x00080000>, /* GPU */
137 <0x00 0x70000000 0x00 0x70000000 0x00 0x00800000>, /* MSMC RAM */
138
139 /* MCUSS_WKUP Range */
140 <0x00 0x28380000 0x00 0x28380000 0x00 0x03880000>,
141 <0x00 0x40200000 0x00 0x40200000 0x00 0x00998400>,
142 <0x00 0x40f00000 0x00 0x40f00000 0x00 0x00020000>,
143 <0x00 0x41000000 0x00 0x41000000 0x00 0x00020000>,
144 <0x00 0x41400000 0x00 0x41400000 0x00 0x00020000>,
145 <0x00 0x41c00000 0x00 0x41c00000 0x00 0x00100000>,
146 <0x00 0x42040000 0x00 0x42040000 0x00 0x03ac2400>,
147 <0x00 0x45100000 0x00 0x45100000 0x00 0x00c24000>,
148 <0x00 0x46000000 0x00 0x46000000 0x00 0x00200000>,
149 <0x00 0x47000000 0x00 0x47000000 0x00 0x00068400>,
150 <0x00 0x50000000 0x00 0x50000000 0x00 0x10000000>,
151 <0x05 0x00000000 0x05 0x00000000 0x01 0x00000000>,
152 <0x07 0x00000000 0x07 0x00000000 0x01 0x00000000>;
153
154 cbass_mcu_wakeup: interconnect@28380000 {
155 compatible = "simple-bus";
156 #address-cells = <2>;
157 #size-cells = <2>;
158 ranges = <0x00 0x28380000 0x00 0x28380000 0x00 0x03880000>, /* MCU NAVSS*/
159 <0x00 0x40200000 0x00 0x40200000 0x00 0x00998400>, /* First peripheral window */
160 <0x00 0x40f00000 0x00 0x40f00000 0x00 0x00020000>, /* CTRL_MMR0 */
161 <0x00 0x41000000 0x00 0x41000000 0x00 0x00020000>, /* MCU R5F Core0 */
162 <0x00 0x41400000 0x00 0x41400000 0x00 0x00020000>, /* MCU R5F Core1 */
163 <0x00 0x41c00000 0x00 0x41c00000 0x00 0x00100000>, /* MCU SRAM */
164 <0x00 0x42040000 0x00 0x42040000 0x00 0x03ac2400>, /* WKUP peripheral window */
165 <0x00 0x45100000 0x00 0x45100000 0x00 0x00c24000>, /* MMRs, remaining NAVSS */
166 <0x00 0x46000000 0x00 0x46000000 0x00 0x00200000>, /* CPSW */
167 <0x00 0x47000000 0x00 0x47000000 0x00 0x00068400>, /* OSPI register space */
168 <0x00 0x50000000 0x00 0x50000000 0x00 0x10000000>, /* FSS OSPI0/1 data region 0 */
169 <0x05 0x00000000 0x05 0x00000000 0x01 0x00000000>, /* FSS OSPI0 data region 3 */
170 <0x07 0x00000000 0x07 0x00000000 0x01 0x00000000>; /* FSS OSPI1 data region 3*/
171 };
172 };
173};
174
175/* Now include the peripherals for each bus segments */
176#include "k3-j721e-main.dtsi"
177#include "k3-j721e-mcu-wakeup.dtsi"