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Texas Instruments ICSSG PRUSS Ethernet
======================================
Required properties:
- compatible : Should be "ti,am654-icssg-prueth" for AM65x Family SoCs
"ti,am654-icssg-prueth-sr1" for SR1.0
"ti,am642-icssg-prueth" for AM64x
- ti,prus : list of pHandles to the PRU, RTU and TX_PRU nodes
- firmware-name : should contain the name of the firmware image
file located in the firmware search path
- sram : phandle to MSMC SRAM node
- dmas : list of phandles and specifiers to UDMA as specified in
bindings/dma/ti/k3-udma.txt.
- dma-names : Names for the DMA channels.
Should be "tx0-0", "tx0-1", "tx0-2", "0-3",
"tx1-0", "tx1-1", "tx1-2", "tx1-3",
"rx0", "rx1", "rxmgm0", "rxmgm1"
- mii-g-rt : phandle to MII_G_RT module's syscon regmap.
- mii-rt : phandle to MII_RT module's syscon regmap.
- ti,pruss-gp-mux-sel : GP-MUX value required for both ports.
- iep : list of pHandles to the to IEP modules
- interrupts : (SR2.0 only) Interrupt specifiers to TX timestamp IRQ.
- interrupt-names : "tx_ts0", "tx_ts1"
Must contain children, one for each of the MAC ports.
Children must be named ethernet-mii0 and ethernet-mii1.
Either one or both children can be present. If only one
child is present driver operates in single EMAC mode.
For single mode operation with the 2nd SLICE, you still need
to provide both PRUs and RTUs and firmware-names but the firmware-name
for the first PRU & RTU can be NULL.
Required properties for children:
- phy-handle : See ethernet.txt file in the same directory.
- phy-mode : See ethernet.txt file in the same directory.
- syscon-rgmii-delay : phandle to system controller node and register offset
to ICSSG control register for RGMII transmit delay.
Optional properties for children:
- local-mac-address : mac address for the port.
- ti,half-duplex-capable : Enable half duplex operation on ICSSG MII port.
This requires board modification to route PHY
output pin (COL) to ICSSG GPIO pin
(PRG0_PRU1_GPIO10) as input.
Example (k3-am654 base board SR2.0, dual-emac):
==============================================
/* Dual Ethernet application node on PRU-ICSSG2 */
pruss2_eth: pruss2_eth {
compatible = "ti,am654-icssg-prueth";
pinctrl-names = "default";
pinctrl-0 = <&icssg2_rgmii_pins_default>;
sram = <&msmc_ram>;
prus = <&pru2_0>, <&rtu2_0>, <&tx_pru2_0>, <&pru2_1>, <&rtu2_1>, <&tx_pru2_1>;
firmware-name = "ti-pruss/am65x-sr2-pru0-prueth-fw.elf",
"ti-pruss/am65x-sr2-rtu0-prueth-fw.elf",
"ti-pruss/am65x-sr2-txpru0-prueth-fw.elf",
"ti-pruss/am65x-sr2-pru1-prueth-fw.elf",
"ti-pruss/am65x-sr2-rtu1-prueth-fw.elf",
"ti-pruss/am65x-sr2-txpru1-prueth-fw.elf";
ti,pruss-gp-mux-sel = <2>, /* MII mode */
<2>,
<2>,
<2>, /* MII mode */
<2>,
<2>;
mii-g-rt = <&icssg2_mii_g_rt>;
dma-coherent;
dmas = <&main_udmap 0xc300>, /* egress slice 0 */
<&main_udmap 0xc301>, /* egress slice 0 */
<&main_udmap 0xc302>, /* egress slice 0 */
<&main_udmap 0xc303>, /* egress slice 0 */
<&main_udmap 0xc304>, /* egress slice 1 */
<&main_udmap 0xc305>, /* egress slice 1 */
<&main_udmap 0xc306>, /* egress slice 1 */
<&main_udmap 0xc307>, /* egress slice 1 */
<&main_udmap 0x4300>, /* ingress slice 0 */
<&main_udmap 0x4301>, /* ingress slice 1 */
<&main_udmap 0x4302>, /* mgmnt rsp slice 0 */
<&main_udmap 0x4303>; /* mgmnt rsp slice 1 */
dma-names = "tx0-0", "tx0-1", "tx0-2", "tx0-3",
"tx1-0", "tx1-1", "tx1-2", "tx1-3",
"rx0", "rx1",
"rxmgm0", "rxmgm1";
pruss2_emac0: ethernet-mii0 {
phy-handle = <&pruss2_eth0_phy>;
phy-mode = "rgmii-rxid";
interrupts-extended = <&icssg2_intc 24>;
syscon-rgmii-delay = <&scm_conf 0x4120>;
iep = <&icssg2_iep0>;
/* Filled in by bootloader */
local-mac-address = [00 00 00 00 00 00];
};
pruss2_emac1: ethernet-mii1 {
phy-handle = <&pruss2_eth1_phy>;
phy-mode = "rgmii-rxid";
interrupts-extended = <&icssg2_intc 25>;
syscon-rgmii-delay = <&scm_conf 0x4124>;
/* Filled in by bootloader */
local-mac-address = [00 00 00 00 00 00];
};
};
&icssg2_mdio {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&icssg2_mdio_pins_default>;
pruss2_eth0_phy: ethernet-phy@0 {
reg = <0>;
ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
};
pruss2_eth1_phy: ethernet-phy@3 {
reg = <3>;
ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
};
};
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