path: root/arch/arm64/boot/dts/ti/k3-am6.dtsi

// SPDX-License-Identifier: GPL-2.0
/*
 * Device Tree Source for AM6 SoC Family
 *
 * Copyright (C) 2016-2018 Texas Instruments Incorporated - http://www.ti.com/
 */

#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/phy/phy-am654-serdes.h>
#include <dt-bindings/pinctrl/k3-am6.h>
#include <dt-bindings/dma/k3-udma.h>

/ {
	model = "Texas Instruments K3 AM654 SoC";
	compatible = "ti,am654";
	interrupt-parent = <&gic>;
	#address-cells = <2>;
	#size-cells = <2>;

	aliases {
		serial0 = &wkup_uart0;
		serial1 = &mcu_uart0;
		serial2 = &main_uart0;
		serial3 = &main_uart1;
		serial4 = &main_uart2;
		i2c0 = &wkup_i2c0;
		i2c1 = &mcu_i2c0;
		i2c2 = &main_i2c0;
		i2c3 = &main_i2c1;
		i2c4 = &main_i2c2;
		i2c5 = &main_i2c3;
		spi0 = &ospi0;
		spi1 = &ospi1;
		spi2 = &main_spi0;
		ethernet0 = &cpsw_port1;
		rproc0 = &mcu_r5f0;
		rproc1 = &mcu_r5f1;
	};

	chosen { };

	firmware {
		optee {
			compatible = "linaro,optee-tz";
			method = "smc";
		};

		psci: psci {
			compatible = "arm,psci-1.0";
			method = "smc";
		};
	};

	soc0: soc0 {
		compatible = "simple-bus";
		#address-cells = <2>;
		#size-cells = <2>;
		ranges;

		scm_conf: scm_conf@100000 {
			compatible = "syscon", "simple-mfd";
			reg = <0 0x00100000 0 0x1c000>;
			#address-cells = <1>;
			#size-cells = <1>;
			ranges = <0x0 0x0 0x00100000 0x1c000>;

			serdes_mux: mux-controller {
				compatible = "mmio-mux";
				#mux-control-cells = <1>;
				mux-reg-masks = <0x4080 0x3>, /* SERDES0 lane select */
						<0x4090 0x3>; /* SERDES1 lane select */
			};

			pcie0_mode: pcie-mode@4060 {
				compatible = "syscon";
				reg = <0x00004060 0x4>;
			};

			pcie1_mode: pcie-mode@4070 {
				compatible = "syscon";
				reg = <0x00004070 0x4>;
			};

			serdes0_clk: serdes_clk@4080 {
				compatible = "syscon";
				reg = <0x00004080 0x4>;
			};

			serdes1_clk: serdes_clk@4090 {
				compatible = "syscon";
				reg = <0x00004090 0x4>;
			};

			pcie_devid: pcie-devid@210 {
				compatible = "syscon";
				reg = <0x00000210 0x4>;
			};
		};

		mcu_conf: scm_conf@40f00000 {
			compatible = "syscon";
			reg = <0 0x40f00000 0 0x20000>;
		};

		msmc_ram: sram@70000000 {
			compatible = "mmio-sram";
			reg = <0x0 0x70000000 0x0 0x200000>;
			#address-cells = <1>;
			#size-cells = <1>;
			ranges = <0x0 0x0 0x70000000 0x200000>;

			sram@0 {	/* Reserved for ATF */
				reg = <0x0 0x40000>;
			};

			sram@100000 {	/* Reserved for Cache */
				reg = <0x100000 0x100000>;
			};
		};

		a53_timer0: timer-cl0-cpu0 {
			compatible = "arm,armv8-timer";
			interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, /* cntpsirq */
				     <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, /* cntpnsirq */
				     <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, /* cntvirq */
				     <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; /* cnthpirq */
		};

		pmu: pmu {
			compatible = "arm,armv8-pmuv3";
			/* Recommendation from GIC500 TRM Table A.3 */
			interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
		};

		gic: interrupt-controller@1800000 {
			compatible = "arm,gic-v3";
			#address-cells = <2>;
			#size-cells = <2>;
			ranges;
			#interrupt-cells = <3>;
			interrupt-controller;
			/*
			 * NOTE: we are NOT gicv2 backward compat, so no GICC,
			 * GICH or GICV
			 */
			reg = <0x0 0x01800000 0x0 0x10000>,	/* GICD */
			      <0x0 0x01880000 0x0 0x90000>;	/* GICR */

			/*
			 * vcpumntirq:
			 * virtual CPU interface maintenance interrupt
			 */
			interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;

			gic_its: gic-its@1000000 {
				compatible = "arm,gic-v3-its";
				reg = <0x0 0x1820000 0x0 0x10000>;
				socionext,synquacer-pre-its = <0x1000000 0x400000>;
				msi-controller;
				#msi-cells = <1>;
			};
		};

		secure_proxy: secure_proxy@32c00000 {
			compatible = "ti,am654-secure-proxy";
			#mbox-cells = <1>;
			reg-names = "target_data", "rt", "scfg";
			reg = <0x0 0x32c00000 0x0 0x100000>,
			      <0x0 0x32400000 0x0 0x100000>,
			      <0x0 0x32800000 0x0 0x100000>;
			interrupt-names = "rx_011";
			interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
		};

		dmsc: dmsc {
			compatible = "ti,k2g-sci";
			ti,host-id = <12>;
			#address-cells = <2>;
			#size-cells = <2>;
			ranges;
			/*
			 * In case of rare platforms that does not use am6 as
			 * system master, use /delete-property/
			 */
			ti,system-reboot-controller;
			mbox-names = "rx", "tx";

			mboxes= <&secure_proxy 11>,
				<&secure_proxy 13>;

			k3_pds: power-controller {
				compatible = "ti,sci-pm-domain";
				#power-domain-cells = <1>;
			};

			k3_clks: clocks {
				compatible = "ti,k2g-sci-clk";
				#clock-cells = <2>;
			};

			k3_reset: reset-controller {
				compatible = "ti,sci-reset";
				#reset-cells = <2>;
			};
		};

		main_intr: interrupt-controller@1 {
			compatible = "ti,sci-intr";
			interrupt-controller;
			interrupt-parent = <&gic>;
			#interrupt-cells = <3>;
			ti,sci = <&dmsc>;
			ti,sci-dst-id = <56>;
			ti,sci-dst-irq-type = <0xb 0x1>;
		};

		cmpevt_intr: interrupt-controller@2 {
			compatible = "ti,sci-intr";
			interrupt-controller;
			interrupt-parent = <&gic>;
			#interrupt-cells = <3>;
			ti,sci = <&dmsc>;
			ti,sci-dst-id = <56>;
			ti,sci-dst-irq-type = <0xb 0x3>;
		};

		wkup_intr: interrupt-controller@3 {
			compatible = "ti,sci-intr";
			interrupt-controller;
			interrupt-parent = <&gic>;
			#interrupt-cells = <3>;
			ti,sci = <&dmsc>;
			ti,sci-dst-id = <56>;
			ti,sci-dst-irq-type = <0xb 0x4>;
		};

		main_pmx0: pinmux@11c000 {
			compatible = "pinctrl-single";
			reg = <0x0 0x11c000 0x0 0x2e4>;
			#pinctrl-cells = <1>;
			pinctrl-single,register-width = <32>;
			pinctrl-single,function-mask = <0xffffffff>;
		};

		main_pmx1: pinmux@11c2e8 {
			compatible = "pinctrl-single";
			reg = <0x0 0x11c2e8 0x0 0x24>;
			#pinctrl-cells = <1>;
			pinctrl-single,register-width = <32>;
			pinctrl-single,function-mask = <0xffffffff>;
		};

		wkup_pmx0: pinmux@4301c000 {
			compatible = "pinctrl-single";
			reg = <0x0 0x4301c000 0x0 0x118>;
			#pinctrl-cells = <1>;
			pinctrl-single,register-width = <32>;
			pinctrl-single,function-mask = <0xffffffff>;
		};

		mmc0: mmc@4f80000 {
			compatible = "simple-bus";
			#address-cells = <1>;
			#size-cells = <1>;
			ranges = <0x0 0x0 0x4f80000 0x20000>;

			sdhci0: sdhci@0 {
				compatible = "ti,am654-sdhci-5.1", "arasan,sdhci-5.1";
				reg = <0x0 0x1000>, <0x10000 0x100>;
				power-domains = <&k3_pds 47>;
				clocks = <&k3_clks 47 0>, <&k3_clks 47 1>;
				clock-names = "clk_ahb", "clk_xin";
				interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;
				clock-output-names = "emmc_cardclck";
				#clock-cells = <0>;
				phys=<&mmc_phy0>;
				phy-names = "phy_arasan";
				sdhci-caps-mask = <0x80000007 0x0>;
				mmc-hs200-1_8v;
				mmc-ddr-1_8v;
				status = "disabled";
			};

			mmc_phy0: mmc_phy@10100 {
				compatible = "ti,am654-mmc-phy";
				reg = <0x10100 0x34>;
				clocks = <&sdhci0>;
				clock-names = "mmcclk";
				#phy-cells = <0>;
				ti,otap-del-sel = <0x2>;
				ti,trm-icp = <0x8>;
				status = "disabled";
			};
		};

		mmc1: mmc@4fa0000 {
			compatible = "simple-bus";
			#address-cells = <1>;
			#size-cells = <1>;
			ranges = <0x0 0x0 0x4fa0000 0x20000>;

			sdhci1: sdhci@0 {
				compatible = "ti,am654-sdhci-5.1", "arasan,sdhci-5.1";
				reg = <0x0 0x1000>, <0x10000 0x100>;
				power-domains = <&k3_pds 48>;
				clocks = <&k3_clks 48 0>, <&k3_clks 48 1>;
				clock-names = "clk_ahb", "clk_xin";
				interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>;
				clock-output-names = "mmc_cardclck";
				#clock-cells = <0>;
				phys=<&mmc_phy1>;
				phy-names = "phy_arasan";
				sdhci-caps-mask = <0x7 0x0>;
				mmc-hs200-1_8v;
				mmc-ddr-1_8v;
				status = "disabled";
			};

			mmc_phy1: mmc_phy@10100 {
				compatible = "ti,am654-mmc-phy";
				reg = <0x10100 0x34>;
				clocks = <&sdhci1>;
				clock-names = "mmcclk";
				#phy-cells = <0>;
				ti,otap-del-sel = <0x2>;
				ti,trm-icp = <0x8>;
				status = "disabled";
			};
		};

		m_can0: mcan@40528000 {
			compatible = "bosch,m_can";
			reg = <0x0 0x40528000 0x0 0x400>,
			      <0x0 0x40500000 0x0 0x4400>;
			reg-names = "m_can", "message_ram";
			power-domains = <&k3_pds 102>;
			clocks = <&k3_clks 102 0>, <&k3_clks 102 5>;
			clock-names = "cclk", "hclk";
			interrupt-parent = <&gic>;
			interrupts = <GIC_SPI 544 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 545 IRQ_TYPE_LEVEL_HIGH>;
			interrupt-names = "int0", "int1";
			bosch,mram-cfg = <0x0 0 0 32 0 0 1 1>;
			status = "disabled";
		};

		m_can1: mcan@40568000 {
			compatible = "bosch,m_can";
			reg = <0x0 0x40568000 0x0 0x400>,
			      <0x0 0x40540000 0x0 0x4400>;
			reg-names = "m_can", "message_ram";
			power-domains = <&k3_pds 103>;
			clocks = <&k3_clks 103 0>, <&k3_clks 103 5>;
			clock-names = "cclk", "hclk";
			interrupt-parent = <&gic>;
			interrupts = <GIC_SPI 547 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 548 IRQ_TYPE_LEVEL_HIGH>;
			interrupt-names = "int0", "int1";
			bosch,mram-cfg = <0x0 0 0 32 0 0 1 1>;
			status = "disabled";
		};

		wkup_uart0: serial@42300000 {
			compatible = "ti,am654-uart", "ti,omap4-uart", "ns16550a";
			reg = <0x0 0x42300000 0x0 0x100>;
			reg-shift = <2>;
			reg-io-width = <4>;
			interrupts = <GIC_SPI 697 IRQ_TYPE_LEVEL_HIGH>;
			clock-frequency = <48000000>;
			current-speed = <115200>;
			status = "disabled";
		};

		mcu_uart0: serial@40a00000 {
			compatible = "ti,am654-uart", "ti,omap4-uart", "ns16550a";
			reg = <0x0 0x40a00000 0x0 0x100>;
			reg-shift = <2>;
			reg-io-width = <4>;
			interrupts = <GIC_SPI 565 IRQ_TYPE_LEVEL_HIGH>;
			clock-frequency = <96000000>;
			current-speed = <115200>;
			dmas = <&mcu_udmap &mcu_pdma1 18 UDMA_DIR_TX>,
			       <&mcu_udmap &mcu_pdma1 18 UDMA_DIR_RX>;
			dma-names = "tx", "rx";
			status = "disabled";
		};

		main_uart0: serial@2800000 {
			compatible = "ti,am654-uart", "ti,omap4-uart", "ns16550a";
			reg = <0x0 0x02800000 0x0 0x100>;
			reg-shift = <2>;
			reg-io-width = <4>;
			interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>;
			clock-frequency = <48000000>;
			current-speed = <115200>;
			dmas = <&main_udmap &pdma1 20 UDMA_DIR_TX>,
			       <&main_udmap &pdma1 20 UDMA_DIR_RX>;
			dma-names = "tx", "rx";
			status = "disabled";
		};

		main_uart1: serial@2810000 {
			compatible = "ti,am654-uart", "ti,omap4-uart", "ns16550a";
			reg = <0x0 0x02810000 0x0 0x100>;
			reg-shift = <2>;
			reg-io-width = <4>;
			interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>;
			clock-frequency = <48000000>;
			current-speed = <115200>;
			dmas = <&main_udmap &pdma1 21 UDMA_DIR_TX>,
			       <&main_udmap &pdma1 21 UDMA_DIR_RX>;
			dma-names = "tx", "rx";
			status = "disabled";
		};

		main_uart2: serial@2820000 {
			compatible = "ti,am654-uart", "ti,omap4-uart", "ns16550a";
			reg = <0x0 0x02820000 0x0 0x100>;
			reg-shift = <2>;
			reg-io-width = <4>;
			interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>;
			clock-frequency = <48000000>;
			current-speed = <115200>;
			dmas = <&main_udmap &pdma1 22 UDMA_DIR_TX>,
			       <&main_udmap &pdma1 22 UDMA_DIR_RX>;
			dma-names = "tx", "rx";
			status = "disabled";
		};

		wkup_i2c0: i2c@42120000 {
			compatible = "ti,am654-i2c", "ti,omap4-i2c";
			reg = <0x0 0x42120000 0x0 0x100>;
			interrupts = <GIC_SPI 696 IRQ_TYPE_LEVEL_HIGH>;
			#address-cells = <1>;
			#size-cells = <0>;
			clock-names = "fck";
			clocks = <&k3_clks 115 1>;
			power-domains = <&k3_pds 115>;
			status = "disabled";
		};

		mcu_i2c0: i2c@40b00000 {
			compatible = "ti,am654-i2c", "ti,omap4-i2c";
			reg = <0x0 0x40b00000 0x0 0x100>;
			interrupts = <GIC_SPI 564 IRQ_TYPE_LEVEL_HIGH>;
			#address-cells = <1>;
			#size-cells = <0>;
			clock-names = "fck";
			clocks = <&k3_clks 114 1>;
			power-domains = <&k3_pds 114>;
			status = "disabled";
		};

		main_i2c0: i2c@2000000 {
			compatible = "ti,am654-i2c", "ti,omap4-i2c";
			reg = <0x0 0x2000000 0x0 0x100>;
			interrupts = <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>;
			#address-cells = <1>;
			#size-cells = <0>;
			clock-names = "fck";
			clocks = <&k3_clks 110 1>;
			power-domains = <&k3_pds 110>;
			status = "disabled";
		};

		main_i2c1: i2c@2010000 {
			compatible = "ti,am654-i2c", "ti,omap4-i2c";
			reg = <0x0 0x2010000 0x0 0x100>;
			interrupts = <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>;
			#address-cells = <1>;
			#size-cells = <0>;
			clock-names = "fck";
			clocks = <&k3_clks 111 1>;
			power-domains = <&k3_pds 111>;
			status = "disabled";
		};

		main_i2c2: i2c@2020000 {
			compatible = "ti,am654-i2c", "ti,omap4-i2c";
			reg = <0x0 0x2020000 0x0 0x100>;
			interrupts = <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>;
			#address-cells = <1>;
			#size-cells = <0>;
			clock-names = "fck";
			clocks = <&k3_clks 112 1>;
			power-domains = <&k3_pds 112>;
			status = "disabled";
		};

		main_i2c3: i2c@2030000 {
			compatible = "ti,am654-i2c", "ti,omap4-i2c";
			reg = <0x0 0x2030000 0x0 0x100>;
			interrupts = <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>;
			#address-cells = <1>;
			#size-cells = <0>;
			clock-names = "fck";
			clocks = <&k3_clks 113 1>;
			power-domains = <&k3_pds 113>;
			status = "disabled";
		};

		main_gpio0:  main_gpio0@600000 {
			compatible = "ti,k2g-gpio", "ti,keystone-gpio";
			reg = <0x0 0x600000 0x0 0x100>;
			gpio-controller;
			#gpio-cells = <2>;

			interrupt-parent = <&main_intr>;
			interrupts = <57 256 IRQ_TYPE_EDGE_RISING>,
					<57 257 IRQ_TYPE_EDGE_RISING>,
					<57 258 IRQ_TYPE_EDGE_RISING>,
					<57 259 IRQ_TYPE_EDGE_RISING>,
					<57 260 IRQ_TYPE_EDGE_RISING>,
					<57 261 IRQ_TYPE_EDGE_RISING>;
			interrupt-controller;
			#interrupt-cells = <2>;
			ti,ngpio = <96>;
			ti,davinci-gpio-unbanked = <0>;
			clocks = <&k3_clks 57 0>;
			clock-names = "gpio";
		};

		main_gpio1:  main_gpio1@601000 {
			compatible = "ti,k2g-gpio", "ti,keystone-gpio";
			reg = <0x0 0x601000 0x0 0x100>;
			gpio-controller;
			#gpio-cells = <2>;

			interrupt-parent = <&main_intr>;
			interrupts = <58 256 IRQ_TYPE_EDGE_RISING>,
					<58 257 IRQ_TYPE_EDGE_RISING>,
					<58 258 IRQ_TYPE_EDGE_RISING>,
					<58 259 IRQ_TYPE_EDGE_RISING>,
					<58 260 IRQ_TYPE_EDGE_RISING>,
					<58 261 IRQ_TYPE_EDGE_RISING>;
			interrupt-controller;
			#interrupt-cells = <2>;
			ti,ngpio = <90>;
			ti,davinci-gpio-unbanked = <0>;
			clocks = <&k3_clks 58 0>;
			clock-names = "gpio";
		};

		wkup_gpio0: wkup_gpio0:@42110000 {
			compatible = "ti,k2g-gpio", "ti,keystone-gpio";
			reg = <0x0 0x42110000 0x0 0x100>;
			gpio-controller;
			#gpio-cells = <2>;

			interrupt-parent = <&wkup_intr>;
			interrupts = <59 128 IRQ_TYPE_EDGE_RISING>,
					<59 129 IRQ_TYPE_EDGE_RISING>,
					<59 130 IRQ_TYPE_EDGE_RISING>,
					<59 131 IRQ_TYPE_EDGE_RISING>;
			interrupt-controller;
			#interrupt-cells = <2>;
			ti,ngpio = <56>;
			ti,davinci-gpio-unbanked = <0>;
			clocks = <&k3_clks 59 0>;
			clock-names = "gpio";
		};

		gpu: gpu@7000000 {
			compatible = "ti,am654-sgx544", "img,sgx544";
			reg = <0x0 0x7000000 0x0 0x10000>;
			interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>;
			power-domains = <&k3_pds 65>;
			clocks = <&k3_clks 65 0>, <&k3_clks 65 1>,
				 <&k3_clks 65 2>, <&k3_clks 65 3>;
			clock-names = "mem_clk", "hyd_clk",
				      "sgx_clk", "sys_clk";
			status = "disabled";
		};

		hwspinlock: spinlock@30e00000 {
			compatible = "ti,am654-hwspinlock";
			reg = <0x0 0x30e00000 0x0 0x1000>;
			#hwlock-cells = <1>;
		};

		mailbox0: mailbox@31f80000 {
			compatible = "ti,am654-mailbox";
			reg = <0x0 0x31f80000 0x0 0x200>;
			#mbox-cells = <1>;
			ti,mbox-num-users = <4>;
			ti,mbox-num-fifos = <16>;
			interrupt-parent = <&main_navss_intr>;
			interrupts = <164 0 IRQ_TYPE_LEVEL_HIGH>;

			mbox_mcu_r5f0_ipc3x: mbox-mcu-r5f0-ipc3x {
				ti,mbox-tx = <1 0 0>;
				ti,mbox-rx = <0 0 0>;
			};
		};

		mailbox1: mailbox@31f81000 {
			compatible = "ti,am654-mailbox";
			reg = <0x0 0x31f81000 0x0 0x200>;
			#mbox-cells = <1>;
			ti,mbox-num-users = <4>;
			ti,mbox-num-fifos = <16>;
			interrupt-parent = <&main_navss_intr>;
			interrupts = <165 0 IRQ_TYPE_LEVEL_HIGH>;

			mbox_mcu_r5f1_ipc3x: mbox-mcu-r5f1-ipc3x {
				ti,mbox-tx = <1 0 0>;
				ti,mbox-rx = <0 0 0>;
			};
		};

		mailbox2: mailbox@31f82000 {
			compatible = "ti,am654-mailbox";
			reg = <0x0 0x31f82000 0x0 0x200>;
			#mbox-cells = <1>;
			ti,mbox-num-users = <4>;
			ti,mbox-num-fifos = <16>;
			status = "disabled";
		};

		mailbox3: mailbox@31f83000 {
			compatible = "ti,am654-mailbox";
			reg = <0x0 0x31f83000 0x0 0x200>;
			#mbox-cells = <1>;
			ti,mbox-num-users = <4>;
			ti,mbox-num-fifos = <16>;
			status = "disabled";
		};

		mailbox4: mailbox@31f84000 {
			compatible = "ti,am654-mailbox";
			reg = <0x0 0x31f84000 0x0 0x200>;
			#mbox-cells = <1>;
			ti,mbox-num-users = <4>;
			ti,mbox-num-fifos = <16>;
			status = "disabled";
		};

		mailbox5: mailbox@31f85000 {
			compatible = "ti,am654-mailbox";
			reg = <0x0 0x31f85000 0x0 0x200>;
			#mbox-cells = <1>;
			ti,mbox-num-users = <4>;
			ti,mbox-num-fifos = <16>;
			status = "disabled";
		};

		mailbox6: mailbox@31f86000 {
			compatible = "ti,am654-mailbox";
			reg = <0x0 0x31f86000 0x0 0x200>;
			#mbox-cells = <1>;
			ti,mbox-num-users = <4>;
			ti,mbox-num-fifos = <16>;
			status = "disabled";
		};

		mailbox7: mailbox@31f87000 {
			compatible = "ti,am654-mailbox";
			reg = <0x0 0x31f87000 0x0 0x200>;
			#mbox-cells = <1>;
			ti,mbox-num-users = <4>;
			ti,mbox-num-fifos = <16>;
			status = "disabled";
		};

		mailbox8: mailbox@31f88000 {
			compatible = "ti,am654-mailbox";
			reg = <0x0 0x31f88000 0x0 0x200>;
			#mbox-cells = <1>;
			ti,mbox-num-users = <4>;
			ti,mbox-num-fifos = <16>;
			status = "disabled";
		};

		mailbox9: mailbox@31f89000 {
			compatible = "ti,am654-mailbox";
			reg = <0x0 0x31f89000 0x0 0x200>;
			#mbox-cells = <1>;
			ti,mbox-num-users = <4>;
			ti,mbox-num-fifos = <16>;
			status = "disabled";
		};

		mailbox10: mailbox@31f8a000 {
			compatible = "ti,am654-mailbox";
			reg = <0x0 0x31f8a000 0x0 0x200>;
			#mbox-cells = <1>;
			ti,mbox-num-users = <4>;
			ti,mbox-num-fifos = <16>;
			status = "disabled";
		};

		mailbox11: mailbox@31f8b000 {
			compatible = "ti,am654-mailbox";
			reg = <0x0 0x31f8b000 0x0 0x200>;
			#mbox-cells = <1>;
			ti,mbox-num-users = <4>;
			ti,mbox-num-fifos = <16>;
			status = "disabled";
		};

		mcu_ram: mcu-ram@41c00000 {
			compatible = "mmio-sram";
			reg = <0x0 0x41c00000 0x0 0x80000>;
			ranges = <0x0 0x0 0x41c00000 0x80000>;
			#address-cells = <1>;
			#size-cells = <1>;
		};

		mcu_r5f_cluster: mcu_r5f_cluster@41000000 {
			compatible = "ti,am654-mcu-r5f";
			lockstep-mode = <1>;
			#address-cells = <1>;
			#size-cells = <1>;
			ranges = <0x41000000 0x0 0x41000000 0x20000>,
				 <0x41400000 0x0 0x41400000 0x20000>;
			power-domains = <&k3_pds 129>;

			mcu_r5f0: r5f@41000000 {
				compatible = "ti,am654-r5f";
				reg = <0x41000000 0x00008000>,
				      <0x41010000 0x00008000>;
				reg-names = "atcm", "btcm";
				ti,sci = <&dmsc>;
				ti,sci-dev-id = <159>;
				ti,sci-proc-ids = <0x01 0xFF>;
				resets = <&k3_reset 159 1>;
				atcm-enable = <1>;
				btcm-enable = <1>;
				loczrama = <1>;
				mboxes = <&mailbox0 &mbox_mcu_r5f0_ipc3x>;
			};

			mcu_r5f1: r5f@41400000 {
				compatible = "ti,am654-r5f";
				reg = <0x41400000 0x00008000>,
				      <0x41410000 0x00008000>;
				reg-names = "atcm", "btcm";
				ti,sci = <&dmsc>;
				ti,sci-dev-id = <245>;
				ti,sci-proc-ids = <0x02 0xFF>;
				resets = <&k3_reset 245 1>;
				atcm-enable = <1>;
				btcm-enable = <1>;
				loczrama = <1>;
				mboxes = <&mailbox1 &mbox_mcu_r5f1_ipc3x>;
			};
		};

		icssg_soc_bus0: pruss_soc_bus@b026004 {
			compatible = "ti,am654-icssg-soc-bus";
			reg = <0x0 0x0b026004 0x0 0x4>;
			power-domains = <&k3_pds 62>;
			#address-cells = <1>;
			#size-cells = <1>;
			ranges = <0x0 0x0 0x0b000000 0x100000>;
			dma-ranges;

			icssg0: icssg@0 {
				compatible = "ti,am654-icssg";
				reg = <0x0 0x80000>;
				interrupts = <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>,
					     <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>,
					     <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,
					     <GIC_SPI 257 IRQ_TYPE_LEVEL_HIGH>,
					     <GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH>,
					     <GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH>,
					     <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>,
					     <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>;
				interrupt-names = "host2", "host3", "host4",
						  "host5", "host6", "host7",
						  "host8", "host9";
				#address-cells = <1>;
				#size-cells = <1>;
				ranges;
				dma-ranges;

				icssg0_mem: memories@0 {
					reg = <0x0 0x2000>,
					      <0x2000 0x2000>,
					      <0x10000 0x10000>;
					reg-names = "dram0", "dram1",
						    "shrdram2";
				};

				icssg0_cfg: cfg@26000 {
					compatible = "syscon";
					reg = <0x26000 0x200>;
				};

				icssg0_iep: iep@2e000 {
					compatible = "syscon";
					reg = <0x2e000 0x1000>;
				};

				icssg0_mii_rt: mii_rt@32000 {
					compatible = "syscon";
					reg = <0x32000 0x100>;
				};

				icssg0_mii_g_rt: mii_g_rt@33000 {
					compatible = "syscon";
					reg = <0x33000 0x1000>;
				};

				icssg0_intc: intc@20000 {
					compatible = "ti,am654-icssg-intc";
					reg = <0x20000 0x2000>;
					reg-names = "intc";
					interrupt-controller;
					#interrupt-cells = <1>;
				};

				pru0_0: pru@34000 {
					compatible = "ti,am654-pru";
					reg = <0x34000 0x4000>,
					      <0x22000 0x100>,
					      <0x22400 0x100>;
					reg-names = "iram", "control", "debug";
					firmware-name = "am65x-pru0_0-fw";
					interrupt-parent = <&icssg0_intc>;
					interrupts = <16>, <17>;
					interrupt-names = "vring", "kick";
				};

				rtu0_0: rtu@4000 {
					compatible = "ti,am654-rtu";
					reg = <0x4000 0x2000>,
					      <0x23000 0x100>,
					      <0x23400 0x100>;
					reg-names = "iram", "control", "debug";
					firmware-name = "am65x-rtu0_0-fw";
					interrupt-parent = <&icssg0_intc>;
					interrupts = <20>, <21>;
					interrupt-names = "vring", "kick";
				};

				pru0_1: pru@38000 {
					compatible = "ti,am654-pru";
					reg = <0x38000 0x4000>,
					      <0x24000 0x100>,
					      <0x24400 0x100>;
					reg-names = "iram", "control", "debug";
					firmware-name = "am65x-pru0_1-fw";
					interrupt-parent = <&icssg0_intc>;
					interrupts = <18>, <19>;
					interrupt-names = "vring", "kick";
				};

				rtu0_1: rtu@6000 {
					compatible = "ti,am654-rtu";
					reg = <0x6000 0x2000>,
					      <0x23800 0x100>,
					      <0x23c00 0x100>;
					reg-names = "iram", "control", "debug";
					firmware-name = "am65x-rtu0_1-fw";
					interrupt-parent = <&icssg0_intc>;
					interrupts = <22>, <23>;
					interrupt-names = "vring", "kick";
				};

				icssg0_mdio: mdio@32400 {
					compatible = "ti,davinci_mdio";
					reg = <0x32400 0x100>;
					clocks = <&k3_clks 62 3>;
					clock-names = "fck";
					#address-cells = <1>;
					#size-cells = <0>;
					bus_freq = <1000000>;
					status = "disabled";
				};
			};
		};

		icssg_soc_bus1: pruss_soc_bus@b126004 {
			compatible = "ti,am654-icssg-soc-bus";
			reg = <0x0 0x0b126004 0x0 0x4>;
			power-domains = <&k3_pds 63>;
			#address-cells = <1>;
			#size-cells = <1>;
			ranges = <0x0 0x0 0x0b100000 0x100000>;
			dma-ranges;

			icssg1: icssg@0 {
				compatible = "ti,am654-icssg";
				reg = <0x0 0x80000>;
				interrupts = <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>,
					     <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>,
					     <GIC_SPI 264 IRQ_TYPE_LEVEL_HIGH>,
					     <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>,
					     <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>,
					     <GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>,
					     <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>,
					     <GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH>;
				interrupt-names = "host2", "host3", "host4",
						  "host5", "host6", "host7",
						  "host8", "host9";
				#address-cells = <1>;
				#size-cells = <1>;
				ranges;
				dma-ranges;

				icssg1_mem: memories@0 {
					reg = <0x0 0x2000>,
					      <0x2000 0x2000>,
					      <0x10000 0x10000>;
					reg-names = "dram0", "dram1",
						    "shrdram2";
				};

				icssg1_cfg: cfg@26000 {
					compatible = "syscon";
					reg = <0x26000 0x200>;
				};

				icssg1_iep: iep@2e000 {
					compatible = "syscon";
					reg = <0x2e000 0x1000>;
				};

				icssg1_mii_rt: mii_rt@32000 {
					compatible = "syscon";
					reg = <0x32000 0x100>;
				};

				icssg1_mii_g_rt: mii_g_rt@33000 {
					compatible = "syscon";
					reg = <0x33000 0x1000>;
				};

				icssg1_intc: intc@20000 {
					compatible = "ti,am654-icssg-intc";
					reg = <0x20000 0x2000>;
					reg-names = "intc";
					interrupt-controller;
					#interrupt-cells = <1>;
				};

				pru1_0: pru@34000 {
					compatible = "ti,am654-pru";
					reg = <0x34000 0x4000>,
					      <0x22000 0x100>,
					      <0x22400 0x100>;
					reg-names = "iram", "control", "debug";
					firmware-name = "am65x-pru1_0-fw";
					interrupt-parent = <&icssg1_intc>;
					interrupts = <16>, <17>;
					interrupt-names = "vring", "kick";
				};

				rtu1_0: rtu@4000 {
					compatible = "ti,am654-rtu";
					reg = <0x4000 0x2000>,
					      <0x23000 0x100>,
					      <0x23400 0x100>;
					reg-names = "iram", "control", "debug";
					firmware-name = "am65x-rtu1_0-fw";
					interrupt-parent = <&icssg1_intc>;
					interrupts = <20>, <21>;
					interrupt-names = "vring", "kick";
				};

				pru1_1: pru@38000 {
					compatible = "ti,am654-pru";
					reg = <0x38000 0x4000>,
					      <0x24000 0x100>,
					      <0x24400 0x100>;
					reg-names = "iram", "control", "debug";
					firmware-name = "am65x-pru1_1-fw";
					interrupt-parent = <&icssg1_intc>;
					interrupts = <18>, <19>;
					interrupt-names = "vring", "kick";
				};

				rtu1_1: rtu@6000 {
					compatible = "ti,am654-rtu";
					reg = <0x6000 0x2000>,
					      <0x23800 0x100>,
					      <0x23c00 0x100>;
					reg-names = "iram", "control", "debug";
					firmware-name = "am65x-rtu1_1-fw";
					interrupt-parent = <&icssg1_intc>;
					interrupts = <22>, <23>;
					interrupt-names = "vring", "kick";
				};

				icssg1_mdio: mdio@32400 {
					compatible = "ti,davinci_mdio";
					reg = <0x32400 0x100>;
					clocks = <&k3_clks 63 3>;
					clock-names = "fck";
					#address-cells = <1>;
					#size-cells = <0>;
					bus_freq = <1000000>;
					status = "disabled";
				};
			};
		};

		icssg_soc_bus2: pruss_soc_bus@b226004 {
			compatible = "ti,am654-icssg-soc-bus";
			reg = <0x0 0x0b226004 0x0 0x4>;
			power-domains = <&k3_pds 64>;
			#address-cells = <1>;
			#size-cells = <1>;
			ranges = <0x0 0x0 0x0b200000 0x100000>;
			dma-ranges;

			icssg2: icssg@0 {
				compatible = "ti,am654-icssg";
				reg = <0x0 0x80000>;
				interrupts = <GIC_SPI 270 IRQ_TYPE_LEVEL_HIGH>,
					     <GIC_SPI 271 IRQ_TYPE_LEVEL_HIGH>,
					     <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>,
					     <GIC_SPI 273 IRQ_TYPE_LEVEL_HIGH>,
					     <GIC_SPI 274 IRQ_TYPE_LEVEL_HIGH>,
					     <GIC_SPI 275 IRQ_TYPE_LEVEL_HIGH>,
					     <GIC_SPI 276 IRQ_TYPE_LEVEL_HIGH>,
					     <GIC_SPI 277 IRQ_TYPE_LEVEL_HIGH>;
				interrupt-names = "host2", "host3", "host4",
						  "host5", "host6", "host7",
						  "host8", "host9";
				#address-cells = <1>;
				#size-cells = <1>;
				ranges;
				dma-ranges;

				icssg2_mem: memories@0 {
					reg = <0x0 0x2000>,
					      <0x2000 0x2000>,
					      <0x10000 0x10000>;
					reg-names = "dram0", "dram1",
						    "shrdram2";
				};

				icssg2_cfg: cfg@26000 {
					compatible = "syscon";
					reg = <0x26000 0x200>;
				};

				icssg2_iep: iep@2e000 {
					compatible = "syscon";
					reg = <0x2e000 0x1000>;
				};

				icssg2_mii_rt: mii_rt@32000 {
					compatible = "syscon";
					reg = <0x32000 0x100>;
				};

				icssg2_mii_g_rt: mii_g_rt@33000 {
					compatible = "syscon";
					reg = <0x33000 0x1000>;
				};

				icssg2_intc: intc@20000 {
					compatible = "ti,am654-icssg-intc";
					reg = <0x20000 0x2000>;
					reg-names = "intc";
					interrupt-controller;
					#interrupt-cells = <1>;
				};

				pru2_0: pru@34000 {
					compatible = "ti,am654-pru";
					reg = <0x34000 0x4000>,
					      <0x22000 0x100>,
					      <0x22400 0x100>;
					reg-names = "iram", "control", "debug";
					firmware-name = "am65x-pru2_0-fw";
					interrupt-parent = <&icssg2_intc>;
					interrupts = <16>, <17>;
					interrupt-names = "vring", "kick";
				};

				rtu2_0: rtu@4000 {
					compatible = "ti,am654-rtu";
					reg = <0x4000 0x2000>,
					      <0x23000 0x100>,
					      <0x23400 0x100>;
					reg-names = "iram", "control", "debug";
					firmware-name = "am65x-rtu2_0-fw";
					interrupt-parent = <&icssg2_intc>;
					interrupts = <20>, <21>;
					interrupt-names = "vring", "kick";
				};

				pru2_1: pru@38000 {
					compatible = "ti,am654-pru";
					reg = <0x38000 0x4000>,
					      <0x24000 0x100>,
					      <0x24400 0x100>;
					reg-names = "iram", "control", "debug";
					firmware-name = "am65x-pru2_1-fw";
					interrupt-parent = <&icssg2_intc>;
					interrupts = <18>, <19>;
					interrupt-names = "vring", "kick";
				};

				rtu2_1: rtu@6000 {
					compatible = "ti,am654-rtu";
					reg = <0x6000 0x2000>,
					      <0x23800 0x100>,
					      <0x23c00 0x100>;
					reg-names = "iram", "control", "debug";
					firmware-name = "am65x-rtu2_1-fw";
					interrupt-parent = <&icssg2_intc>;
					interrupts = <22>, <23>;
					interrupt-names = "vring", "kick";
				};

				icssg2_mdio: mdio@32400 {
					compatible = "ti,davinci_mdio";
					reg = <0x32400 0x100>;
					clocks = <&k3_clks 64 3>;
					clock-names = "fck";
					#address-cells = <1>;
					#size-cells = <0>;
					bus_freq = <1000000>;
					status = "disabled";
				};
			};
		};

		main_navss: main_navss {
			compatible = "simple-bus";
			#address-cells = <2>;
			#size-cells = <2>;
			dma-coherent;
			dma-ranges;
			ranges;

			ti,sci-dev-id = <118>;

			main_navss_intr: interrupt-controller@0 {
				compatible = "ti,sci-intr";
				interrupt-controller;
				interrupt-parent = <&gic>;
				#interrupt-cells = <3>;
				ti,sci = <&dmsc>;
				ti,sci-dst-id = <56>;
				ti,sci-dst-irq-type = <0xb 0x0>,
						      <0xb 0x2>;
			};

			main_udmass_inta: interrupt-controller@33d00000 {
				compatible = "ti,sci-inta";
				reg = <0x0 0x33d00000 0x0 0x100000>;
				interrupt-controller;
				interrupt-parent = <&main_navss_intr>;
				#interrupt-cells = <3>;
				ti,sci = <&dmsc>;
				ti,sci-dev-id = <179>;
				ti,sci-vint-type = <0x0 0x0>;
				ti,sci-global-event-type = <0x0 0x1>;
			};

			ringacc: ringacc@3c000000 {
				compatible = "ti,am654-navss-ringacc";
				reg =	<0x0 0x3c000000 0x0 0x400000>,
					<0x0 0x38000000 0x0 0x400000>,
					<0x0 0x31120000 0x0 0x100>,
					<0x0 0x33000000 0x0 0x40000>;
				reg-names = "rt", "fifos",
					    "proxy_gcfg", "proxy_target";
				ti,num-rings = <818>;
				ti,gp-rings = <304 464>; /* start, cnt */
				ti,dma-ring-reset-quirk;
				ti,sci = <&dmsc>;
				ti,sci-dev-id = <187>;
				interrupt-parent = <&main_udmass_inta>;
			};

			main_udmap: udmap@31150000 {
				compatible = "ti,am654-navss-main-udmap";
				reg =	<0x0 0x31150000 0x0 0x100>,
					<0x0 0x34000000 0x0 0x100000>,
					<0x0 0x35000000 0x0 0x100000>;
				reg-names = "gcfg", "rchanrt", "tchanrt";
				#dma-cells = <3>;

				ti,ringacc = <&ringacc>;
				ti,psil-base = <0x1000>;

				interrupt-parent = <&main_udmass_inta>;

				ti,sci = <&dmsc>;
				ti,sci-dev-id = <188>;

				ti,sci-rm-range-tchan = <0x6 0x1>, /* TX_HCHAN */
							<0x6 0x2>; /* TX_CHAN */
				ti,sci-rm-range-rchan = <0x6 0x4>, /* RX_HCHAN */
							<0x6 0x5>; /* RX_CHAN */
				ti,sci-rm-range-rflow = <0x6 0x6>; /* GP RFLOW */
			};

			cpts@310d0000 {
				compatible = "ti,am65-cpts";
				reg = <0x0 0x310d0000 0x0 0x400>;
				reg-names = "cpts";
				clocks = <&main_cpts_mux>;
				clock-names = "cpts";
				interrupts-extended = <&main_navss_intr 163 0 IRQ_TYPE_LEVEL_HIGH>;
				interrupt-names = "cpts";
				ti,cpts-periodic-outputs = <6>;
				ti,cpts-ext-ts-inputs = <8>;

				main_cpts_mux: cpts_refclk_mux {
					#clock-cells = <0>;
					clocks = <&k3_clks 118 5>, <&k3_clks 118 11>,
						<&k3_clks 157 91>, <&k3_clks 157 77>,
						<&k3_clks 157 102>, <&k3_clks 157 80>,
						<&k3_clks 120 3>, <&k3_clks 121 3>;
					cpts-mux-tbl = <0>, <1>;
					assigned-clocks = <&main_cpts_mux>;
					assigned-clock-parents = <&k3_clks 118 5>;
				};
			};
		};

		cpsw-phy-sel@40f04040 {
			compatible = "ti,am654-cpsw-phy-sel";
			reg= <0x0 0x40f04040 0x0 0x4>;
			reg-names = "gmii-sel";
		};

		mcu_cpsw: ethernet@046000000 {
			compatible = "ti,am654-cpsw-nuss";
			#address-cells = <2>;
			#size-cells = <2>;
			reg = <0x0 0x46000000 0x0 0x200000>;
			reg-names = "cpsw_nuss";
			ranges;
			dma-coherent;
			clocks = <&k3_clks 5 10>;
			clock-names = "fck";
			power-domains = <&k3_pds 5>;
			ti,psil-base = <0x7000>;

			interrupt-parent = <&main_udmass_inta>;

			dmas = <&mcu_udmap &mcu_cpsw 0 UDMA_DIR_TX>,
			       <&mcu_udmap &mcu_cpsw 1 UDMA_DIR_TX>,
			       <&mcu_udmap &mcu_cpsw 2 UDMA_DIR_TX>,
			       <&mcu_udmap &mcu_cpsw 3 UDMA_DIR_TX>,
			       <&mcu_udmap &mcu_cpsw 4 UDMA_DIR_TX>,
			       <&mcu_udmap &mcu_cpsw 5 UDMA_DIR_TX>,
			       <&mcu_udmap &mcu_cpsw 6 UDMA_DIR_TX>,
			       <&mcu_udmap &mcu_cpsw 7 UDMA_DIR_TX>,
			       <&mcu_udmap &mcu_cpsw 0 UDMA_DIR_RX>;
			dma-names = "tx0", "tx1", "tx2", "tx3",
				    "tx4", "tx5", "tx6", "tx7",
				    "rx";

			ports {
				#address-cells = <1>;
				#size-cells = <0>;

				host: host@0 {
					reg = <0>;
					ti,label = "host";
				};

				cpsw_port1: port@1 {
					reg = <1>;
					ti,mac-only;
					ti,label = "port1";
					ti,syscon-efuse = <&mcu_conf 0x200>;
				};
			};

			davinci_mdio: mdio {
				#address-cells = <1>;
				#size-cells = <0>;
				bus_freq = <1000000>;
			};

			cpts {
				clocks = <&mcu_cpsw_cpts_mux>;
				clock-names = "cpts";
				interrupts-extended = <&gic GIC_SPI 570 IRQ_TYPE_LEVEL_HIGH>;
				interrupt-names = "cpts";
				ti,cpts-ext-ts-inputs = <4>;
				ti,cpts-periodic-outputs = <2>;

				mcu_cpsw_cpts_mux: cpts_refclk_mux {
					#clock-cells = <0>;
					clocks = <&k3_clks 118 5>, <&k3_clks 118 11>,
						<&k3_clks 157 91>, <&k3_clks 157 77>,
						<&k3_clks 157 102>, <&k3_clks 157 80>,
						<&k3_clks 120 3>, <&k3_clks 121 3>;
					assigned-clocks = <&mcu_cpsw_cpts_mux>;
					assigned-clock-parents = <&k3_clks 118 5>;
				};
			};

			ti,psil-config0 {
				linux,udma-mode = <UDMA_PKT_MODE>;
				statictr-type = <PSIL_STATIC_TR_NONE>;
				ti,needs-epib;
				ti,psd-size = <16>;
			};

			ti,psil-config1 {
				linux,udma-mode = <UDMA_PKT_MODE>;
				statictr-type = <PSIL_STATIC_TR_NONE>;
				ti,needs-epib;
				ti,psd-size = <16>;
			};

			ti,psil-config2 {
				linux,udma-mode = <UDMA_PKT_MODE>;
				statictr-type = <PSIL_STATIC_TR_NONE>;
				ti,needs-epib;
				ti,psd-size = <16>;
			};

			ti,psil-config3 {
				linux,udma-mode = <UDMA_PKT_MODE>;
				statictr-type = <PSIL_STATIC_TR_NONE>;
				ti,needs-epib;
				ti,psd-size = <16>;
			};

			ti,psil-config4 {
				linux,udma-mode = <UDMA_PKT_MODE>;
				statictr-type = <PSIL_STATIC_TR_NONE>;
				ti,needs-epib;
				ti,psd-size = <16>;
			};

			ti,psil-config5 {
				linux,udma-mode = <UDMA_PKT_MODE>;
				statictr-type = <PSIL_STATIC_TR_NONE>;
				ti,needs-epib;
				ti,psd-size = <16>;
			};

			ti,psil-config6 {
				linux,udma-mode = <UDMA_PKT_MODE>;
				statictr-type = <PSIL_STATIC_TR_NONE>;
				ti,needs-epib;
				ti,psd-size = <16>;
			};

			ti,psil-config7 {
				linux,udma-mode = <UDMA_PKT_MODE>;
				statictr-type = <PSIL_STATIC_TR_NONE>;
				ti,needs-epib;
				ti,psd-size = <16>;
			};
		};

		mcu_navss: mcu_navss {
			compatible = "simple-bus";
			#address-cells = <2>;
			#size-cells = <2>;
			dma-coherent;
			dma-ranges;
			ranges;

			ti,sci-dev-id = <119>;

			mcu_ringacc: ringacc@2b800000 {
				compatible = "ti,am654-navss-ringacc";
				reg =	<0x0 0x2b800000 0x0 0x400000>,
					<0x0 0x2b000000 0x0 0x400000>,
					<0x0 0x28590000 0x0 0x100>,
					<0x0 0x2a500000 0x0 0x40000>;
				reg-names = "rt", "fifos",
					    "proxy_gcfg", "proxy_target";
				ti,num-rings = <286>;
				ti,gp-rings = <96 255>; /* start, cnt */
				ti,dma-ring-reset-quirk;
				ti,sci = <&dmsc>;
				ti,sci-dev-id = <195>;
				interrupt-parent = <&main_udmass_inta>;
			};

			mcu_udmap: udmap@31150000 {
				compatible = "ti,am654-navss-mcu-udmap";
				reg =	<0x0 0x285c0000 0x0 0x100>,
					<0x0 0x2a800000 0x0 0x40000>,
					<0x0 0x2aa00000 0x0 0x40000>;
				reg-names = "gcfg", "rchanrt", "tchanrt";
				#dma-cells = <3>;

				ti,ringacc = <&mcu_ringacc>;
				ti,psil-base = <0x6000>;

				ti,sci = <&dmsc>;
				ti,sci-dev-id = <194>;

				ti,sci-rm-range-tchan = <0x7 0x1>, /* TX_HCHAN */
							<0x7 0x2>; /* TX_CHAN */
				ti,sci-rm-range-rchan = <0x7 0x3>, /* RX_HCHAN */
							<0x7 0x4>; /* RX_CHAN */
				ti,sci-rm-range-rflow = <0x7 0x5>; /* GP RFLOW */

				interrupt-parent = <&main_udmass_inta>;
			};
		};

		mcu_pdma0: pdma@40710000 {
			compatible = "ti,am654-pdma";
			reg = <0x0 0x40710000 0x0 0x400>;
			reg-names = "eccaggr_cfg";

			ti,psil-base = <0x7100>;

			/* ti,psil-config0-3 */
			UDMA_PDMA_TR_XY(0);
			UDMA_PDMA_TR_XY(1);
			UDMA_PDMA_TR_XY(2);
			UDMA_PDMA_TR_XY(3);
		};

		mcu_pdma1: pdma@40711000 {
			compatible = "ti,am654-pdma";
			reg = <0x0 0x40711000 0x0 0x400>;
			reg-names = "eccaggr_cfg";

			ti,psil-base = <0x7200>;

			/* ti,psil-config18 */
			UDMA_PDMA_PKT_XY(18);
		};

		pdma0: pdma@2a41000 {
			compatible = "ti,am654-pdma";
			reg = <0x0 0x02A41000 0x0 0x400>;
			reg-names = "eccaggr_cfg";

			ti,psil-base = <0x4400>;

			/* ti,psil-config0-2 */
			UDMA_PDMA_TR_XY(0);
			UDMA_PDMA_TR_XY(1);
			UDMA_PDMA_TR_XY(2);
		};

		pdma1: pdma@2a42000 {
			compatible = "ti,am654-pdma";
			reg = <0x0 0x02A42000 0x0 0x400>;
			reg-names = "eccaggr_cfg";

			ti,psil-base = <0x4500>;

			/* ti,psil-config0-22 */
			UDMA_PDMA_TR_XY(0);
			UDMA_PDMA_TR_XY(1);
			UDMA_PDMA_TR_XY(2);
			UDMA_PDMA_TR_XY(3);
			UDMA_PDMA_TR_XY(4);
			UDMA_PDMA_TR_XY(5);
			UDMA_PDMA_TR_XY(6);
			UDMA_PDMA_TR_XY(7);
			UDMA_PDMA_TR_XY(8);
			UDMA_PDMA_TR_XY(9);
			UDMA_PDMA_TR_XY(10);
			UDMA_PDMA_TR_XY(11);
			UDMA_PDMA_TR_XY(12);
			UDMA_PDMA_TR_XY(13);
			UDMA_PDMA_TR_XY(14);
			UDMA_PDMA_TR_XY(15);
			UDMA_PDMA_TR_XY(16);
			UDMA_PDMA_TR_XY(17);
			UDMA_PDMA_TR_XY(18);
			UDMA_PDMA_TR_XY(19);
			UDMA_PDMA_PKT_XY(20);
			UDMA_PDMA_PKT_XY(21);
			UDMA_PDMA_PKT_XY(22);
		};

		mcasp0: mcasp@02B00000 {
			compatible = "ti,am33xx-mcasp-audio";
			reg = <0x0 0x02B00000 0x0 0x2000>,
			      <0x0 0x02B08000 0x0 0x1000>;
			reg-names = "mpu","dat";
			interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>;
			interrupt-names = "tx", "rx";

			/* tx: pdma0-0, rx: pdma0-0 */
			dmas = <&main_udmap &pdma0 0 UDMA_DIR_TX>,
			       <&main_udmap &pdma0 0 UDMA_DIR_RX>;
			dma-names = "tx", "rx";

			clocks = <&k3_clks 104 0>;
			clock-names = "fck";
			power-domains = <&k3_pds 104>;

			status = "disabled";
		};

		mcasp1: mcasp@02B10000 {
			compatible = "ti,am33xx-mcasp-audio";
			reg = <0x0 0x02B10000 0x0 0x2000>,
			      <0x0 0x02B18000 0x0 0x1000>;
			reg-names = "mpu","dat";
			interrupts = <GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>;
			interrupt-names = "tx", "rx";

			/* tx: pdma0-1, rx: pdma0-1 */
			dmas = <&main_udmap &pdma0 1 UDMA_DIR_TX>,
			       <&main_udmap &pdma0 1 UDMA_DIR_RX>;
			dma-names = "tx", "rx";

			clocks = <&k3_clks 105 0>;
			clock-names = "fck";
			power-domains = <&k3_pds 105>;

			status = "disabled";
		};

		mcasp2: mcasp@02B20000 {
			compatible = "ti,am33xx-mcasp-audio";
			reg = <0x0 0x02B20000 0x0 0x2000>,
			      <0x0 0x02B28000 0x0 0x1000>;
			reg-names = "mpu","dat";
			interrupts = <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>;
			interrupt-names = "tx", "rx";

			/* tx: pdma0-1, rx: pdma0-1 */
			dmas = <&main_udmap &pdma0 2 UDMA_DIR_TX>,
			       <&main_udmap &pdma0 2 UDMA_DIR_RX>;
			dma-names = "tx", "rx";

			clocks = <&k3_clks 106 0>;
			clock-names = "fck";
			power-domains = <&k3_pds 106>;

			status = "disabled";
		};

		eip76d_trng: trng@4e10000 {
			compatible = "inside-secure,safexcel-eip76";
			reg = <0x0 0x4e10000 0x0 0x7d>;
			interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&k3_clks 136 1>;
		};

		crypto: crypto@4E00000 {
			compatible = "ti,sa2ul-crypto";
			label = "crypto-aes-gbe";
			reg = <0x0 0x4E00000 0x0 0x1200>;

			status = "okay";
			ti,psil-base = <0x4000>;

			/* tx: crypto_pnp-1, rx: crypto_pnp-1 */
			dmas = <&main_udmap &crypto 0 UDMA_DIR_TX>,
					<&main_udmap &crypto 0 UDMA_DIR_RX>,
					<&main_udmap &crypto 1 UDMA_DIR_RX>;
			dma-names = "tx", "rx1", "rx2";

			ti,psil-config0 {
				linux,udma-mode = <UDMA_PKT_MODE>;
				ti,needs-epib;
				ti,psd-size = <64>;
			};

			ti,psil-config1 {
				linux,udma-mode = <UDMA_PKT_MODE>;
				ti,needs-epib;
				ti,psd-size = <64>;
			};

			ti,psil-config2 {
				linux,udma-mode = <UDMA_PKT_MODE>;
				ti,needs-epib;
				ti,psd-size = <64>;
			};
		};

		ecap0: pwm@3100000 {
			compatible = "ti,am654-ecap", "ti,am3352-ecap";
			#pwm-cells = <3>;
			reg = <0x0 0x03100000 0x0 0x60>;
			power-domains = <&k3_pds 39>;
			clocks = <&k3_clks 39 0>;
			clock-names = "fck";
			status = "disabled";
		};

		serdes0: serdes@900000 {
			compatible = "ti,phy-am654-serdes";
			reg = <0x0 0x900000 0x0 0x2000>;
			reg-names = "serdes";
			#phy-cells = <2>;
			power-domains = <&k3_pds 153>;
			clocks = <&k3_clks 153 4>, <&k3_clks 153 1>, <&serdes1 AM654_SERDES_LO_REFCLK>;
			clock-output-names = "serdes0_cmu_refclk", "serdes0_lo_refclk", "serdes0_ro_refclk";
			assigned-clocks = <&k3_clks 153 4>, <&serdes0 AM654_SERDES_CMU_REFCLK>;
			assigned-clock-parents = <&k3_clks 153 8>, <&k3_clks 153 4>;
			ti,serdes-clk = <&serdes0_clk>;
			mux-controls = <&serdes_mux 0>;
			#clock-cells = <1>;
			status = "disabled";
		};

		serdes1: serdes@910000 {
			compatible = "ti,phy-am654-serdes";
			reg = <0x0 0x910000 0x0 0x2000>;
			reg-names = "serdes";
			#phy-cells = <2>;
			power-domains = <&k3_pds 154>;
			clocks = <&serdes0 AM654_SERDES_RO_REFCLK>, <&k3_clks 154 1>, <&k3_clks 154 5>;
			clock-output-names = "serdes1_cmu_refclk", "serdes1_lo_refclk", "serdes1_ro_refclk";
			assigned-clocks = <&k3_clks 154 5>, <&serdes1 AM654_SERDES_CMU_REFCLK>;
			assigned-clock-parents = <&k3_clks 154 9>, <&k3_clks 154 5>;
			ti,serdes-clk = <&serdes1_clk>;
			mux-controls = <&serdes_mux 1>;
			#clock-cells = <1>;
			status = "disabled";
		};

		pcie0_rc: pcie@5500000 {
			compatible = "ti,am654-pcie-rc";
			reg =  <0x0 0x5500000 0x0 0x1000>, <0x0 0x5501000 0x0 0x1000>, <0x0 0x10000000 0x0 0x2000>, <0x0 0x5506000 0x0 0x1000>;
			reg-names = "app", "dbics", "config", "atu";
			power-domains = <&k3_pds 120>;
			#address-cells = <3>;
			#size-cells = <2>;
			ranges = <0x81000000 0 0          0x0   0x10020000 0 0x00010000
				  0x82000000 0 0x10030000 0x0   0x10030000 0 0x07FD0000>;
			ti,syscon-pcie-id = <&pcie_devid>;
			ti,syscon-pcie-mode = <&pcie0_mode>;
			bus-range = <0x0 0xff>;
			status = "disabled";
			device_type = "pci";
			num-lanes = <1>;
			num-ob-windows = <16>;
			num-viewport = <16>;
			max-link-speed = <3>;
			interrupts = <GIC_SPI 340 IRQ_TYPE_EDGE_RISING>;
			#interrupt-cells = <1>;
			interrupt-map-mask = <0 0 0 7>;
			interrupt-map = <0 0 0 1 &pcie0_intc 0>, /* INT A */
					<0 0 0 2 &pcie0_intc 0>, /* INT B */
					<0 0 0 3 &pcie0_intc 0>, /* INT C */
					<0 0 0 4 &pcie0_intc 0>; /* INT D */
			msi-map = <0x0 &gic_its 0x0 0x10000>;

			pcie0_intc: legacy-interrupt-controller@1 {
				interrupt-controller;
				#interrupt-cells = <1>;
				interrupt-parent = <&gic>;
				interrupts = <GIC_SPI 328 IRQ_TYPE_EDGE_RISING>;
			};
		};

		pcie0_ep: pcie-ep@5500000 {
			compatible = "ti,am654-pcie-ep";
			reg =  <0x0 0x5500000 0x0 0x1000>, <0x0 0x5501000 0x0 0x1000>, <0x0 0x10000000 0x0 0x8000000>, <0x0 0x5506000 0x0 0x1000>;
			reg-names = "app", "dbics", "addr_space", "atu";
			power-domains = <&k3_pds 120>;
			ti,syscon-pcie-mode = <&pcie0_mode>;
			status = "disabled";
			num-lanes = <1>;
			num-ib-windows = <16>;
			num-ob-windows = <16>;
			max-link-speed = <3>;
			interrupts = <GIC_SPI 340 IRQ_TYPE_EDGE_RISING>;
		};

		pcie1_rc: pcie-rc@5600000 {
			compatible = "ti,am654-pcie-rc";
			reg =  <0x0 0x5600000 0x0 0x1000>, <0x0 0x5601000 0x0 0x1000>, <0x0 0x18000000 0x0 0x2000>, <0x0 0x5606000 0x0 0x1000>;
			reg-names = "app", "dbics", "config", "atu";
			power-domains = <&k3_pds 121>;
			#address-cells = <3>;
			#size-cells = <2>;
			ranges = <0x81000000 0 0          0x0   0x18020000 0 0x00010000
				  0x82000000 0 0x18030000 0x0   0x18030000 0 0x07FD0000>;
			ti,syscon-pcie-id = <&pcie_devid>;
			ti,syscon-pcie-mode = <&pcie1_mode>;
			bus-range = <0x0 0xff>;
			status = "disabled";
			device_type = "pci";
			num-lanes = <1>;
			num-ob-windows = <16>;
			num-viewport = <16>;
			max-link-speed = <3>;
			interrupts = <GIC_SPI 355 IRQ_TYPE_EDGE_RISING>;
			#interrupt-cells = <1>;
			interrupt-map-mask = <0 0 0 7>;
			interrupt-map = <0 0 0 1 &pcie1_intc 0>, /* INT A */
					<0 0 0 2 &pcie1_intc 0>, /* INT B */
					<0 0 0 3 &pcie1_intc 0>, /* INT C */
					<0 0 0 4 &pcie1_intc 0>; /* INT D */
			msi-map = <0x0 &gic_its 0x10000 0x10000>;

			pcie1_intc: legacy-interrupt-controller@1 {
				interrupt-controller;
				#interrupt-cells = <1>;
				interrupt-parent = <&gic>;
				interrupts = <GIC_SPI 343 IRQ_TYPE_EDGE_RISING>;
			};
		};

		pcie1_ep: pcie-ep@5600000 {
			compatible = "ti,am654-pcie-ep";
			reg =  <0x0 0x5600000 0x0 0x1000>, <0x0 0x5601000 0x0 0x1000>, <0x0 0x18000000 0x0 0x4000000>, <0x0 0x5606000 0x0 0x1000>;
			reg-names = "app", "dbics", "addr_space", "atu";
			power-domains = <&k3_pds 121>;
			ti,syscon-pcie-mode = <&pcie1_mode>;
			status = "disabled";
			num-lanes = <1>;
			num-ib-windows = <16>;
			num-ob-windows = <16>;
			max-link-speed = <3>;
			interrupts = <GIC_SPI 355 IRQ_TYPE_EDGE_RISING>;
		};

		dwc3_0: dwc3@4000000 {
			compatible = "ti,am654-dwc3";
			reg = <0x0 0x4000000 0x0 0x4000>;
			#address-cells = <1>;
			#size-cells = <1>;
			ranges = <0x0 0x0 0x4000000 0x20000>;
			interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
			dma-coherent;
			status = "disabled";
			power-domains = <&k3_pds 151>;
			assigned-clocks = <&k3_clks 151 2>, <&k3_clks 151 7>;
			assigned-clock-parents = <&k3_clks 151 4>,	/* set REF_CLK to 20MHz i.e. PER0_PLL/48 */
						 <&k3_clks 151 9>;	/* set PIPE3_TXB_CLK to CLK_12M_RC/256 (for HS only) */

			/* TODO
			 * For SS, set PIPE3_TXB_CLK to WIZ8B2M4VSB serdes clk
			 */

			usb0: usb@10000 {
				compatible = "snps,dwc3";
				reg = <0x10000 0x10000>;
				interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
					     <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
					     <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
				interrupt-names = "peripheral",
						  "host",
						  "otg";
				maximum-speed = "high-speed";
				dr_mode = "otg";
				phys = <&usb0_phy>;
				phy-names = "usb2-phy";
			};
		};

		usb0_phy: phy@4100000 {
			compatible = "ti,am654-usb2", "ti,omap-usb2";
			reg = <0x0 0x4100000 0x0 0x54>;
			syscon-phy-power = <&scm_conf 0x4000>;
			clocks = <&k3_clks 151 0>, <&k3_clks 151 1>;
			clock-names = "wkupclk", "refclk";
			#phy-cells = <0>;
			status = "disabled";
		};

		dwc3_1: dwc3@4020000 {
			compatible = "ti,am654-dwc3";
			reg = <0x0 0x4020000 0x0 0x4000>;
			#address-cells = <1>;
			#size-cells = <1>;
			ranges = <0x0 0x0 0x4020000 0x20000>;
			interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
			dma-coherent;
			status = "disabled";
			power-domains = <&k3_pds 152>;
			assigned-clocks = <&k3_clks 152 2>;
			assigned-clock-parents = <&k3_clks 152 4>;	/* set REF_CLK to 20MHz i.e. PER0_PLL/48 */

			usb1: usb@10000 {
				compatible = "snps,dwc3";
				reg = <0x10000 0x10000>;
				interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
					     <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
					     <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
				interrupt-names = "peripheral",
						  "host",
						  "otg";
				maximum-speed = "high-speed";
				dr_mode = "otg";
				phys = <&usb1_phy>;
				phy-names = "usb2-phy";
			};
		};

		usb1_phy: phy@4110000 {
			compatible = "ti,am654-usb2", "ti,omap-usb2";
			reg = <0x0 0x4110000 0x0 0x54>;
			syscon-phy-power = <&scm_conf 0x4020>;
			clocks = <&k3_clks 152 0>, <&k3_clks 152 1>;
			clock-names = "wkupclk", "refclk";
			#phy-cells = <0>;
			status = "disabled";
		};

		fss: fss@47000000 {
			compatible = "simple-bus";
			#address-cells = <2>;
			#size-cells = <2>;
			ranges;

			ospi0: ospi@47040000 {
				compatible = "ti,am654-ospi", "cdns,qspi-nor";
				reg = <0x0 0x47040000 0x0 0x100>,
					<0x5 0x00000000 0x1 0x0000000>;
				interrupts = <GIC_SPI 552 IRQ_TYPE_LEVEL_HIGH>;
				cdns,fifo-depth = <256>;
				cdns,fifo-width = <4>;
				cdns,trigger-address = <0x50000000>;
				cdns,delay-elem-ps = <80>;
				clocks = <&k3_clks 55 5>;
				assigned-clocks = <&k3_clks 55 5>;
				assigned-clock-parents = <&k3_clks 55 7>;
				assigned-clock-rates = <166666666>;
				power-domains = <&k3_pds 55>;
				#address-cells = <1>;
				#size-cells = <0>;
				dma-coherent;
				status = "disabled";
			};

			ospi1: ospi@47050000 {
				compatible = "ti,am654-ospi", "cdns,qspi-nor";
				reg = <0x0 0x47050000 0x0 0x100>,
					<0x7 0x00000000 0x1 0x00000000>;
				interrupts = <GIC_SPI 553 IRQ_TYPE_LEVEL_HIGH>;
				cdns,fifo-depth = <256>;
				cdns,fifo-width = <4>;
				cdns,trigger-address = <0x58000000>;
				clocks = <&k3_clks 55 16>;
				power-domains = <&k3_pds 55>;
				#address-cells = <1>;
				#size-cells = <0>;
				dma-coherent;
				status = "disabled";
			};
		};

		cal: cal@6f03000 {
			compatible = "ti,am654-cal";
			reg = <0x0 0x06f03000 0x0 0x400>,
			      <0x0 0x06f03800 0x0 0x40>;
			reg-names = "cal_top",
				    "cal_rx_core0";
			interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
			syscon-camerrx = <&scm_conf 0x40c0>;
			#address-cells = <1>;
			#size-cells = <0>;
			clock-names = "fck";
			clocks = <&k3_clks 2 0>;
			power-domains = <&k3_pds 2>;
			status = "disabled";

			ports {
				#address-cells = <1>;
				#size-cells = <0>;

				csi2_0: port@0 {
					reg = <0>;
				};
			};
		};

		dss: dss@04a00000 {
			compatible = "ti,am6-dss";
			reg =	<0x0 0x04a00000 0x0 0x1000>, /* common */
				<0x0 0x04a02000 0x0 0x1000>, /* vidl1 */
				<0x0 0x04a06000 0x0 0x1000>, /* vid */
				<0x0 0x04a07000 0x0 0x1000>, /* ovr1 */
				<0x0 0x04a08000 0x0 0x1000>, /* ovr2 */
				<0x0 0x04a0a000 0x0 0x1000>, /* vp1 */
				<0x0 0x04a0b000 0x0 0x1000>; /* vp2 */
			reg-names = "common", "vidl1", "vid",
				"ovr1", "ovr2", "vp1", "vp2";

			syscon = <&scm_conf>;

			power-domains = <&k3_pds 67>;

			clocks =	<&k3_clks 67 1>,
					<&k3_clks 216 1>,
					<&k3_clks 67 2>;
			clock-names = "fck", "vp1", "vp2";

			/*
			 * Set vp2 clk (DPI_1_IN_CLK) mux to PLL4 via
			 * DIV1. See "Figure 12-3365. DSS Integration"
			 * in AM65x TRM for details.
			 */
			assigned-clocks = <&k3_clks 67 2>;
			assigned-clock-parents = <&k3_clks 67 5>;

			interrupts = <GIC_SPI 166 IRQ_TYPE_EDGE_RISING>;

			status = "disabled";

			dss_ports: ports {
				#address-cells = <1>;
				#size-cells = <0>;
			};
		};

		wkup_vtm0: wkup_vtm0@42050000 {
			compatible = "ti,am654-vtm";
			reg = <0x0 0x42050000 0x0 0x25c>;
			power-domains = <&k3_pds 80>;
			#thermal-sensor-cells = <1>;
		};

		thermal_zones: thermal-zones {
			#include "am654-industrial-thermal.dtsi"
		};

		tscadc0: tscadc@40200000 {
			compatible = "ti,am654-tscadc", "ti,am3359-tscadc";
			reg = <0x0 0x40200000 0x0 0x1000>;
			interrupts = <GIC_SPI 580 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&k3_clks 0 2>;
			assigned-clocks = <&k3_clks 0 2>;
			/* Set to 60MHz clock from MCUHSDIV_CLKOUT1 */
			assigned-clock-parents = <&k3_clks 0 4>;
			clock-names = "adc_tsc_fck";
			dmas = <&mcu_udmap &mcu_pdma0 0 UDMA_DIR_RX>,
			       <&mcu_udmap &mcu_pdma0 1 UDMA_DIR_RX>;
			dma-names = "fifo0", "fifo1";
			dma-coherent;
			status = "disabled";

			adc {
				#io-channel-cells = <1>;
				compatible = "ti,am654-adc", "ti,am3359-adc";
				dma-coherent;
			};
		};

		tscadc1: tscadc@40210000 {
			compatible = "ti,am654-tscadc", "ti,am3359-tscadc";
			reg = <0x0 0x40210000 0x0 0x1000>;
			interrupts = <GIC_SPI 581 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&k3_clks 1 2>;
			assigned-clocks = <&k3_clks 1 2>;
			/* Set to 60MHz clock from MCUHSDIV_CLKOUT1 */
			assigned-clock-parents = <&k3_clks 1 4>;
			clock-names = "adc_tsc_fck";
			dmas = <&mcu_udmap &mcu_pdma0 2 UDMA_DIR_RX>,
			       <&mcu_udmap &mcu_pdma0 3 UDMA_DIR_RX>;
			dma-names = "fifo0", "fifo1";
			dma-coherent;
			status = "disabled";

			adc {
				#io-channel-cells = <1>;
				compatible = "ti,am654-adc", "ti,am3359-adc";
				dma-coherent;
			};
		};

		mcu_spi0: spi@40300000 {
			compatible = "ti,am654-mcspi","ti,omap4-mcspi";
			reg = <0x0 0x40300000 0x0 0x400>;
			interrupts = <GIC_SPI 560 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&k3_clks 142 1>;
			power-domains = <&k3_pds 142>;
			#address-cells = <1>;
			#size-cells = <0>;
			status = "disabled";
		};

		mcu_spi1: spi@40310000 {
			compatible = "ti,am654-mcspi","ti,omap4-mcspi";
			reg = <0x0 0x40310000 0x0 0x400>;
			interrupts = <GIC_SPI 561 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&k3_clks 143 1>;
			power-domains = <&k3_pds 143>;
			#address-cells = <1>;
			#size-cells = <0>;
			status = "disabled";
		};

		mcu_spi2: spi@40320000 {
			compatible = "ti,am654-mcspi","ti,omap4-mcspi";
			reg = <0x0 0x40320000 0x0 0x400>;
			interrupts = <GIC_SPI 562 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&k3_clks 144 1>;
			power-domains = <&k3_pds 144>;
			#address-cells = <1>;
			#size-cells = <0>;
			status = "disabled";
		};

		main_spi0: spi@2100000 {
			compatible = "ti,am654-mcspi","ti,omap4-mcspi";
			reg = <0x0 0x2100000 0x0 0x400>;
			interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&k3_clks 137 1>;
			power-domains = <&k3_pds 137>;
			#address-cells = <1>;
			#size-cells = <0>;
			status = "disabled";
		};

		main_spi1: spi@2110000 {
			compatible = "ti,am654-mcspi","ti,omap4-mcspi";
			reg = <0x0 0x2110000 0x0 0x400>;
			interrupts = <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&k3_clks 138 1>;
			power-domains = <&k3_pds 138>;
			#address-cells = <1>;
			#size-cells = <0>;
			assigned-clocks = <&k3_clks 137 1>;
			assigned-clock-rates = <48000000>;
			status = "disabled";
		};

		main_spi2: spi@2120000 {
			compatible = "ti,am654-mcspi","ti,omap4-mcspi";
			reg = <0x0 0x2120000 0x0 0x400>;
			interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&k3_clks 139 1>;
			power-domains = <&k3_pds 139>;
			#address-cells = <1>;
			#size-cells = <0>;
			status = "disabled";
		};

		main_spi3: spi@2130000 {
			compatible = "ti,am654-mcspi","ti,omap4-mcspi";
			reg = <0x0 0x2130000 0x0 0x400>;
			interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&k3_clks 140 1>;
			power-domains = <&k3_pds 140>;
			#address-cells = <1>;
			#size-cells = <0>;
			status = "disabled";
		};

		main_spi4: spi@2140000 {
			compatible = "ti,am654-mcspi","ti,omap4-mcspi";
			reg = <0x0 0x2140000 0x0 0x400>;
			interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&k3_clks 141 1>;
			power-domains = <&k3_pds 141>;
			#address-cells = <1>;
			#size-cells = <0>;
			status = "disabled";
		};
	};
};