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author | Steve Kipisz | 2013-03-09 07:52:58 -0600 |
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committer | Tom Rini | 2013-03-08 11:42:20 -0600 |
commit | 5091e9a86ea034ded668d299e09c1d5dd2cb680c (patch) | |
tree | 7a6068ca2b62a4a675bf881f75a3790454369a8d | |
parent | 5e62f0491069d9d4d96845d50dd3f2847ad696a9 (diff) | |
download | ti-u-boot-5091e9a86ea034ded668d299e09c1d5dd2cb680c.tar.gz ti-u-boot-5091e9a86ea034ded668d299e09c1d5dd2cb680c.tar.xz ti-u-boot-5091e9a86ea034ded668d299e09c1d5dd2cb680c.zip |
am33xx:ddr:Fix config_sdram to work for all DDR
The original write to sdram_config is correct for DDR3 but incorrect
for DDR2 so SPL was hanging. For DDR2, the write to sdram_config
should be after the writes to ref_ctrl. This was working for DDR3
because there was a write of 0x2800 to ref_ctrl before a write
to sdram_config.
Tested on: GP EVM 1.1A (DDR2), GP EVM 1.5A (DDR3),
Beaglebone A6 (DDR2), Beagleone Blacd A4A (DDR3)
Signed-off-by: Steve Kipisz <s-kipisz2@ti.com>
-rw-r--r-- | arch/arm/cpu/armv7/am33xx/ddr.c | 5 |
1 files changed, 4 insertions, 1 deletions
diff --git a/arch/arm/cpu/armv7/am33xx/ddr.c b/arch/arm/cpu/armv7/am33xx/ddr.c index 448cc40157..7932a39e7c 100644 --- a/arch/arm/cpu/armv7/am33xx/ddr.c +++ b/arch/arm/cpu/armv7/am33xx/ddr.c | |||
@@ -54,10 +54,13 @@ void config_sdram(const struct emif_regs *regs) | |||
54 | writel(0x2800, &emif_reg->emif_sdram_ref_ctrl); | 54 | writel(0x2800, &emif_reg->emif_sdram_ref_ctrl); |
55 | writel(regs->zq_config, &emif_reg->emif_zq_config); | 55 | writel(regs->zq_config, &emif_reg->emif_zq_config); |
56 | writel(regs->sdram_config, &cstat->secure_emif_sdram_config); | 56 | writel(regs->sdram_config, &cstat->secure_emif_sdram_config); |
57 | writel(regs->sdram_config, &emif_reg->emif_sdram_config); | ||
58 | writel(regs->ref_ctrl, &emif_reg->emif_sdram_ref_ctrl); | ||
59 | writel(regs->ref_ctrl, &emif_reg->emif_sdram_ref_ctrl_shdw); | ||
57 | } | 60 | } |
58 | writel(regs->sdram_config, &emif_reg->emif_sdram_config); | ||
59 | writel(regs->ref_ctrl, &emif_reg->emif_sdram_ref_ctrl); | 61 | writel(regs->ref_ctrl, &emif_reg->emif_sdram_ref_ctrl); |
60 | writel(regs->ref_ctrl, &emif_reg->emif_sdram_ref_ctrl_shdw); | 62 | writel(regs->ref_ctrl, &emif_reg->emif_sdram_ref_ctrl_shdw); |
63 | writel(regs->sdram_config, &emif_reg->emif_sdram_config); | ||
61 | } | 64 | } |
62 | 65 | ||
63 | /** | 66 | /** |