author | James Hogan <james.hogan@imgtec.com> | |
Tue, 9 Oct 2012 09:54:43 +0000 (10:54 +0100) | ||
committer | James Hogan <james.hogan@imgtec.com> | |
Sat, 2 Mar 2013 20:09:45 +0000 (20:09 +0000) | ||
commit | ac919f0883e53d7785745566692c8a0620abd7ea | |
tree | 521a0b0ddcab5176a1998d0b7b9faefde6e3f0ae | tree | snapshot (tar.xz tar.gz zip) |
parent | a2c5d4ed92bbc02ff4a37efc2adffe7d145abe4f | commit | diff |
metag: Traps
Add trap code for metag. At the lowest level Meta traps (and return from
interrupt instruction - RTI) simply swap the PC and PCX registers and
optionally toggle the interrupt status bit (ISTAT). Low level TBX code
in tbipcx.S handles the core context save, determine the TBX signal
number based on the core trigger that fired (using the TXSTATI status
register), and call TBX signal handlers (mostly in traps.c) via a vector
table.
Signed-off-by: James Hogan <james.hogan@imgtec.com>
Cc: Al Viro <viro@zeniv.linux.org.uk>
Add trap code for metag. At the lowest level Meta traps (and return from
interrupt instruction - RTI) simply swap the PC and PCX registers and
optionally toggle the interrupt status bit (ISTAT). Low level TBX code
in tbipcx.S handles the core context save, determine the TBX signal
number based on the core trigger that fired (using the TXSTATI status
register), and call TBX signal handlers (mostly in traps.c) via a vector
table.
Signed-off-by: James Hogan <james.hogan@imgtec.com>
Cc: Al Viro <viro@zeniv.linux.org.uk>
arch/metag/include/asm/switch.h | [new file with mode: 0644] | blob |
arch/metag/include/asm/traps.h | [new file with mode: 0644] | blob |
arch/metag/kernel/kick.c | [new file with mode: 0644] | blob |
arch/metag/kernel/tbiunexp.S | [new file with mode: 0644] | blob |
arch/metag/kernel/traps.c | [new file with mode: 0644] | blob |