1 <counter_set name="ARM_ARM11MPCore_cnt" count="3"/>
2 <category name="ARM11MPCore" counter_set="ARM_ARM11MPCore_cnt" per_cpu="yes">
3 <event counter="ARM_ARM11MPCore_ccnt" title="Clock" name="Cycles" display="hertz" units="Hz" average_selection="yes" description="The number of core clock cycles"/>
4 <event event="0x00" title="Cache" name="Inst miss" description="Instruction cache miss to a cacheable location, which requires a fetch from external memory"/>
5 <event event="0x01" title="Pipeline" name="Instruction stall" description="Stall because instruction buffer cannot deliver an instruction"/>
6 <event event="0x02" title="Pipeline" name="Data stall" description="Stall because of a data dependency"/>
7 <event event="0x03" title="Cache" name="Inst micro TLB miss" description="Instruction MicroTLB miss (unused on ARM1156)"/>
8 <event event="0x04" title="Cache" name="Data micro TLB miss" description="Data MicroTLB miss (unused on ARM1156)"/>
9 <event event="0x05" title="Branch" name="Instruction executed" description="Branch instructions executed, branch might or might not have changed program flow"/>
10 <event event="0x06" title="Branch" name="Not predicted" description="Branch not predicted"/>
11 <event event="0x07" title="Branch" name="Mispredicted" description="Branch mispredicted"/>
12 <event event="0x08" title="Core" name="Instructions" description="Instructions executed"/>
13 <event event="0x09" title="Core" name="Folded Instructions" description="Folded instructions executed"/>
14 <event event="0x0a" title="Cache" name="Data read access" description="Data cache read access, not including cache operations"/>
15 <event event="0x0b" title="Cache" name="Data read miss" description="Data cache miss, not including Cache Operations"/>
16 <event event="0x0c" title="Cache" name="Data write access" description="Data cache write access"/>
17 <event event="0x0d" title="Cache" name="Data write miss" description="Data cache write miss"/>
18 <event event="0x0e" title="Cache" name="Data line eviction" description="Data cache line eviction, not including cache operations"/>
19 <event event="0x0f" title="Branch" name="PC change w/o mode change" description="Software changed the PC and there is not a mode change"/>
20 <event event="0x10" title="Cache " name="TLB miss" description="Main TLB miss"/>
21 <event event="0x11" title="External" name="External Memory request" description="External memory request (cache refill, noncachable, write-back)"/>
22 <event event="0x12" title="Cache" name="Stall" description="Stall because of Load Store Unit request queue being full"/>
23 <event event="0x13" title="Write Buffer" name="Drains" description="The number of times the Write Buffer was drained because of LSU ordering constraints or CP15 operations (Data Synchronization Barrier command) or Strongly Ordered operation"/>
24 <event event="0x14" title="Write Buffer" name="Write Merges" description="Buffered write merged in a store buffer slot"/>
25 <event event="0xFF" title="Core" name="Cycle counter" description="An increment each cycle"/>
26 </category>