1 <counter_set name="ARM_Cortex-A15_cntX">\r
2 <counter name="ARM_Cortex-A15_cnt0"/>\r
3 <counter name="ARM_Cortex-A15_cnt1"/>\r
4 <counter name="ARM_Cortex-A15_cnt2"/>\r
5 <counter name="ARM_Cortex-A15_cnt3"/>\r
6 <counter name="ARM_Cortex-A15_cnt4"/>\r
7 <counter name="ARM_Cortex-A15_cnt5"/>\r
8 </counter_set>\r
9 <category name="Cortex-A15" counter_set="ARM_Cortex-A15_cntX" per_cpu="yes" event_based_sampling="yes">\r
10 <event counter="ARM_Cortex-A15_ccnt" title="Clock" name="Cycles" description="The number of core clock cycles"/>\r
11 <event event="0x00" title="Software" name="Increment" description="Software increment architecturally executed"/>\r
12 <event event="0x01" title="Cache" name="Instruction refill" description="Instruction fetch that causes a refill of at least the level of instruction or unified cache closest to the processor"/>\r
13 <event event="0x02" title="Cache" name="Inst TLB refill" description="Instruction fetch that causes a TLB refill of at least the level of TLB closest to the processor"/>\r
14 <event event="0x03" title="Cache" name="Data refill" description="Memory Read or Write operation that causes a refill of at least the level of data or unified cache closest to the processor"/>\r
15 <event event="0x04" title="Cache" name="Data access" description="Memory Read or Write operation that causes a cache access to at least the level of data or unified cache closest to the processor"/>\r
16 <event event="0x05" title="Cache" name="Data TLB refill" description="Memory Read or Write operation that causes a TLB refill of at least the level of TLB closest to the processor"/>\r
17 <event event="0x08" title="Instruction" name="Executed" description="Instruction architecturally executed"/>\r
18 <event event="0x09" title="Exception" name="Taken" description="Exceptions taken"/>\r
19 <event event="0x0a" title="Exception" name="Return" description="Exception return architecturally executed"/>\r
20 <event event="0x0b" title="Instruction" name="CONTEXTIDR" description="Instruction that writes to the CONTEXTIDR architecturally executed"/>\r
21 <event event="0x10" title="Branch" name="Mispredicted" description="Branch mispredicted or not predicted"/>\r
22 <event event="0x11" title="Cycle" name="Cycle" description=""/>\r
23 <event event="0x12" title="Branch" name="Potential prediction" description="Branch or other change in program flow that could have been predicted by the branch prediction resources of the processor"/>\r
24 <event event="0x13" title="Memory" name="Memory access" description="Data memory access"/>\r
25 <event event="0x14" title="Cache" name="L1 inst access" description="Instruction cache access"/>\r
26 <event event="0x15" title="Cache" name="L1 data write" description="Level 1 data cache Write-Back"/>\r
27 <event event="0x16" title="Cache" name="L2 data access" description="Level 2 data cache access"/>\r
28 <event event="0x17" title="Cache" name="L2 data refill" description="Level 2 data cache refill"/>\r
29 <event event="0x18" title="Cache" name="L2 data write" description="Level 2 data cache Write-Back"/>\r
30 <event event="0x19" title="Bus" name="Access" description=""/>\r
31 <event event="0x1a" title="Memory" name="Error" description="Local memory error"/>\r
32 <event event="0x1b" title="Instruction" name="Speculative" description="Instruction speculatively executed"/>\r
33 <event event="0x1c" title="Memory" name="Translation table" description="Write to translation table base architecturally executed"/>\r
34 <event event="0x1d" title="Bus" name="Cycle" description=""/>\r
35 <event event="0x40" title="Cache" name="L1 data read" description="Level 1 data cache access - Read"/>\r
36 <event event="0x41" title="Cache" name="L1 data write" description="Level 1 data cache access - Write"/>\r
37 <event event="0x42" title="Cache" name="L1 data refill read" description="Level 1 data cache refill - Read"/>\r
38 <event event="0x43" title="Cache" name="L1 data refill write" description="Level 1 data cache refill - Write"/>\r
39 <event event="0x46" title="Cache" name="L1 data victim" description="Level 1 data cache Write-Back - Victim"/>\r
40 <event event="0x47" title="Cache" name="L1 data clean" description="Level 1 data cache Write-Back - Cleaning and coherency"/>\r
41 <event event="0x48" title="Cache" name="L1 data invalidate" description="Level 1 data cache invalidate"/>\r
42 <event event="0x4c" title="TLB" name="L1 data refill read" description="Level 1 data TLB refill - Read"/>\r
43 <event event="0x4d" title="TLB" name="L1 data refill write" description="Level 1 data TLB refill - Write"/>\r
44 <event event="0x50" title="Cache" name="L2 data read" description="Level 2 data cache access - Read"/>\r
45 <event event="0x51" title="Cache" name="L2 data write" description="Level 2 data cache access - Write"/>\r
46 <event event="0x52" title="Cache" name="L2 data refill read" description="Level 2 data cache refill - Read"/>\r
47 <event event="0x53" title="Cache" name="L2 data refill write" description="Level 2 data cache refill - Write"/>\r
48 <event event="0x56" title="Cache" name="L2 data victim" description="Level 2 data cache Write-Back - Victim"/>\r
49 <event event="0x57" title="Cache" name="L2 data clean" description="Level 2 data cache Write-Back - Cleaning and coherency"/>\r
50 <event event="0x58" title="Cache" name="L2 data invalidate" description="Level 2 data cache invalidate"/>\r
51 <event event="0x60" title="Bus" name="Read" description="Bus access - Read"/>\r
52 <event event="0x61" title="Bus" name="Write" description="Bus access - Write"/>\r
53 <event event="0x64" title="Bus" name="Access" description="Bus access - Normal"/>\r
54 <event event="0x65" title="Bus" name="Peripheral" description="Bus access - Peripheral"/>\r
55 <event event="0x66" title="Memory" name="Read" description="Data memory access - Read"/>\r
56 <event event="0x67" title="Memory" name="Write" description="Data memory access - Write"/>\r
57 <event event="0x68" title="Memory" name="Unaligned Read" description="Unaligned access - Read"/>\r
58 <event event="0x69" title="Memory" name="Unaligned Write" description="Unaligned access - Write"/>\r
59 <event event="0x6a" title="Memory" name="Unaligned" description="Unaligned access"/>\r
60 <event event="0x6c" title="Intrinsic" name="LDREX" description="Exclusive instruction speculatively executed - LDREX"/>\r
61 <event event="0x6d" title="Intrinsic" name="STREX pass" description="Exclusive instruction speculatively executed - STREX pass"/>\r
62 <event event="0x6e" title="Intrinsic" name="STREX fail" description="Exclusive instruction speculatively executed - STREX fail"/>\r
63 <event event="0x70" title="Instructions" name="Load" description="Instruction speculatively executed - Load"/>\r
64 <event event="0x71" title="Instructions" name="Store" description="Instruction speculatively executed - Store"/>\r
65 <event event="0x72" title="Instructions" name="Load/Store" description="Instruction speculatively executed - Load or store"/>\r
66 <event event="0x73" title="Instructions" name="Integer" description="Instruction speculatively executed - Integer data processing"/>\r
67 <event event="0x74" title="Instructions" name="Advanced SIMD" description="Instruction speculatively executed - Advanced SIMD"/>\r
68 <event event="0x75" title="Instructions" name="VFP" description="Instruction speculatively executed - VFP"/>\r
69 <event event="0x76" title="Instructions" name="Software change" description="Instruction speculatively executed - Software change of the PC"/>\r
70 <event event="0x78" title="Instructions" name="Immediate branch" description="Branch speculatively executed - Immediate branch"/>\r
71 <event event="0x79" title="Instructions" name="Procedure return" description="Branch speculatively executed - Procedure return"/>\r
72 <event event="0x7a" title="Instructions" name="Indirect branch" description="Branch speculatively executed - Indirect branch"/>\r
73 <event event="0x7c" title="Instructions" name="ISB" description="Barrier speculatively executed - ISB"/>\r
74 <event event="0x7d" title="Instructions" name="DSB" description="Barrier speculatively executed - DSB"/>\r
75 <event event="0x7e" title="Instructions" name="DMB" description="Barrier speculatively executed - DMB"/>\r
76 </category> \r